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61 Commits 4 Branches 32 Tags 7.4 MiB
Commit Graph

20 Commits

Author SHA1 Message Date
marqs 01b5fe20ee Sync and masking improvements 
* detect VSM=1 properly
* increase mask brightness
* add L2 optimized modes
* fix internal vsync alignment
 2017-05-18 23:36:37 +03:00
marqs 2c934c9dd0 Fix line3x 4:3 mode and VGA interlace detection 2017-02-09 23:14:24 +02:00
marqs 6e043ef577 Improve input mode handling 
* New options and better compatibility for Line5x
* Add support for 960i and 1080i
* Make TVP HPLL2x option user-selectable
 2017-02-07 23:04:30 +02:00
marqs 3b19b2843c Preliminary Line5x implementation 2017-01-29 13:02:12 +02:00
marqs d41c7522a0 Misc updates 
* Fix mask placement and make its brightness adjustable
* Line4x
 2017-01-24 00:18:15 +02:00
marqs 434186d64e Improve lo-res mode processing features 
* workaround for phase shift issue on optimized modes
* add hscale option for 256x240 opt Line3x mode
* distribute video modes to groups and allow passthru for all modes
 2017-01-23 00:56:17 +02:00
marqs d77c293b70 * Clean up some FPGA code 
* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
 2016-12-31 14:18:21 +02:00
marqs 03bf4c2c9a Update to Quartus 16.1. 2016-12-13 20:55:10 +02:00
marqs d548d53272 Add dedicated SPI mode option to i2c_opencores. 2016-11-05 15:39:36 +02:00
marqs 611c8763c2 Improve SD card IO. 2016-10-27 01:08:23 +03:00
marqs f55e9a877e SD SPI implementation finished 2016-10-21 01:19:53 +03:00
marqs 71d60144e8 Timer and SPI added. 2016-10-16 12:53:54 +03:00
marqs 9f086828ac Release 0.73 
* Fixed adv. timing tweaker using previous values when updating parameters
* Added "Hsync tolerance" option to fix detection of certain Neo-Geo models
 2016-09-05 20:49:41 +03:00
marqs 2dee0a2eb5 * R/G/B gain/offset controls added 
* misc optimizations
 2016-08-20 15:54:28 +03:00
marqs 827df7930f * L3 optimized mode scanlines fixed 
* Advanced timing tweaker implemented
 2016-08-16 22:45:23 +03:00
marqs a488422089 * Fix scanline rendering issues 
* Add initial input and SDTV sync glitch filter settings
* Modify input initialization logic
* Fix debug build warnings
 2016-08-14 18:57:50 +03:00
marqs c8b542b917 * 480p/576p line2x 
* 480i/576i passthrough
* alternating scanlines for interlaced material
 2016-07-09 23:12:35 +03:00
marqs c83653c880 Release 0.69 
* Improved remote control handling code
* Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal
* Fixed randomly missing blue channel at power-on when using DVI output mode
* Added H-PLL coast options
* Finer tuning range for scanline strength and mask
 2016-04-15 22:05:53 +03:00
marqs f502b2e46c Release 0.67. 
- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
 2016-03-27 23:09:31 +03:00
marqs 388c464f63 Initial public release (FW 0.64) 2016-02-23 01:03:50 +02:00