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Author	SHA1	Message	Date
Florian Reitz	ad4c2939b8	Smartport Control added	2018-05-24 09:44:21 +02:00
Florian Reitz	b62f7cfda0	All Smartport functions except Status and Control added	2018-05-23 22:17:19 +02:00
Florian Reitz	0910ca3db0	Smartport dispatcher added	2018-05-23 20:51:44 +02:00
Florian Reitz	457e8bff9c	Prepared for Smartport	2018-05-22 21:53:11 +02:00
Florian Reitz	31817a481c	Save zeropage in loop	2018-05-17 22:41:48 +02:00
Florian Reitz	515c19684e	ProDOS jump table moved	2018-05-17 22:41:24 +02:00
Florian Reitz	048d1df99a	Error codes added	2018-05-17 22:41:02 +02:00
Florian Reitz	2daaa107a0	Smartport.s added	2018-05-17 22:40:38 +02:00
Florian Reitz	fe9ae43e09	Test with phantom slots	2017-12-19 15:20:59 +01:00
Florian Reitz	06efc602c4	Merge branch 'devel'	2017-12-19 15:15:53 +01:00
Florian Reitz	13bfa30227	ProDOS functions moved to separate file ... Debug functions removed	2017-12-17 20:42:37 +01:00
Florian Reitz	f656800697	Updated to V1.1	2017-12-17 20:23:38 +01:00
Unknown	4cd6a76790	Fix for non-SDHC SDV2	2017-12-16 15:19:07 +01:00
Florian Reitz	4be091a1cb	Helper and include files added	2017-12-12 19:19:06 +01:00
Florian Reitz	0b33b5d385	Gerber for V1.1	2017-12-07 18:42:10 +01:00
Unknown	52852a3a07	Merge remote-tracking branch 'origin/master'	2017-12-02 00:46:58 +01:00
Unknown	05791c4e3d	Schematic PDF updated	2017-12-02 00:46:29 +01:00
Unknown	db0bf9dd5b	Schematic PDF updated	2017-12-01 15:05:22 +01:00
Florian Reitz	85687ed649	README.md updated	2017-12-01 14:26:18 +01:00
Florian Reitz	c93b63a92c	Skip boot added	2017-11-30 16:25:11 +01:00
Florian Reitz	331b84cc17	Change in makefile and folder structure	2017-11-30 13:00:06 +01:00
Unknown	2df245675d	Schematic updated	2017-11-30 12:14:54 +01:00
Florian Reitz	ab87f81ba8	Boot verified for IIgs, IIe 128k and IIe 64k	2017-11-29 01:20:44 +01:00
Florian Reitz	741624f3b5	IIgs boot working!!!	2017-11-26 21:26:15 +01:00
Florian Reitz	4feea40b5d	VS2015 project added	2017-11-26 00:19:35 +01:00
Florian Reitz	0f92b7cf03	Source updated for CC65	2017-11-25 23:23:25 +01:00
freitz85	505fe10434	SDHC flag added to CPLD	2017-11-25 19:42:33 +01:00
Florian Reitz	6517f86ce3	Load block 0 and 1 on boot	2017-11-20 19:13:16 +01:00
freitz85	9aa65960c4	SPI Mode 3	2017-11-01 16:50:56 +01:00
Florian Reitz	e9bd383d2e	Save and restore ZP locations ... Shorter read write loops	2017-11-01 16:22:35 +01:00
freitz85	cf98c54e77	Linear addressing from Cn00	2017-10-23 22:42:27 +02:00
Florian Reitz	b0df142692	Linear addressing from C700, test code added to ram	2017-10-22 20:50:14 +02:00
Florian Reitz	9e674fe0c6	Hex file for new address mapping	2017-10-17 00:06:33 +02:00
freitz85	c5945ff0ec	New address decoding	2017-10-16 22:53:41 +02:00
freitz85	b37df65a45	Test for old AddressDecoder	2017-10-16 22:01:41 +02:00
Unknown	f2314f838d	IRQ Pin removed, A11 added	2017-10-16 21:42:57 +02:00
freitz85	70def47cf2	More VDHL tests added	2017-10-15 20:58:33 +02:00
Florian Reitz	f20a1d529d	Test routine added	2017-10-15 16:48:13 +02:00
freitz85	723406657e	Fixes according to IIgs Tech Note #68	2017-10-13 23:04:38 +02:00
freitz85	eeb0b14725	AddressDecoder testbench	2017-10-12 20:37:37 +02:00
freitz85	819904bea2	Spi simulation working	2017-10-10 23:37:21 +02:00
freitz85	cc9d9d21db	Rename files	2017-10-10 22:57:47 +02:00
freitz85	7e2414c1bf	AddressDecoder in VHDL	2017-10-10 22:36:48 +02:00
freitz85	74c6b83b4e	Synthesis guards for debug signals	2017-10-10 21:58:22 +02:00
freitz85	2e4ebd9ac0	Test bench worst and best case timings	2017-10-10 21:22:18 +02:00
freitz85	8a6e7e647e	Test bench	2017-10-10 02:53:21 +02:00
freitz85	797993500e	Test bench added	2017-10-10 01:35:18 +02:00
freitz85	c03bc37834	Test bench	2017-10-10 00:41:31 +02:00
freitz85	caa40196d7	Removed BUFG constraint warnings	2017-10-09 23:35:52 +02:00
freitz85	b888590d11	Top level in VHDL	2017-10-09 22:35:47 +02:00