ed0821b322
Added CKE back
2021-04-18 20:24:58 -04:00
bfd262def7
Sorta works
2021-04-18 06:01:08 -04:00
8e35f6fc16
Remove CKE
2021-04-18 03:59:56 -04:00
4fd3d2ff3f
Make apple boot
...
Apple boots but SDRAM not working. Register R/W/increment works
2021-04-18 03:54:45 -04:00
a85863d0be
Create FrontIsom.png
2021-04-12 04:27:58 -04:00
32025498f8
Update RAM Map
2021-04-12 03:46:33 -04:00
d8a5dc069d
idk
2021-04-11 15:39:19 -04:00
fc2e875ac2
Works?
2021-04-03 03:44:42 -04:00
763861e444
ugh
2021-03-19 16:38:48 -04:00
e4bfc93b1f
before remove UFM
2021-03-19 14:23:33 -04:00
a336f5969b
hmm
2021-03-19 06:59:22 -04:00
4defba0f50
better
2021-03-19 06:45:31 -04:00
72851cefc5
ugh
2021-03-19 02:56:20 -04:00
686fac229e
idk
2021-03-15 13:40:59 -04:00
fdbc92725a
Remove old CPLD stuff
2021-03-15 13:40:41 -04:00
0a649d68ac
Fabbed
2021-02-17 19:29:24 -05:00
e2a3901004
reset button detect
2020-10-25 05:22:14 -04:00
312ef9354d
Board done?
2020-10-07 23:32:57 -04:00
13c6a59278
Sketch of verilog
2020-10-07 23:32:29 -04:00
089fee98b8
Update .gitignore
2020-05-15 22:51:14 -04:00
fbd98b8928
Update .gitignore
2020-05-15 18:49:20 -04:00
0ad3b4640a
Many changes
2020-03-10 18:54:44 -04:00
ac8cf35610
Put FullIOEN back
2020-02-26 03:37:20 -05:00
ef9b5852fb
Added transfer counters
2020-02-26 03:34:33 -05:00
fe0a092924
Added separate configuration section
2020-02-26 03:31:20 -05:00
490fcfb8e7
Cleanup
2020-02-26 03:15:36 -05:00
04be5a0257
Removed inhibit output
2020-02-26 03:14:33 -05:00
92cde65a9d
Moved REGEN and IOROMEN (no functional change)
2020-02-26 03:14:13 -05:00
a4f29ea751
Removed SetWR and FullIOEN
2020-02-26 02:13:35 -05:00
764b09ba6a
Comments, no actual changes to CPLD verilog
2020-02-16 22:03:57 -05:00
88a4169ab6
Fixed previous problem, working again
2020-02-16 00:11:12 -05:00
c5f1e637ac
Doesn't work but committing for posterity
2020-02-15 23:15:54 -05:00
c7cd1bb11e
Removed AVR-JTAG-10 connector footprint
2020-02-09 03:40:57 -05:00
6e6813786d
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
2020-01-26 15:15:07 -05:00
a2eecf4475
Separated CSDBEN
2020-01-26 15:13:37 -05:00
85e3eb627d
Removed state counter reset
2019-12-21 01:46:05 -05:00
3e06d30382
Fixed bugs in new PLD stuff
2019-10-20 22:41:24 -04:00
79dd794f45
New PLD revision
...
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00
21f18c14db
Recompiled just to be sure
2019-10-13 21:18:41 -04:00
4d12361823
Switch library location, fixed datasheet fields
2019-10-13 02:04:29 -04:00
1f0596291c
Update GR8RAM-render.png
2019-10-13 02:04:13 -04:00
4d8af3b074
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
2019-10-13 01:42:28 -04:00
1bf5ce4be3
New schematic revision
2019-10-13 01:40:49 -04:00
67399312b6
Register reset/initial values set syntax changed
2019-10-13 01:40:25 -04:00
a45778b440
Put gerber files back
2019-10-13 01:39:20 -04:00
cf16763591
24-bit counter, CAS fixed
2019-10-11 20:34:51 -04:00
2382fdfda6
Made AddrH high bit variable with mode input
2019-09-07 21:16:23 -04:00
b0a001aa58
Clarified assignments
2019-09-06 17:26:42 -04:00
7ccb2b670e
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
2019-09-05 13:50:40 -04:00
6dabfca306
added some disassembly of RamFactor
2019-09-05 13:50:38 -04:00
Zane Kaminski