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RAM2GS
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MAX, MachXO, MachXO2 working

This commit is contained in:
Zane Kaminski 2023-08-20 07:10:11 -04:00
parent 43e816b74c
commit a59177004e
545 changed files with 317413 additions and 205635 deletions
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5
CPLD/LCMXO2-640HC/.setting.ini
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@ -1,3 +1,4 @@
[General]
Export.auto_tasks=Jedecgen
PAR.auto_tasks=@@empty()
Export.auto_tasks=IBIS, TimingSimFileVlg, TimingSimFileVHD, Bitgen, Jedecgen
PAR.auto_tasks=PARTrace, IOTiming
Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile

3
CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf
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@ -9,6 +9,9 @@
<Source name="REFB.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="../RAM2GS-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>

2
CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf
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@ -1,2 +0,0 @@
BLOCK RESETPATHS;
BLOCK ASYNCPATHS;

136
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html
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@ -17,6 +17,142 @@ prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf
<A name="pn230816210353"></A><B><U><big>pn230816210353</big></U></B>
#Start recording tcl command: 8/16/2023 20:34:55
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Synthesis -impl impl1
prj_run Map -impl impl1
prj_run Export -impl impl1
prj_run PAR -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
prj_run Export -impl impl1
#Stop recording: 8/16/2023 21:03:53
<A name="pn230819062748"></A><B><U><big>pn230819062748</big></U></B>
#Start recording tcl command: 8/18/2023 08:16:23
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Synthesis -impl impl1
#Stop recording: 8/19/2023 06:27:48
<A name="pn230819062826"></A><B><U><big>pn230819062826</big></U></B>
#Start recording tcl command: 8/19/2023 06:27:54
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Synthesis -impl impl1 -task Synplify_Synthesis
#Stop recording: 8/19/2023 06:28:26
<A name="pn230819062853"></A><B><U><big>pn230819062853</big></U></B>
#Start recording tcl command: 8/19/2023 06:28:30
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Synthesis -impl impl1
prj_project close
#Stop recording: 8/19/2023 06:28:53
<A name="pn230819062900"></A><B><U><big>pn230819062900</big></U></B>
#Start recording tcl command: 8/19/2023 06:28:53
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_project close
#Stop recording: 8/19/2023 06:29:00
<A name="pn230819063021"></A><B><U><big>pn230819063021</big></U></B>
#Start recording tcl command: 8/19/2023 06:29:00
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
#Stop recording: 8/19/2023 06:30:21
<A name="pn230819205234"></A><B><U><big>pn230819205234</big></U></B>
#Start recording tcl command: 8/19/2023 06:30:42
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
pgr_program run
pgr_program run
pgr_program set -cable USB2
pgr_program set -port FTUSB-0
pgr_program run
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_run Export -impl impl1
prj_run Export -impl impl1
pgr_project close
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_project save
prj_project close
#Stop recording: 8/19/2023 20:52:34
<A name="pn230820055534"></A><B><U><big>pn230820055534</big></U></B>
#Start recording tcl command: 8/19/2023 21:54:38
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1 -forceAll
prj_project close
#Stop recording: 8/20/2023 05:55:34
<BR>
<BR>
<BR>

7
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062748.tcr Normal file
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@ -0,0 +1,7 @@
#Start recording tcl command: 8/18/2023 08:16:23
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Synthesis -impl impl1
#Stop recording: 8/19/2023 06:27:48

5
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062826.tcr Normal file
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@ -0,0 +1,5 @@
#Start recording tcl command: 8/19/2023 06:27:54
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Synthesis -impl impl1 -task Synplify_Synthesis
#Stop recording: 8/19/2023 06:28:26

6
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062853.tcr Normal file
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@ -0,0 +1,6 @@
#Start recording tcl command: 8/19/2023 06:28:30
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Synthesis -impl impl1
prj_project close
#Stop recording: 8/19/2023 06:28:53

5
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062900.tcr Normal file
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@ -0,0 +1,5 @@
#Start recording tcl command: 8/19/2023 06:28:53
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_project close
#Stop recording: 8/19/2023 06:29:00

4
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819063021.tcr Normal file
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@ -0,0 +1,4 @@
#Start recording tcl command: 8/19/2023 06:29:00
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
#Stop recording: 8/19/2023 06:30:21

47
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819205234.tcr Normal file
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@ -0,0 +1,47 @@
#Start recording tcl command: 8/19/2023 06:30:42
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
pgr_program run
pgr_program run
pgr_program set -cable USB2
pgr_program set -port FTUSB-0
pgr_program run
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_run Export -impl impl1
prj_run Export -impl impl1
pgr_project close
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_project save
prj_project close
#Stop recording: 8/19/2023 20:52:34

6
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055534.tcr Normal file
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@ -0,0 +1,6 @@
#Start recording tcl command: 8/19/2023 21:54:38
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1 -forceAll
prj_project close
#Stop recording: 8/20/2023 05:55:34

4
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055626.tcr Normal file
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@ -0,0 +1,4 @@
#Start recording tcl command: 8/20/2023 05:55:58
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
#Stop recording: 8/20/2023 05:56:26

10
CPLD/LCMXO2-640HC/REFB.edn
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@ -4,9 +4,9 @@
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2023 8 16 20 52 2)
(timestamp 2023 8 19 7 25 4)
(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ")
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 ")
(library ORCLIB
(edifLevel 0)
(technology
@ -287,9 +287,9 @@
(property UFM_INIT_FILE_FORMAT
(string "HEX"))
(property UFM_INIT_FILE_NAME
(string "NONE"))
(string "../RAM2GS-LCMXO2.mem"))
(property UFM_INIT_ALL_ZEROS
(string "ENABLED"))
(string "DISABLED"))
(property UFM_INIT_START_PAGE
(string "190"))
(property UFM_INIT_PAGES
@ -383,7 +383,7 @@
(property EFB_I2C1
(string "DISABLED"))
(property EFB_WB_CLK_FREQ
(string "62.5")))
(string "66.7")))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))

8
CPLD/LCMXO2-640HC/REFB.ipx
View File

@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 16 20:52:14.413" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 19 07:25:06.194" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
<Package>
<File name="REFB.lpc" type="lpc" modified="2023 08 16 20:52:02.825"/>
<File name="REFB.v" type="top_level_verilog" modified="2023 08 16 20:52:02.871"/>
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 16 20:52:02.871"/>
<File name="REFB.lpc" type="lpc" modified="2023 08 19 07:25:04.117"/>
<File name="REFB.v" type="top_level_verilog" modified="2023 08 19 07:25:04.191"/>
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 19 07:25:04.191"/>
</Package>
</DiamondModule>

12
CPLD/LCMXO2-640HC/REFB.lpc
View File

@ -16,8 +16,8 @@ CoreRevision=1.2
ModuleName=REFB
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=08/16/2023
Time=20:52:02
Date=08/19/2023
Time=07:25:04
[Parameters]
Verilog=1
@ -81,14 +81,14 @@ ufm2=0
ufm3=0
ufm_cfg0=0
ufm_cfg1=0
wb_clk_freq=62.5
wb_clk_freq=66.7
ufm_usage=SHARED_EBR_TAG
ufm_ebr=190
ufm_remain=
mem_size=1
ufm_start=
ufm_init=0
memfile=
ufm_init=mem
memfile=../RAM2GS-LCMXO2.mem
ufm_dt=hex
ufm0_ebr=
mem_size0=1
@ -138,4 +138,4 @@ t_wbport=0
t_portlock=0
[Command]
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640

4
CPLD/LCMXO2-640HC/REFB.srp
View File

@ -1,5 +1,5 @@
SCUBA, Version Diamond (64-bit) 3.12.1.454
Wed Aug 16 20:52:02 2023
Sat Aug 19 07:25:04 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -7,7 +7,7 @@ Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640
Circuit name : REFB
Module type : efb
Module Version : 1.2

10
CPLD/LCMXO2-640HC/REFB.v
View File

@ -1,7 +1,7 @@
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
/* Module Version: 1.2 */
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 */
/* Wed Aug 16 20:52:02 2023 */
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 */
/* Sat Aug 19 07:25:04 2023 */
`timescale 1 ns / 1 ps
@ -26,8 +26,8 @@ module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem" ;
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
defparam EFBInst_0.UFM_INIT_PAGES = 1 ;
defparam EFBInst_0.DEV_DENSITY = "640L" ;
@ -74,7 +74,7 @@ module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
defparam EFBInst_0.EFB_WB_CLK_FREQ = "62.5" ;
defparam EFBInst_0.EFB_WB_CLK_FREQ = "66.7" ;
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),

4
CPLD/LCMXO2-640HC/REFB_generate.log
View File

@ -3,7 +3,7 @@ Starting process: Module
Starting process:
SCUBA, Version Diamond (64-bit) 3.12.1.454
Wed Aug 16 20:52:02 2023
Sat Aug 19 07:25:04 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -13,7 +13,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640
Circuit name : REFB
Module type : efb
Module Version : 1.2

2
CPLD/LCMXO2-640HC/REFB_tmpl.v
View File

@ -1,6 +1,6 @@
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
/* Module Version: 1.2 */
/* Wed Aug 16 20:52:02 2023 */
/* Sat Aug 19 07:25:04 2023 */
/* parameterized module instance */
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),

65
CPLD/LCMXO2-640HC/impl1/.build_status
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@ -2,41 +2,54 @@
<BuildStatus>
<Strategy name="Strategy1">
<Milestone name="Export" build_result="0" build_time="0">
<Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692233986"/>
<Task name="IBIS" build_result="2" update_result="0" update_time="1692496517"/>
<Task name="TimingSimFileVlg" build_result="2" update_result="0" update_time="1692496519"/>
<Task name="TimingSimFileVHD" build_result="2" update_result="0" update_time="1692496520"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1692496523"/>
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692496527"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1692233977">
<Task name="Map" build_result="2" update_result="0" update_time="1692233977"/>
<Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
<Milestone name="Map" build_result="2" build_time="1692496497">
<Task name="Map" build_result="2" update_result="0" update_time="1692496497"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1692496498"/>
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1692496499"/>
<Task name="MapVHDLSimFile" build_result="2" update_result="0" update_time="1692496501"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1692233984">
<Task name="PAR" build_result="2" update_result="0" update_time="1692233984"/>
<Task name="PARTrace" build_result="0" update_result="3" update_time="0"/>
<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
<Milestone name="PAR" build_result="2" build_time="1692496511">
<Task name="PAR" build_result="2" update_result="0" update_time="1692496511"/>
<Task name="PARTrace" build_result="2" update_result="0" update_time="1692496511"/>
<Task name="IOTiming" build_result="2" update_result="0" update_time="1692496513"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1692233976">
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692233976"/>
<Milestone name="Synthesis" build_result="2" build_time="1692496496">
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692496496"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="0" update_result="2" update_time="1692233963"/>
<Task name="BKM" build_result="0" update_result="2" update_time="1692233963"/>
<Task name="HDLE" build_result="2" update_result="0" update_time="1692444754"/>
<Task name="BKM" build_result="0" update_result="2" update_time="1692444754"/>
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Translate" build_result="2" build_time="1692233976">
<Task name="Translate" build_result="2" update_result="0" update_time="1692233976"/>
<Milestone name="Translate" build_result="2" build_time="1692496497">
<Task name="Translate" build_result="2" update_result="0" update_time="1692496497"/>
</Milestone>
<Report name="LCMXO2_640HC_impl1.bgn" last_build_time="1692233986" last_build_size="4399"/>
<Report name="LCMXO2_640HC_impl1.edi" last_build_time="1692233975" last_build_size="204145"/>
<Report name="LCMXO2_640HC_impl1.jed" last_build_time="1692233986" last_build_size="177085"/>
<Report name="LCMXO2_640HC_impl1.ncd" last_build_time="1692233984" last_build_size="278109"/>
<Report name="LCMXO2_640HC_impl1.ngd" last_build_time="1692233976" last_build_size="207794"/>
<Report name="LCMXO2_640HC_impl1_map.ncd" last_build_time="1692233977" last_build_size="197654"/>
<Report name="IBIS/LCMXO2_640HC_impl1.ibs" last_build_time="1692496517" last_build_size="184928"/>
<Report name="LCMXO2_640HC_impl1.bgn" last_build_time="1692496527" last_build_size="4359"/>
<Report name="LCMXO2_640HC_impl1.bit" last_build_time="1692496523" last_build_size="6185"/>
<Report name="LCMXO2_640HC_impl1.edi" last_build_time="1692496494" last_build_size="198884"/>
<Report name="LCMXO2_640HC_impl1.ior" last_build_time="1692496513" last_build_size="6573"/>
<Report name="LCMXO2_640HC_impl1.jed" last_build_time="1692496527" last_build_size="177085"/>
<Report name="LCMXO2_640HC_impl1.ncd" last_build_time="1692496511" last_build_size="268674"/>
<Report name="LCMXO2_640HC_impl1.ngd" last_build_time="1692496497" last_build_size="204730"/>
<Report name="LCMXO2_640HC_impl1.tw1" last_build_time="1692496498" last_build_size="17550"/>
<Report name="LCMXO2_640HC_impl1.twr" last_build_time="1692496511" last_build_size="90277"/>
<Report name="LCMXO2_640HC_impl1_map.ncd" last_build_time="1692496497" last_build_size="193033"/>
<Report name="LCMXO2_640HC_impl1_mapvho.sdf" last_build_time="1692496501" last_build_size="164487"/>
<Report name="LCMXO2_640HC_impl1_mapvho.vho" last_build_time="1692496501" last_build_size="1365291"/>
<Report name="LCMXO2_640HC_impl1_mapvo.sdf" last_build_time="1692496499" last_build_size="163556"/>
<Report name="LCMXO2_640HC_impl1_mapvo.vo" last_build_time="1692496499" last_build_size="201461"/>
<Report name="LCMXO2_640HC_impl1_vho.sdf" last_build_time="1692496520" last_build_size="181438"/>
<Report name="LCMXO2_640HC_impl1_vho.vho" last_build_time="1692496520" last_build_size="1408234"/>
<Report name="LCMXO2_640HC_impl1_vo.sdf" last_build_time="1692496519" last_build_size="180465"/>
<Report name="LCMXO2_640HC_impl1_vo.vo" last_build_time="1692496519" last_build_size="212142"/>
</Strategy>
</BuildStatus>

3151
CPLD/LCMXO2-640HC/impl1/IBIS/LCMXO2_640HC_impl1.ibs Normal file
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2
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt
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@ -1,6 +1,6 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Wed Aug 16 20:59:46 2023 *
NOTE DATE CREATED: Sat Aug 19 21:55:27 2023 *
NOTE DESIGN NAME: RAM2GS *
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *

21
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr
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@ -1,7 +1,7 @@
----------------------------------------------------------------------
Report for cell RAM2GS.verilog
Register bits: 109 of 640 (17%)
Register bits: 111 of 640 (17%)
PIC Latch: 0
I/O cells: 63
Cell usage:
@ -9,34 +9,35 @@ I/O cells: 63
BB 8 100.0
CCU2D 10 100.0
EFB 1 100.0
FD1P3AX 27 100.0
FD1P3IX 3 100.0
FD1S3AX 51 100.0
FD1S3IX 3 100.0
FD1P3AX 28 100.0
FD1P3IX 2 100.0
FD1S3AX 52 100.0
FD1S3IX 4 100.0
GSR 1 100.0
IB 25 100.0
IFS1P3DX 9 100.0
INV 8 100.0
INV 6 100.0
OB 30 100.0
OFS1P3BX 4 100.0
OFS1P3DX 11 100.0
OFS1P3JX 1 100.0
ORCALUT4 206 100.0
PFUMX 1 100.0
ORCALUT4 199 100.0
PFUMX 3 100.0
PUR 1 100.0
VHI 2 100.0
VLO 2 100.0
SUB MODULES
REFB 1 100.0
TOTAL 405
TOTAL 400
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ufmefb
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
ORCALUT4 1 0.5
VHI 1 50.0
VLO 1 50.0
TOTAL 3
TOTAL 4

10
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn
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@ -4,10 +4,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:44 2023
Sat Aug 19 21:55:24 2023
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Command: bitgen -g RamCfg:Reset -path Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
Design name: RAM2GS
@ -81,6 +81,6 @@ UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 1 secs
Total REAL Time: 2 secs
Peak Memory Usage: 245 MB
Total CPU Time: 3 secs
Total REAL Time: 3 secs
Peak Memory Usage: 266 MB

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bit Normal file
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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.ncd
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4
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.pad
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@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Wed Aug 16 20:59:41 2023
Sat Aug 19 21:55:06 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -269,5 +269,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:42 2023
Sat Aug 19 21:55:09 2023

117
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par
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@ -1,9 +1,9 @@
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
Wed Aug 16 20:59:37 2023
Sat Aug 19 21:55:01 2023
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Preference file: LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
@ -28,45 +28,44 @@ Device utilization summary:
63+4(JTAG)/79 85% bonded
IOLOGIC 25/80 31% used
SLICE 117/320 36% used
SLICE 113/320 35% used
EFB 1/1 100% used
Number of Signals: 380
Number of Connections: 1008
Number of Signals: 374
Number of Connections: 978
Pin Constraint Summary:
63 out of 63 pins locked (100% locked).
The following 3 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 46)
PHI2_c (driver: PHI2, clk load #: 19)
RCLK_c (driver: RCLK, clk load #: 47)
PHI2_c (driver: PHI2, clk load #: 21)
nCRAS_c (driver: nCRAS, clk load #: 10)
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 2 signals are selected to use the secondary clock routing resources:
The following 1 signal is selected to use the secondary clock routing resources:
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
..............
............
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
...................
Placer score = 55012.
Finished Placer Phase 1. REAL time: 4 secs
....................
Placer score = 53481.
Finished Placer Phase 1. REAL time: 5 secs
Starting Placer Phase 2.
.
Placer score = 54994
Finished Placer Phase 2. REAL time: 4 secs
Placer score = 53406
Finished Placer Phase 2. REAL time: 5 secs
------------------ Clock Report ------------------
@ -78,14 +77,13 @@ Global Clock Resources:
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
PRIMARY : 3 out of 8 (37%)
SECONDARY: 2 out of 8 (25%)
SECONDARY: 1 out of 8 (12%)
--------------- End of Clock Report ---------------
@ -106,21 +104,18 @@ I/O Bank Usage Summary:
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Total placer CPU time: 5 secs
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 1008 unrouted.
0 connections routed; 978 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 8 secs
Completed router resource preassignment. Real time: 5 secs
Start NBR router at 20:59:43 08/16/23
Start NBR router at 21:55:09 08/19/23
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
@ -135,54 +130,41 @@ Note: NBR uses a different method to calculate timing slacks. The
your design.
*****************************************************************
Start NBR special constraint process at 20:59:43 08/16/23
Start NBR special constraint process at 21:55:09 08/19/23
Start NBR section for initial routing at 20:59:43 08/16/23
Start NBR section for initial routing at 21:55:10 08/19/23
Level 1, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
Level 2, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
Level 3, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
Level 4, iteration 1
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 20:59:43 08/16/23
Level 1, iteration 1
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
Start NBR section for normal routing at 21:55:10 08/19/23
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
Level 4, iteration 0
Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
Start NBR section for re-routing at 21:55:10 08/19/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs
Level 4, iteration 0
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Start NBR section for re-routing at 20:59:44 08/16/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs
Start NBR section for post-routing at 20:59:44 08/16/23
Start NBR section for post-routing at 21:55:10 08/19/23
End NBR router with 0 unrouted connection
@ -190,20 +172,17 @@ NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 4.922ns
Estimated worst slack<setup> : 6.966ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Total CPU time 6 secs
Total REAL time: 7 secs
Total CPU time 9 secs
Total REAL time: 9 secs
Completely routed.
End of route. 1008 routed (100.00%); 0 unrouted.
End of route. 978 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
@ -217,14 +196,14 @@ All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
par done!

17
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd
View File

@ -4,27 +4,22 @@ GLOBAL_PRIMARY_USED = 3;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_0_LOADNUM = 46;
GLOBAL_PRIMARY_0_LOADNUM = 47;
; Global primary clock #1
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_1_LOADNUM = 19;
GLOBAL_PRIMARY_1_LOADNUM = 21;
; Global primary clock #2
GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_2_LOADNUM = 10;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 2;
GLOBAL_SECONDARY_USED = 1;
; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = un1_wb_clk32_i;
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_0_SIGNALNAME = nCCAS_c;
GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
GLOBAL_SECONDARY_0_LOADNUM = 10;
GLOBAL_SECONDARY_0_SIGTYPE = CE;
; Global secondary clock #1
GLOBAL_SECONDARY_1_SIGNALNAME = nCCAS_c;
GLOBAL_SECONDARY_1_DRIVERTYPE = PIO;
GLOBAL_SECONDARY_1_LOADNUM = 10;
GLOBAL_SECONDARY_1_SIGTYPE = CLK;
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
; I/O Bank 0 Usage
BANK_0_USED = 13;
BANK_0_AVAIL = 19;

8
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par
View File

@ -4,11 +4,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:37 2023
Sat Aug 19 21:55:01 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Preference file: LCMXO2_640HC_impl1.prf.
@ -16,11 +16,11 @@ Preference file: LCMXO2_640HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 4.922 0 0.088 0 07 Completed
5_1 * 0 6.966 0 0.304 0 10 Completed
* : Design saved.
Total (real) run time for 1-seed: 7 secs
Total (real) run time for 1-seed: 10 secs
par done!

3026
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi
View File

File diff suppressed because it is too large Load Diff

752
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed
View File

@ -2,7 +2,7 @@
NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
NOTE All Rights Reserved.*
NOTE DATE CREATED: Wed Aug 16 20:59:44 2023*
NOTE DATE CREATED: Sat Aug 19 21:55:24 2023*
NOTE DESIGN NAME: LCMXO2_640HC_impl1.ncd*
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100*
NOTE JEDEC FILE STATUS: Final Version 1.95*
@ -75,385 +75,385 @@ QF171904*
G0*
F0*
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*
NOTE END CONFIG DATA*
L48128
L46720
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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@ -1425,10 +1425,10 @@ L171648
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
*
C5C3C*
CE650*
NOTE FEATURE_ROW*
E0000000000000000000000000000000000000000000000000000000000000000
0000010001100000*
NOTE User Electronic Signature Data*
UH00000000*
FF27
FC87

112
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp
View File

@ -7,28 +7,28 @@ Design Information
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document
s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
-lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf
Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
-lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -msgset
Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 08/16/23 20:59:36
Mapped on: 08/19/23 21:54:57
Design Summary
--------------
Number of registers: 109 out of 877 (12%)
PFU registers: 84 out of 640 (13%)
Number of registers: 111 out of 877 (13%)
PFU registers: 86 out of 640 (13%)
PIO registers: 25 out of 237 (11%)
Number of SLICEs: 117 out of 320 (37%)
SLICEs as Logic/ROM: 117 out of 320 (37%)
Number of SLICEs: 113 out of 320 (35%)
SLICEs as Logic/ROM: 113 out of 320 (35%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 10 out of 320 (3%)
Number of LUT4s: 230 out of 640 (36%)
Number used as logic LUTs: 210
Number of LUT4s: 222 out of 640 (35%)
Number used as logic LUTs: 202
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
@ -51,48 +51,46 @@ Design Summary
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 5
Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK )
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk )
Number of clocks: 4
Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 )
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 7
Net N_245_i: 1 loads, 1 LSLICEs
Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs
Number of Clock Enables: 6
Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs
Net XOR8MEG18: 6 loads, 6 LSLICEs
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
Page 1
Design: RAM2GS Date: 08/16/23 20:59:36
Design: RAM2GS Date: 08/19/23 21:54:57
Design Summary (cont)
---------------------
Net InitReady: 1 loads, 1 LSLICEs
Net un1_wb_clk32_i: 10 loads, 10 LSLICEs
Net N_18: 2 loads, 2 LSLICEs
Net XOR8MEG18: 3 loads, 3 LSLICEs
Net N_193_i: 2 loads, 2 LSLICEs
Net un1_wb_rst14_i: 9 loads, 9 LSLICEs
Net un1_FS_38_i: 2 loads, 2 LSLICEs
Net N_253_i: 2 loads, 2 LSLICEs
Number of LSRs: 5
Net RA10s_i: 1 loads, 0 LSLICEs
Net wb_clk23: 3 loads, 3 LSLICEs
Net wb_rst10: 3 loads, 3 LSLICEs
Net wb_rst: 1 loads, 0 LSLICEs
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net InitReady: 42 loads
Net FS[12]: 27 loads
Net FS[10]: 25 loads
Net FS[11]: 22 loads
Net FS[7]: 17 loads
Net FS[6]: 16 loads
Net Ready: 15 loads
Net InitReady: 33 loads
Net FS[13]: 22 loads
Net FS[12]: 21 loads
Net FS[14]: 20 loads
Net wb_rst11: 18 loads
Net FS[10]: 16 loads
Net Ready: 16 loads
Net FS[11]: 15 loads
Net FS[9]: 15 loads
Net Ready_fast: 14 loads
Net nRowColSel: 12 loads
Net S[1]: 12 loads
@ -125,6 +123,8 @@ IO (PIO) Attributes
| PHI2 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RDQMH | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 2
@ -132,12 +132,10 @@ IO (PIO) Attributes
Design: RAM2GS Date: 08/16/23 20:59:36
Design: RAM2GS Date: 08/19/23 21:54:57
IO (PIO) Attributes (cont)
--------------------------
| RDQMH | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRCAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRRAS | OUTPUT | LVCMOS33 | OUT |
@ -191,6 +189,8 @@ IO (PIO) Attributes (cont)
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 3
@ -198,12 +198,10 @@ IO (PIO) Attributes (cont)
Design: RAM2GS Date: 08/16/23 20:59:36
Design: RAM2GS Date: 08/19/23 21:54:57
IO (PIO) Attributes (cont)
--------------------------
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nFWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nCRAS | INPUT | LVCMOS33 | |
@ -257,6 +255,8 @@ IO (PIO) Attributes (cont)
| MAin[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 4
@ -264,12 +264,10 @@ IO (PIO) Attributes (cont)
Design: RAM2GS Date: 08/16/23 20:59:36
Design: RAM2GS Date: 08/19/23 21:54:57
IO (PIO) Attributes (cont)
--------------------------
| MAin[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[0] | INPUT | LVCMOS33 | |
@ -281,8 +279,8 @@ Removed logic
Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2
Signal InitReady_i was merged into signal InitReady
Signal XOR8MEG.CN was merged into signal PHI2_c
Signal XOR8MEG_3_u_0_am was merged into signal XOR8MEG
Signal GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped.
@ -324,18 +322,18 @@ Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Page 5
Design: RAM2GS Date: 08/16/23 20:59:36
Design: RAM2GS Date: 08/19/23 21:54:57
Removed logic (cont)
--------------------
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
@ -347,7 +345,6 @@ Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
@ -358,8 +355,8 @@ Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away.
Block wb_rst_RNO_0 was optimized away.
Block XOR8MEG.CN was optimized away.
Block XOR8MEG_3_u_0_am was optimized away.
Block GND was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.
@ -369,8 +366,8 @@ Block ufmefb/GND was optimized away.
Embedded Functional Block Connection Summary
--------------------------------------------
Desired WISHBONE clock frequency: 62.5 MHz
Clock source: wb_clk
Desired WISHBONE clock frequency: 66.7 MHz
Clock source: RCLK_c
Reset source: wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
@ -390,19 +387,19 @@ Embedded Functional Block Connection Summary
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Page 6
Design: RAM2GS Date: 08/16/23 20:59:36
Design: RAM2GS Date: 08/19/23 21:54:57
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 1 Pages (1*128 Bits)
Available General
Purpose Flash Memory: 191 Pages (191*128 Bits)
@ -425,7 +422,10 @@ Run Time and Memory Usage
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 37 MB
Peak Memory Usage: 57 MB

9
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mt Normal file
View File

@ -0,0 +1,9 @@
-v
1
-gt
-mapchkpnt 0
-sethld

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ncd
View File

Binary file not shown.

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngd
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Binary file not shown.

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngo
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Binary file not shown.

4
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad
View File

@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Wed Aug 16 20:59:41 2023
Sat Aug 19 21:55:06 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -269,5 +269,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:42 2023
Sat Aug 19 21:55:09 2023

125
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par
View File

@ -4,11 +4,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:37 2023
Sat Aug 19 21:55:01 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Preference file: LCMXO2_640HC_impl1.prf.
@ -16,21 +16,21 @@ Preference file: LCMXO2_640HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 4.922 0 0.088 0 07 Completed
5_1 * 0 6.966 0 0.304 0 10 Completed
* : Design saved.
Total (real) run time for 1-seed: 7 secs
Total (real) run time for 1-seed: 10 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
Wed Aug 16 20:59:37 2023
Sat Aug 19 21:55:01 2023
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Preference file: LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
@ -55,45 +55,44 @@ Device utilization summary:
63+4(JTAG)/79 85% bonded
IOLOGIC 25/80 31% used
SLICE 117/320 36% used
SLICE 113/320 35% used
EFB 1/1 100% used
Number of Signals: 380
Number of Connections: 1008
Number of Signals: 374
Number of Connections: 978
Pin Constraint Summary:
63 out of 63 pins locked (100% locked).
The following 3 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 46)
PHI2_c (driver: PHI2, clk load #: 19)
RCLK_c (driver: RCLK, clk load #: 47)
PHI2_c (driver: PHI2, clk load #: 21)
nCRAS_c (driver: nCRAS, clk load #: 10)
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 2 signals are selected to use the secondary clock routing resources:
The following 1 signal is selected to use the secondary clock routing resources:
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
..............
............
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
...................
Placer score = 55012.
Finished Placer Phase 1. REAL time: 4 secs
....................
Placer score = 53481.
Finished Placer Phase 1. REAL time: 5 secs
Starting Placer Phase 2.
.
Placer score = 54994
Finished Placer Phase 2. REAL time: 4 secs
Placer score = 53406
Finished Placer Phase 2. REAL time: 5 secs
------------------ Clock Report ------------------
@ -105,14 +104,13 @@ Global Clock Resources:
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
PRIMARY : 3 out of 8 (37%)
SECONDARY: 2 out of 8 (25%)
SECONDARY: 1 out of 8 (12%)
--------------- End of Clock Report ---------------
@ -133,21 +131,18 @@ I/O Bank Usage Summary:
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Total placer CPU time: 5 secs
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 1008 unrouted.
0 connections routed; 978 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 8 secs
Completed router resource preassignment. Real time: 5 secs
Start NBR router at 20:59:43 08/16/23
Start NBR router at 21:55:09 08/19/23
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
@ -162,54 +157,41 @@ Note: NBR uses a different method to calculate timing slacks. The
your design.
*****************************************************************
Start NBR special constraint process at 20:59:43 08/16/23
Start NBR special constraint process at 21:55:09 08/19/23
Start NBR section for initial routing at 20:59:43 08/16/23
Start NBR section for initial routing at 21:55:10 08/19/23
Level 1, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
Level 2, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
Level 3, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
Level 4, iteration 1
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 20:59:43 08/16/23
Level 1, iteration 1
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
Start NBR section for normal routing at 21:55:10 08/19/23
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
Level 4, iteration 0
Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
Start NBR section for re-routing at 21:55:10 08/19/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs
Level 4, iteration 0
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Start NBR section for re-routing at 20:59:44 08/16/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs
Start NBR section for post-routing at 20:59:44 08/16/23
Start NBR section for post-routing at 21:55:10 08/19/23
End NBR router with 0 unrouted connection
@ -217,20 +199,17 @@ NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 4.922ns
Estimated worst slack<setup> : 6.966ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Total CPU time 6 secs
Total REAL time: 7 secs
Total CPU time 9 secs
Total REAL time: 9 secs
Completely routed.
End of route. 1008 routed (100.00%); 0 unrouted.
End of route. 978 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
@ -244,14 +223,14 @@ All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
par done!

2
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf
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@ -1,5 +1,5 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srd
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579
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf
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579
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BIN
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2
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.t2b
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@ -2,4 +2,4 @@
-g RamCfg:Reset
-path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC"
-path "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC"

423
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.tw1 Normal file
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@ -0,0 +1,423 @@
Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sat Aug 19 21:54:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1_map.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[2] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
Constraint Details:
9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
Physical Path Details:
Data path Din[2]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c)
ROUTE 1 e 1.234 *n[2]_MGIOL.IN to SLICE_37.A1 Bank[2]
CTOF_DEL --- 0.495 SLICE_37.A1 to SLICE_37.F1 SLICE_37
ROUTE 1 e 1.234 SLICE_37.F1 to SLICE_94.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
ROUTE 2 e 1.234 SLICE_94.F0 to SLICE_90.D0 N_304
CTOF_DEL --- 0.495 SLICE_90.D0 to SLICE_90.F0 SLICE_90
ROUTE 5 e 1.234 SLICE_90.F0 to SLICE_91.C1 C1WR_7
CTOF_DEL --- 0.495 SLICE_91.C1 to SLICE_91.F1 SLICE_91
ROUTE 2 e 1.234 SLICE_91.F1 to SLICE_10.B0 un1_ADWR
CTOF_DEL --- 0.495 SLICE_10.B0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
--------
9.223 (33.1% logic, 66.9% route), 6 logic levels.
Report: 53.254MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.226ns
The internal maximum frequency of the following component is 102.312 MHz
Logical Details: Cell type Pin name Component name
Destination: EFB WBCLKI ufmefb/EFBInst_0
Delay: 9.774ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 6.270ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[0] (from RCLK_c +)
Destination: FF Data in nRCS_0io (to RCLK_c +)
Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
Constraint Details:
9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets
16.000ns delay constraint less
0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns
Physical Path Details:
Data path SLICE_16 to nRCS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
ROUTE 9 e 1.234 SLICE_16.Q0 to SLICE_45.A0 CO0
CTOF_DEL --- 0.495 SLICE_45.A0 to SLICE_45.F0 SLICE_45
ROUTE 4 e 0.480 SLICE_45.F0 to SLICE_45.A1 N_41
CTOF_DEL --- 0.495 SLICE_45.A1 to SLICE_45.F1 SLICE_45
ROUTE 2 e 1.234 SLICE_45.F1 to SLICE_77.D0 nRRAS_5_u_i_0
CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_117.B1 N_25
CTOF_DEL --- 0.495 SLICE_117.B1 to SLICE_117.F1 SLICE_117
ROUTE 1 e 1.234 SLICE_117.F1 to SLICE_88.C1 N_28_i_sn
CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
ROUTE 1 e 1.234 SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c)
--------
9.577 (30.6% logic, 69.4% route), 6 logic levels.
Report: 102.312MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Sat Aug 19 21:54:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1_map.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
================================================================================
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_12 to SLICE_12 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

2219
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.twr Normal file
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File diff suppressed because it is too large Load Diff

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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html
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@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:58:50 2023
Sat Aug 19 21:55:24 2023
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Command: bitgen -g RamCfg:Reset -path Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
Design name: RAM2GS
@ -91,9 +91,9 @@ UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 1 secs
Total REAL Time: 2 secs
Peak Memory Usage: 246 MB
Total CPU Time: 3 secs
Total REAL Time: 3 secs
Peak Memory Usage: 266 MB

16
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt
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@ -9,16 +9,16 @@ Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEPC
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Wed Aug 16 20:59:31 2023
# Written on Sat Aug 19 21:54:51 2023
##### DESIGN INFO #######################################################
Top View: "RAM2GS"
Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
@ -50,11 +50,11 @@ nCRAS RCLK | No paths | No paths | No p
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
Unconstrained Start/End Points

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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt.db
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<title>syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm log file</title>
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<frameset cols="20%, 80%">
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<frame src="syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm" name="srrFrame"/>
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<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 5
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 6
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: M
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
// Design: RAM2GS
// Package: TQFP100
// ncd File: lcmxo2_640hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Sat Aug 19 21:55:13 2023
// M: Minimum Performance Grade
// iotiming LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
I/O Timing Report (All units are in ns)
Worst Case Results across Performance Grades (M, 6, 5, 4):
// Input Setup and Hold Times
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
CROW[0] nCRAS F 2.553 4 -0.117 M
CROW[1] nCRAS F 2.019 4 0.001 M
Din[0] PHI2 F 4.715 4 3.636 4
Din[0] nCCAS F 0.790 4 0.535 4
Din[1] PHI2 F 5.021 4 3.516 4
Din[1] nCCAS F 1.086 4 0.264 4
Din[2] PHI2 F 3.385 4 3.516 4
Din[2] nCCAS F 0.282 4 0.948 4
Din[3] PHI2 F 4.644 4 3.516 4
Din[3] nCCAS F 1.278 4 0.095 4
Din[4] PHI2 F 4.335 4 3.516 4
Din[4] nCCAS F 2.446 4 -0.199 M
Din[5] PHI2 F 3.662 4 3.516 4
Din[5] nCCAS F 0.907 4 0.402 4
Din[6] PHI2 F 4.869 4 3.636 4
Din[6] nCCAS F 1.378 4 0.023 M
Din[7] PHI2 F 4.138 4 3.636 4
Din[7] nCCAS F 2.072 4 -0.120 M
MAin[0] PHI2 F 5.613 4 0.006 M
MAin[0] nCRAS F 0.244 4 1.146 4
MAin[1] PHI2 F 3.409 4 0.354 6
MAin[1] nCRAS F 0.244 4 1.146 4
MAin[2] PHI2 F 5.391 4 0.132 M
MAin[2] nCRAS F 0.250 4 1.141 4
MAin[3] PHI2 F 4.627 4 0.087 M
MAin[3] nCRAS F 0.507 4 0.910 4
MAin[4] PHI2 F 5.665 4 -0.133 M
MAin[4] nCRAS F 0.675 4 0.777 4
MAin[5] PHI2 F 5.569 4 0.129 M
MAin[5] nCRAS F 0.050 4 1.238 4
MAin[6] PHI2 F 5.717 4 -0.141 M
MAin[6] nCRAS F 0.242 4 1.146 4
MAin[7] PHI2 F 5.943 4 -0.173 M
MAin[7] nCRAS F 0.170 4 1.228 4
MAin[8] nCRAS F 0.759 4 0.696 4
MAin[9] nCRAS F 0.516 4 0.891 4
PHI2 RCLK R -0.312 M 3.167 4
nCCAS RCLK R 2.600 4 -0.176 M
nCCAS nCRAS F 3.106 4 -0.235 M
nCRAS RCLK R 1.803 4 -0.055 M
nFWE PHI2 F 4.680 4 0.261 M
nFWE nCRAS F 2.234 4 1.143 4
// Clock to Output Delay
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
LED RCLK R 9.922 4 2.878 M
LED nCRAS F 10.555 4 3.057 M
RA[0] RCLK R 11.638 4 3.406 M
RA[0] nCRAS F 11.771 4 3.430 M
RA[10] RCLK R 8.141 4 2.620 M
RA[11] PHI2 R 8.610 4 2.756 M
RA[1] RCLK R 11.674 4 3.407 M
RA[1] nCRAS F 10.635 4 3.155 M
RA[2] RCLK R 12.933 4 3.729 M
RA[2] nCRAS F 11.858 4 3.449 M
RA[3] RCLK R 12.587 4 3.664 M
RA[3] nCRAS F 11.255 4 3.298 M
RA[4] RCLK R 11.721 4 3.433 M
RA[4] nCRAS F 11.153 4 3.297 M
RA[5] RCLK R 12.544 4 3.620 M
RA[5] nCRAS F 11.480 4 3.360 M
RA[6] RCLK R 12.984 4 3.775 M
RA[6] nCRAS F 11.528 4 3.407 M
RA[7] RCLK R 12.553 4 3.625 M
RA[7] nCRAS F 11.610 4 3.368 M
RA[8] RCLK R 11.836 4 3.453 M
RA[8] nCRAS F 10.797 4 3.201 M
RA[9] RCLK R 11.182 4 3.271 M
RA[9] nCRAS F 11.135 4 3.279 M
RBA[0] nCRAS F 8.439 4 2.703 M
RBA[1] nCRAS F 8.439 4 2.703 M
RCKE RCLK R 10.083 4 3.081 M
RDQMH RCLK R 11.381 4 3.325 M
RDQML RCLK R 10.735 4 3.173 M
RD[0] nCCAS F 8.223 4 2.594 M
RD[1] nCCAS F 8.223 4 2.594 M
RD[2] nCCAS F 8.223 4 2.594 M
RD[3] nCCAS F 8.223 4 2.594 M
RD[4] nCCAS F 8.223 4 2.594 M
RD[5] nCCAS F 8.223 4 2.594 M
RD[6] nCCAS F 8.223 4 2.594 M
RD[7] nCCAS F 8.223 4 2.594 M
nRCAS RCLK R 8.141 4 2.620 M
nRCS RCLK R 8.141 4 2.620 M
nRRAS RCLK R 8.141 4 2.620 M
nRWE RCLK R 8.121 4 2.627 M
WARNING: you must also run trce with hold speed: 4
WARNING: you must also run trce with hold speed: 6
WARNING: you must also run trce with setup speed: M
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4
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd
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@ -3,9 +3,9 @@ Device = LCMXO2-640HC;
Package = TQFP100;
Performance = 4;
LUTS_avail = 640;
LUTS_used = 230;
LUTS_used = 222;
FF_avail = 719;
FF_used = 109;
FF_used = 111;
INPUT_LVCMOS33 = 25;
OUTPUT_LVCMOS33 = 30;
BIDI_LVCMOS33 = 8;

5
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam
View File

@ -1,8 +1,8 @@
[ START MERGED ]
RASr2_i RASr2
XOR8MEG.CN PHI2_c
XOR8MEG_3_u_0_am XOR8MEG
nCRAS_c_i nCRAS_c
InitReady_i InitReady
[ END MERGED ]
[ START CLIPPED ]
GND
@ -59,7 +59,6 @@ ufmefb/PLL1STBO
ufmefb/PLL0STBO
ufmefb/PLLRSTO
ufmefb/PLLCLKO
ufmefb/wb_ack_o
ufmefb/wb_dat_o_1[2]
ufmefb/wb_dat_o_1[3]
ufmefb/wb_dat_o_1[4]
@ -71,7 +70,7 @@ N_1
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;

10
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr
View File

@ -3,18 +3,20 @@ Report for cell RAM2GS
Instance path: RAM2GS
Cell usage:
cell count Res Usage(%)
SLIC 117.00 100.0
SLIC 113.00 100.0
IOLGC 25.00 100.0
LUT4 210.00 100.0
LUT4 202.00 100.0
IOREG 25 100.0
IOBUF 63 100.0
PFUREG 84 100.0
PFUREG 86 100.0
RIPPLE 10 100.0
SUB MODULES
cell count SLC Usage(%)
REFB 1 0.0
REFB 1 0.4
---------------------------------------------------
Report for cell REFB
Instance path: RAM2GS/ufmefb
Cell usage:
cell count Res Usage(%)
SLIC 0.50 0.4
LUT4 1.00 0.5

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.ncd
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Binary file not shown.

4384
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvho.sdf Normal file
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File diff suppressed because it is too large Load Diff

36590
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvho.vho Normal file
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File diff suppressed because it is too large Load Diff

4384
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.sdf Normal file
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File diff suppressed because it is too large Load Diff

5552
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.vo Normal file
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File diff suppressed because it is too large Load Diff

88
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html
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@ -15,27 +15,27 @@
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document
s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
-lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf
Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
-lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -msgset
Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 08/16/23 20:59:36
Mapped on: 08/19/23 21:54:57
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 109 out of 877 (12%)
PFU registers: 84 out of 640 (13%)
Number of registers: 111 out of 877 (13%)
PFU registers: 86 out of 640 (13%)
PIO registers: 25 out of 237 (11%)
Number of SLICEs: 117 out of 320 (37%)
SLICEs as Logic/ROM: 117 out of 320 (37%)
Number of SLICEs: 113 out of 320 (35%)
SLICEs as Logic/ROM: 113 out of 320 (35%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 10 out of 320 (3%)
Number of LUT4s: 230 out of 640 (36%)
Number used as logic LUTs: 210
Number of LUT4s: 222 out of 640 (35%)
Number used as logic LUTs: 202
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
@ -58,39 +58,37 @@ Mapped on: 08/16/23 20:59:36
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 5
Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK )
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk )
Number of clocks: 4
Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 )
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 7
Net N_245_i: 1 loads, 1 LSLICEs
Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs
Number of Clock Enables: 6
Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs
Net XOR8MEG18: 6 loads, 6 LSLICEs
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
Net InitReady: 1 loads, 1 LSLICEs
Net un1_wb_clk32_i: 10 loads, 10 LSLICEs
Net N_18: 2 loads, 2 LSLICEs
Net XOR8MEG18: 3 loads, 3 LSLICEs
Net N_193_i: 2 loads, 2 LSLICEs
Net un1_wb_rst14_i: 9 loads, 9 LSLICEs
Net un1_FS_38_i: 2 loads, 2 LSLICEs
Net N_253_i: 2 loads, 2 LSLICEs
Number of LSRs: 5
Net RA10s_i: 1 loads, 0 LSLICEs
Net wb_clk23: 3 loads, 3 LSLICEs
Net wb_rst10: 3 loads, 3 LSLICEs
Net wb_rst: 1 loads, 0 LSLICEs
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net InitReady: 42 loads
Net FS[12]: 27 loads
Net FS[10]: 25 loads
Net FS[11]: 22 loads
Net FS[7]: 17 loads
Net FS[6]: 16 loads
Net Ready: 15 loads
Net InitReady: 33 loads
Net FS[13]: 22 loads
Net FS[12]: 21 loads
Net FS[14]: 20 loads
Net wb_rst11: 18 loads
Net FS[10]: 16 loads
Net Ready: 16 loads
Net FS[11]: 15 loads
Net FS[9]: 15 loads
Net Ready_fast: 14 loads
Net nRowColSel: 12 loads
Net S[1]: 12 loads
@ -127,9 +125,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RDQMH | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRCAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRRAS | OUTPUT | LVCMOS33 | OUT |
@ -184,9 +182,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nFWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nCRAS | INPUT | LVCMOS33 | |
@ -241,9 +239,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[0] | INPUT | LVCMOS33 | |
@ -256,8 +254,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2
Signal InitReady_i was merged into signal InitReady
Signal XOR8MEG.CN was merged into signal PHI2_c
Signal XOR8MEG_3_u_0_am was merged into signal XOR8MEG
Signal GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped.
@ -299,9 +297,9 @@ Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
@ -313,7 +311,6 @@ Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
@ -324,8 +321,8 @@ Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away.
Block wb_rst_RNO_0 was optimized away.
Block XOR8MEG.CN was optimized away.
Block XOR8MEG_3_u_0_am was optimized away.
Block GND was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.
@ -336,8 +333,8 @@ Block ufmefb/GND was optimized away.
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
Desired WISHBONE clock frequency: 62.5 MHz
Clock source: wb_clk
Desired WISHBONE clock frequency: 66.7 MHz
Clock source: RCLK_c
Reset source: wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
@ -357,10 +354,10 @@ Block ufmefb/GND was optimized away.
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 1 Pages (1*128 Bits)
Available General
Purpose Flash Memory: 191 Pages (191*128 Bits)
@ -387,7 +384,10 @@ Instance Name: ufmefb/EFBInst_0
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 37 MB
Peak Memory Usage: 57 MB

4
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html
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@ -14,7 +14,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Wed Aug 16 20:59:41 2023
Sat Aug 19 21:55:06 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -278,7 +278,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:42 2023
Sat Aug 19 21:55:09 2023

125
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html
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@ -12,11 +12,11 @@ Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:37 2023
Sat Aug 19 21:55:01 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Preference file: LCMXO2_640HC_impl1.prf.
@ -25,22 +25,22 @@ Preference file: LCMXO2_640HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 4.922 0 0.088 0 07 Completed
5_1 * 0 6.966 0 0.304 0 10 Completed
* : Design saved.
Total (real) run time for 1-seed: 7 secs
Total (real) run time for 1-seed: 10 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;LCMXO2_640HC_impl1_map.ncd&quot;
Wed Aug 16 20:59:37 2023
Sat Aug 19 21:55:01 2023
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Preference file: LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
@ -66,45 +66,44 @@ Ignore Preference Error(s): True
63+4(JTAG)/79 85% bonded
IOLOGIC 25/80 31% used
SLICE 117/320 36% used
SLICE 113/320 35% used
EFB 1/1 100% used
Number of Signals: 380
Number of Connections: 1008
Number of Signals: 374
Number of Connections: 978
Pin Constraint Summary:
63 out of 63 pins locked (100% locked).
The following 3 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 46)
PHI2_c (driver: PHI2, clk load #: 19)
RCLK_c (driver: RCLK, clk load #: 47)
PHI2_c (driver: PHI2, clk load #: 21)
nCRAS_c (driver: nCRAS, clk load #: 10)
WARNING - par: Signal &quot;RCLK_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;RCLK&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal &quot;PHI2_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;PHI2&quot; is located at &quot;8&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal &quot;nCRAS_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;nCRAS&quot; is located at &quot;17&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 2 signals are selected to use the secondary clock routing resources:
The following 1 signal is selected to use the secondary clock routing resources:
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
WARNING - par: Signal &quot;nCCAS_c&quot; is selected to use Secondary clock resources. However, its driver comp &quot;nCCAS&quot; is located at &quot;9&quot;, which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
..............
............
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
...................
Placer score = 55012.
Finished Placer Phase 1. REAL time: 4 secs
....................
Placer score = 53481.
Finished Placer Phase 1. REAL time: 5 secs
Starting Placer Phase 2.
.
Placer score = 54994
Finished Placer Phase 2. REAL time: 4 secs
Placer score = 53406
Finished Placer Phase 2. REAL time: 5 secs
@ -117,14 +116,13 @@ Global Clock Resources:
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 46
PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;8 (PL3B)&quot;, clk load = 19
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 47
PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;8 (PL3B)&quot;, clk load = 21
PRIMARY &quot;nCRAS_c&quot; from comp &quot;nCRAS&quot; on PIO site &quot;17 (PL6B)&quot;, clk load = 10
SECONDARY &quot;nCCAS_c&quot; from comp &quot;nCCAS&quot; on PIO site &quot;9 (PL3C)&quot;, clk load = 8, ce load = 0, sr load = 0
SECONDARY &quot;un1_wb_clk32_i&quot; from F0 on comp &quot;SLICE_103&quot; on site &quot;R6C8B&quot;, clk load = 0, ce load = 10, sr load = 0
PRIMARY : 3 out of 8 (37%)
SECONDARY: 2 out of 8 (25%)
SECONDARY: 1 out of 8 (12%)
@ -145,21 +143,18 @@ I/O Bank Usage Summary:
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Total placer CPU time: 5 secs
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 1008 unrouted.
0 connections routed; 978 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 8 secs
Completed router resource preassignment. Real time: 5 secs
Start NBR router at 20:59:43 08/16/23
Start NBR router at 21:55:09 08/19/23
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
@ -174,54 +169,41 @@ Note: NBR uses a different method to calculate timing slacks. The
your design.
*****************************************************************
Start NBR special constraint process at 20:59:43 08/16/23
Start NBR special constraint process at 21:55:09 08/19/23
Start NBR section for initial routing at 20:59:43 08/16/23
Start NBR section for initial routing at 21:55:10 08/19/23
Level 1, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 7.085ns/0.000ns; real time: 9 secs
Level 2, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 7.138ns/0.000ns; real time: 9 secs
Level 3, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs
0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 7.276ns/0.000ns; real time: 9 secs
Level 4, iteration 1
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs
10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.966ns/0.000ns; real time: 9 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 20:59:43 08/16/23
Level 1, iteration 1
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs
Start NBR section for normal routing at 21:55:10 08/19/23
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.966ns/0.000ns; real time: 9 secs
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs
Estimated worst slack/total negative slack&lt;setup&gt;: 6.966ns/0.000ns; real time: 9 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
Level 4, iteration 0
Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
Start NBR section for re-routing at 21:55:10 08/19/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;hold &gt;: 0.083ns/0.000ns; real time: 6 secs
Level 4, iteration 0
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.902ns/0.000ns; real time: 6 secs
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.902ns/0.000ns; real time: 6 secs
Estimated worst slack/total negative slack&lt;setup&gt;: 6.966ns/0.000ns; real time: 9 secs
Start NBR section for re-routing at 20:59:44 08/16/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 7 secs
Start NBR section for post-routing at 20:59:44 08/16/23
Start NBR section for post-routing at 21:55:10 08/19/23
End NBR router with 0 unrouted connection
@ -229,20 +211,17 @@ NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 4.922ns
Estimated worst slack&lt;setup&gt; : 6.966ns
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Total CPU time 6 secs
Total REAL time: 7 secs
Total CPU time 9 secs
Total REAL time: 9 secs
Completely routed.
End of route. 1008 routed (100.00%); 0 unrouted.
End of route. 978 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
@ -256,14 +235,14 @@ All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 4.922
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 6.966
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.088
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.304
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
par done!

9
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_premap.htm Normal file
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@ -0,0 +1,9 @@
<html>
<head>
<title>syntmp/LCMXO2_640HC_impl1_premap_srr.htm log file</title>
</head>
<frameset cols="20%, 80%">
<frame src="syntmp/LCMXO2_640HC_impl1_premap_toc.htm" name="tocFrame" />
<frame src="syntmp/LCMXO2_640HC_impl1_premap_srr.htm" name="srrFrame"/>
</frameset>
</html>

10
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt
View File

@ -9,14 +9,14 @@ Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEPC
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Wed Aug 16 20:59:30 2023
# Written on Sat Aug 19 21:54:50 2023
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
#Run constraint checker to find more issues with constraints.
#########################################################################
@ -35,7 +35,7 @@ Level Clock Frequency Period Type Group
----------------------------------------------------------------------------------------
0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 18
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19
0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14
@ -53,7 +53,7 @@ Clock Load Pin Seq Example Seq Example Comb Exam
-----------------------------------------------------------------------------------------
RCLK 65 RCLK(port) CASr2.C - -
PHI2 18 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)

10
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html
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@ -24,9 +24,9 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
@ -62,15 +62,15 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/08/16 20:59:46</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/08/20 05:55:58</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf</SPAN></TD>
</TR>
</small></TABLE>
<BR>

579
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html
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File diff suppressed because it is too large Load Diff

12
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl
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@ -24,7 +24,7 @@ set_option -force_gsr false
set_option -compiler_compatible 0
set_option -dup false
add_file -constraint {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc}
add_file -constraint {Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc}
set_option -default_enum_encoding default
#simulation options
@ -46,15 +46,15 @@ set_option -resolve_multiple_driver 0
set_option -seqshift_no_replicate 0
#-- add_file options
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v}
add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v}
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v}
add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v}
#-- top module name
set_option -top_module RAM2GS
#-- set result format/file last
project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi}
project -result_file {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi}
#-- error message log file
project -log_file {LCMXO2_640HC_impl1.srf}
@ -63,4 +63,4 @@ project -log_file {LCMXO2_640HC_impl1.srf}
#-- run Synplify with 'arrange HDL file'
project -run
project -run -clean

512
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_tw1.html Normal file
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@ -0,0 +1,512 @@
<HTML>
<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
<STYLE TYPE="text/css">
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Aug 19 21:54:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1_map.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 158 items scored, 0 timing errors detected.
Report: 53.254MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 844 items scored, 0 timing errors detected.
Report: 102.312MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[2] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
Constraint Details:
9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
Physical Path Details:
Data path Din[2]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c)
ROUTE 1 e 1.234 *n[2]_MGIOL.IN to SLICE_37.A1 Bank[2]
CTOF_DEL --- 0.495 SLICE_37.A1 to SLICE_37.F1 SLICE_37
ROUTE 1 e 1.234 SLICE_37.F1 to SLICE_94.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
ROUTE 2 e 1.234 SLICE_94.F0 to SLICE_90.D0 N_304
CTOF_DEL --- 0.495 SLICE_90.D0 to SLICE_90.F0 SLICE_90
ROUTE 5 e 1.234 SLICE_90.F0 to SLICE_91.C1 C1WR_7
CTOF_DEL --- 0.495 SLICE_91.C1 to SLICE_91.F1 SLICE_91
ROUTE 2 e 1.234 SLICE_91.F1 to SLICE_10.B0 un1_ADWR
CTOF_DEL --- 0.495 SLICE_10.B0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
--------
9.223 (33.1% logic, 66.9% route), 6 logic levels.
Report: 53.254MHz is the maximum frequency for this preference.
================================================================================
<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.226ns
The internal maximum frequency of the following component is 102.312 MHz
Logical Details: Cell type Pin name Component name
Destination: EFB WBCLKI ufmefb/EFBInst_0
Delay: 9.774ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 6.270ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[0] (from RCLK_c +)
Destination: FF Data in nRCS_0io (to RCLK_c +)
Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
Constraint Details:
9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets
16.000ns delay constraint less
0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns
Physical Path Details:
Data path SLICE_16 to nRCS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
ROUTE 9 e 1.234 SLICE_16.Q0 to SLICE_45.A0 CO0
CTOF_DEL --- 0.495 SLICE_45.A0 to SLICE_45.F0 SLICE_45
ROUTE 4 e 0.480 SLICE_45.F0 to SLICE_45.A1 N_41
CTOF_DEL --- 0.495 SLICE_45.A1 to SLICE_45.F1 SLICE_45
ROUTE 2 e 1.234 SLICE_45.F1 to SLICE_77.D0 nRRAS_5_u_i_0
CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_117.B1 N_25
CTOF_DEL --- 0.495 SLICE_117.B1 to SLICE_117.F1 SLICE_117
ROUTE 1 e 1.234 SLICE_117.F1 to SLICE_88.C1 N_28_i_sn
CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
ROUTE 1 e 1.234 SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c)
--------
9.577 (30.6% logic, 69.4% route), 6 logic levels.
Report: 102.312MHz is the maximum frequency for this preference.
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
--------------------------------------------------------------------------------
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Aug 19 21:54:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1_map.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 158 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 844 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
================================================================================
<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_12 to SLICE_12 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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/>SqS<R"M=3HFsolhNCP"R=F"Is) 3qtv.1>"/
<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
SC<)V=RM"sIF 3)wPA3CDsHFRo"Hk="VVlCL
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12
CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
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File diff suppressed because one or more lines are too long

49
CPLD/LCMXO2-640HC/impl1/impl1.xcf Normal file
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@ -0,0 +1,49 @@
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.12">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>MachXO2</Family>
<Name>LCMXO2-640HC</Name>
<IDCode>0x012b9043</IDCode>
<Package>All</Package>
<PON>LCMXO2-640HC</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed</File>
<FileTime>08/19/23 07:23:26</FileTime>
<JedecChecksum>0xC8BF</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>152</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<Usercode>0x00000000</Usercode>
<AccessMode>FLASH</AccessMode>
</Option>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
<TCKDelay>1</TCKDelay>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
</CableOptions>
</ispXCF>

135
CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1.ior Normal file
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@ -0,0 +1,135 @@
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 5
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 6
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: M
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
// Design: RAM2GS
// Package: TQFP100
// ncd File: lcmxo2_640hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Sat Aug 19 21:55:13 2023
// M: Minimum Performance Grade
// iotiming LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
I/O Timing Report (All units are in ns)
Worst Case Results across Performance Grades (M, 6, 5, 4):
// Input Setup and Hold Times
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
CROW[0] nCRAS F 2.553 4 -0.117 M
CROW[1] nCRAS F 2.019 4 0.001 M
Din[0] PHI2 F 4.715 4 3.636 4
Din[0] nCCAS F 0.790 4 0.535 4
Din[1] PHI2 F 5.021 4 3.516 4
Din[1] nCCAS F 1.086 4 0.264 4
Din[2] PHI2 F 3.385 4 3.516 4
Din[2] nCCAS F 0.282 4 0.948 4
Din[3] PHI2 F 4.644 4 3.516 4
Din[3] nCCAS F 1.278 4 0.095 4
Din[4] PHI2 F 4.335 4 3.516 4
Din[4] nCCAS F 2.446 4 -0.199 M
Din[5] PHI2 F 3.662 4 3.516 4
Din[5] nCCAS F 0.907 4 0.402 4
Din[6] PHI2 F 4.869 4 3.636 4
Din[6] nCCAS F 1.378 4 0.023 M
Din[7] PHI2 F 4.138 4 3.636 4
Din[7] nCCAS F 2.072 4 -0.120 M
MAin[0] PHI2 F 5.613 4 0.006 M
MAin[0] nCRAS F 0.244 4 1.146 4
MAin[1] PHI2 F 3.409 4 0.354 6
MAin[1] nCRAS F 0.244 4 1.146 4
MAin[2] PHI2 F 5.391 4 0.132 M
MAin[2] nCRAS F 0.250 4 1.141 4
MAin[3] PHI2 F 4.627 4 0.087 M
MAin[3] nCRAS F 0.507 4 0.910 4
MAin[4] PHI2 F 5.665 4 -0.133 M
MAin[4] nCRAS F 0.675 4 0.777 4
MAin[5] PHI2 F 5.569 4 0.129 M
MAin[5] nCRAS F 0.050 4 1.238 4
MAin[6] PHI2 F 5.717 4 -0.141 M
MAin[6] nCRAS F 0.242 4 1.146 4
MAin[7] PHI2 F 5.943 4 -0.173 M
MAin[7] nCRAS F 0.170 4 1.228 4
MAin[8] nCRAS F 0.759 4 0.696 4
MAin[9] nCRAS F 0.516 4 0.891 4
PHI2 RCLK R -0.312 M 3.167 4
nCCAS RCLK R 2.600 4 -0.176 M
nCCAS nCRAS F 3.106 4 -0.235 M
nCRAS RCLK R 1.803 4 -0.055 M
nFWE PHI2 F 4.680 4 0.261 M
nFWE nCRAS F 2.234 4 1.143 4
// Clock to Output Delay
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
LED RCLK R 9.922 4 2.878 M
LED nCRAS F 10.555 4 3.057 M
RA[0] RCLK R 11.638 4 3.406 M
RA[0] nCRAS F 11.771 4 3.430 M
RA[10] RCLK R 8.141 4 2.620 M
RA[11] PHI2 R 8.610 4 2.756 M
RA[1] RCLK R 11.674 4 3.407 M
RA[1] nCRAS F 10.635 4 3.155 M
RA[2] RCLK R 12.933 4 3.729 M
RA[2] nCRAS F 11.858 4 3.449 M
RA[3] RCLK R 12.587 4 3.664 M
RA[3] nCRAS F 11.255 4 3.298 M
RA[4] RCLK R 11.721 4 3.433 M
RA[4] nCRAS F 11.153 4 3.297 M
RA[5] RCLK R 12.544 4 3.620 M
RA[5] nCRAS F 11.480 4 3.360 M
RA[6] RCLK R 12.984 4 3.775 M
RA[6] nCRAS F 11.528 4 3.407 M
RA[7] RCLK R 12.553 4 3.625 M
RA[7] nCRAS F 11.610 4 3.368 M
RA[8] RCLK R 11.836 4 3.453 M
RA[8] nCRAS F 10.797 4 3.201 M
RA[9] RCLK R 11.182 4 3.271 M
RA[9] nCRAS F 11.135 4 3.279 M
RBA[0] nCRAS F 8.439 4 2.703 M
RBA[1] nCRAS F 8.439 4 2.703 M
RCKE RCLK R 10.083 4 3.081 M
RDQMH RCLK R 11.381 4 3.325 M
RDQML RCLK R 10.735 4 3.173 M
RD[0] nCCAS F 8.223 4 2.594 M
RD[1] nCCAS F 8.223 4 2.594 M
RD[2] nCCAS F 8.223 4 2.594 M
RD[3] nCCAS F 8.223 4 2.594 M
RD[4] nCCAS F 8.223 4 2.594 M
RD[5] nCCAS F 8.223 4 2.594 M
RD[6] nCCAS F 8.223 4 2.594 M
RD[7] nCCAS F 8.223 4 2.594 M
nRCAS RCLK R 8.141 4 2.620 M
nRCS RCLK R 8.141 4 2.620 M
nRRAS RCLK R 8.141 4 2.620 M
nRWE RCLK R 8.121 4 2.627 M
WARNING: you must also run trce with hold speed: 4
WARNING: you must also run trce with hold speed: 6
WARNING: you must also run trce with setup speed: M

17
CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1_trce.asd Normal file
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@ -0,0 +1,17 @@
[ActiveSupport TRCE]
; Setup Analysis
Fmax_0 = 47.556 MHz (2.900 MHz);
Fmax_1 = 150.150 MHz (2.900 MHz);
Fmax_2 = 150.150 MHz (2.900 MHz);
Fmax_3 = 102.312 MHz (62.500 MHz);
Failed = 0 (Total 4);
Clock_ports = 4;
Clock_nets = 4;
; Hold Analysis
Fmax_0 = - (-);
Fmax_1 = - (-);
Fmax_2 = - (-);
Fmax_3 = - (-);
Failed = 0 (Total 4);
Clock_ports = 4;
Clock_nets = 4;

14
CPLD/LCMXO2-640HC/impl1/run_options.txt
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@ -1,13 +1,13 @@
#-- Synopsys, Inc.
#-- Version R-2021.03L-SP1
#-- Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt
#-- Written on Wed Aug 16 20:59:29 2023
#-- Project file Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt
#-- Written on Sat Aug 19 21:54:48 2023
#project files
add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
#implementation: "impl1"
@ -18,7 +18,7 @@ impl -add impl1 -type fpga
set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
#device options
set_option -technology MACHXO2
@ -77,5 +77,5 @@ set_option -write_apr_constraint 1
project -result_file "./LCMXO2_640HC_impl1.edi"
#set log file
set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
impl -active "impl1"

18
CPLD/LCMXO2-640HC/impl1/scratchproject.prs
View File

@ -1,23 +1,23 @@
#-- Synopsys, Inc.
#-- Version R-2021.03L-SP1
#-- Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\scratchproject.prs
#-- Project file Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\scratchproject.prs
#project files
add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
#implementation: "impl1"
impl -add D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga
impl -add Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/}
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/}
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
#device options
set_option -technology MACHXO2
@ -73,8 +73,8 @@ set_option -auto_infer_blackbox 0
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi"
project -result_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi"
#set log file
set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
impl -active "impl1"

47
CPLD/LCMXO2-640HC/impl1/stdout.log
View File

@ -12,8 +12,8 @@ Running in Lattice mode
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC
Date: Wed Aug 16 20:59:29 2023
Hostname: ZANEMACWIN11
Date: Sat Aug 19 21:54:47 2023
Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
@ -22,61 +22,68 @@ ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground
Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:59:29 2023
# Sat Aug 19 21:54:48 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:59:29 2023
# Sat Aug 19 21:54:48 2023
Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:59:29 2023
# Sat Aug 19 21:54:48 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
compiler completed
# Wed Aug 16 20:59:30 2023
# Sat Aug 19 21:54:49 2023
Return Code: 0
Run Time:00h:00m:01s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Wed Aug 16 20:59:30 2023
Up-To-Date: multi_srs_gen. No run necessary
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
# Sat Aug 19 21:54:49 2023
multi_srs_gen completed
# Sat Aug 19 21:54:50 2023
Return Code: 0
Run Time:00h:00m:01s
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1
# Wed Aug 16 20:59:30 2023
# Sat Aug 19 21:54:50 2023
premap completed with warnings
# Wed Aug 16 20:59:32 2023
# Sat Aug 19 21:54:51 2023
Return Code: 1
Run Time:00h:00m:02s
Run Time:00h:00m:01s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Wed Aug 16 20:59:32 2023
# Sat Aug 19 21:54:51 2023
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Wed Aug 16 20:59:32 2023
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
# Sat Aug 19 21:54:51 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
fpga_mapper completed with warnings
# Wed Aug 16 20:59:35 2023
# Sat Aug 19 21:54:55 2023
Return Code: 1
Run Time:00h:00m:03s
Run Time:00h:00m:04s
Complete: Map on proj_1|impl1
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=0
exit status=0
Save changes for project:
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no

44
CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1
View File

@ -12,8 +12,8 @@ Running in Lattice mode
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC
Date: Wed Aug 16 20:57:40 2023
Hostname: ZANEMACWIN11
Date: Sat Aug 19 07:28:27 2023
Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
@ -22,68 +22,68 @@ ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground
Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:57:40 2023
# Sat Aug 19 07:28:28 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:57:40 2023
# Sat Aug 19 07:28:28 2023
Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:57:40 2023
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
# Sat Aug 19 07:28:28 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
compiler completed
# Wed Aug 16 20:57:43 2023
# Sat Aug 19 07:28:29 2023
Return Code: 0
Run Time:00h:00m:03s
Run Time:00h:00m:01s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Wed Aug 16 20:57:43 2023
# Sat Aug 19 07:28:29 2023
multi_srs_gen completed
# Wed Aug 16 20:57:43 2023
# Sat Aug 19 07:28:29 2023
Return Code: 0
Run Time:00h:00m:00s
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1
# Wed Aug 16 20:57:43 2023
# Sat Aug 19 07:28:29 2023
premap completed with warnings
# Wed Aug 16 20:57:45 2023
# Sat Aug 19 07:28:31 2023
Return Code: 1
Run Time:00h:00m:02s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Wed Aug 16 20:57:45 2023
# Sat Aug 19 07:28:31 2023
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Wed Aug 16 20:57:45 2023
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
# Sat Aug 19 07:28:31 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
fpga_mapper completed with warnings
# Wed Aug 16 20:57:49 2023
# Sat Aug 19 07:28:34 2023
Return Code: 1
Run Time:00h:00m:04s
Run Time:00h:00m:03s
Complete: Map on proj_1|impl1
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=0
exit status=0
Save changes for project:
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no

68
CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2
View File

@ -12,8 +12,8 @@ Running in Lattice mode
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC
Date: Wed Aug 16 20:52:48 2023
Hostname: ZANEMACWIN11
Date: Sat Aug 19 07:27:36 2023
Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
@ -22,38 +22,68 @@ ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground
Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:52:48 2023
# Sat Aug 19 07:27:37 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:52:48 2023
# Sat Aug 19 07:27:37 2023
Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:52:48 2023
compiler exited with errors
Job failed on: proj_1|impl1
# Sat Aug 19 07:27:37 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Job: "compiler" terminated with error status: 2
See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
# Wed Aug 16 20:52:49 2023
compiler completed
# Sat Aug 19 07:27:38 2023
Return Code: 2
Return Code: 0
Run Time:00h:00m:01s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Sat Aug 19 07:27:38 2023
multi_srs_gen completed
# Sat Aug 19 07:27:38 2023
Return Code: 0
Run Time:00h:00m:00s
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1
# Sat Aug 19 07:27:38 2023
premap completed with warnings
# Sat Aug 19 07:27:40 2023
Return Code: 1
Run Time:00h:00m:02s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Sat Aug 19 07:27:40 2023
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Sat Aug 19 07:27:40 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
fpga_mapper completed with warnings
# Sat Aug 19 07:27:43 2023
Return Code: 1
Run Time:00h:00m:03s
Complete: Map on proj_1|impl1
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Error: At line 65 while processing "LCMXO2_640HC_impl1_synplify.tcl"
2
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=9
exit status=9
exit status=0
exit status=0
Save changes for project:
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no

68
CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3
View File

@ -12,8 +12,8 @@ Running in Lattice mode
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC
Date: Wed Aug 16 20:52:31 2023
Hostname: ZANEMACWIN11
Date: Sat Aug 19 07:26:21 2023
Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
@ -22,38 +22,68 @@ ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground
Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:52:32 2023
# Sat Aug 19 07:26:21 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:52:32 2023
# Sat Aug 19 07:26:21 2023
Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:52:32 2023
compiler exited with errors
Job failed on: proj_1|impl1
# Sat Aug 19 07:26:21 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Job: "compiler" terminated with error status: 2
See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
# Wed Aug 16 20:52:32 2023
compiler completed
# Sat Aug 19 07:26:23 2023
Return Code: 2
Return Code: 0
Run Time:00h:00m:02s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Sat Aug 19 07:26:23 2023
multi_srs_gen completed
# Sat Aug 19 07:26:23 2023
Return Code: 0
Run Time:00h:00m:00s
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1
# Sat Aug 19 07:26:23 2023
premap completed with warnings
# Sat Aug 19 07:26:24 2023
Return Code: 1
Run Time:00h:00m:01s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Sat Aug 19 07:26:25 2023
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Sat Aug 19 07:26:25 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
fpga_mapper completed with warnings
# Sat Aug 19 07:26:28 2023
Return Code: 1
Run Time:00h:00m:03s
Complete: Map on proj_1|impl1
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Error: At line 64 while processing "LCMXO2_640HC_impl1_synplify.tcl"
2
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=9
exit status=9
exit status=0
exit status=0
Save changes for project:
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no

46
CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4
View File

@ -12,8 +12,8 @@ Running in Lattice mode
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC
Date: Wed Aug 16 20:44:48 2023
Hostname: ZANEMACWIN11
Date: Sat Aug 19 07:25:17 2023
Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
@ -22,68 +22,68 @@ ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground
Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:44:49 2023
# Sat Aug 19 07:25:18 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:44:49 2023
# Sat Aug 19 07:25:18 2023
Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:44:49 2023
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
# Sat Aug 19 07:25:18 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
compiler completed
# Wed Aug 16 20:44:51 2023
# Sat Aug 19 07:25:20 2023
Return Code: 0
Run Time:00h:00m:02s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Wed Aug 16 20:44:51 2023
# Sat Aug 19 07:25:20 2023
multi_srs_gen completed
# Wed Aug 16 20:44:52 2023
# Sat Aug 19 07:25:20 2023
Return Code: 0
Run Time:00h:00m:01s
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Run Time:00h:00m:00s
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1
# Wed Aug 16 20:44:52 2023
# Sat Aug 19 07:25:20 2023
premap completed with warnings
# Wed Aug 16 20:44:54 2023
# Sat Aug 19 07:25:21 2023
Return Code: 1
Run Time:00h:00m:02s
Run Time:00h:00m:01s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Wed Aug 16 20:44:54 2023
# Sat Aug 19 07:25:21 2023
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Wed Aug 16 20:44:54 2023
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
# Sat Aug 19 07:25:21 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
fpga_mapper completed with warnings
# Wed Aug 16 20:44:57 2023
# Sat Aug 19 07:25:25 2023
Return Code: 1
Run Time:00h:00m:03s
Run Time:00h:00m:04s
Complete: Map on proj_1|impl1
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=0
exit status=0
Save changes for project:
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no

68
CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5
View File

@ -12,8 +12,8 @@ Running in Lattice mode
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC
Date: Wed Aug 16 20:41:46 2023
Hostname: ZANEMACWIN11
Date: Sat Aug 19 07:23:03 2023
Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
@ -22,38 +22,68 @@ ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground
Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:41:47 2023
# Sat Aug 19 07:23:04 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:41:47 2023
# Sat Aug 19 07:23:04 2023
Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:41:47 2023
compiler exited with errors
Job failed on: proj_1|impl1
# Sat Aug 19 07:23:04 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Job: "compiler" terminated with error status: 2
See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
# Wed Aug 16 20:41:47 2023
compiler completed
# Sat Aug 19 07:23:05 2023
Return Code: 2
Return Code: 0
Run Time:00h:00m:01s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Sat Aug 19 07:23:05 2023
multi_srs_gen completed
# Sat Aug 19 07:23:05 2023
Return Code: 0
Run Time:00h:00m:00s
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1
# Sat Aug 19 07:23:05 2023
premap completed with warnings
# Sat Aug 19 07:23:07 2023
Return Code: 1
Run Time:00h:00m:02s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Sat Aug 19 07:23:07 2023
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Sat Aug 19 07:23:07 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
fpga_mapper completed with warnings
# Sat Aug 19 07:23:11 2023
Return Code: 1
Run Time:00h:00m:04s
Complete: Map on proj_1|impl1
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Error: At line 64 while processing "LCMXO2_640HC_impl1_synplify.tcl"
2
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=9
exit status=9
exit status=0
exit status=0
Save changes for project:
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no

53
CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr
View File

@ -9,7 +9,7 @@ Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEPC
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@ -27,7 +27,7 @@ Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEPC
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@ -39,8 +39,8 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
@I::"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
Verilog syntax check successful!
Compiler output is up to date. No re-compile necessary
@ -48,41 +48,41 @@ Compiler output is up to date. No re-compile necessary
Selecting top level module RAM2GS
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
Running optimization stage 1 on RAM2GS .......
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2GS .......
Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on REFB .......
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on EFB .......
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Wed Aug 16 20:59:29 2023
# Sat Aug 19 21:54:48 2023
###########################################################]
###########################################################[
@ -97,36 +97,33 @@ Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEPC
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
Linker output is up to date. No re-linking necessary
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Wed Aug 16 20:59:29 2023
# Sat Aug 19 21:54:48 2023
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Wed Aug 16 20:59:29 2023
# Sat Aug 19 21:54:48 2023
###########################################################]

BIN
CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.db
View File

Binary file not shown.

425
CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.srr
View File

@ -1,4 +1,4 @@
# Wed Aug 16 20:59:32 2023
# Sat Aug 19 21:54:51 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -11,117 +11,118 @@ Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEPC
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":162:4:162:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":149:4:149:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
@N: FX493 |Applying initial value "0" on instance IS[0].
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance IS[1].
@N: FX493 |Applying initial value "0" on instance IS[2].
@N: FX493 |Applying initial value "0" on instance IS[3].
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Available hyper_sources - for debug and ip models
None Found
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s -2.34ns 199 / 105
2 0h:00m:01s -2.34ns 208 / 105
3 0h:00m:01s -2.34ns 208 / 105
@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
1 0h:00m:01s -2.36ns 191 / 106
2 0h:00m:01s -2.36ns 206 / 106
3 0h:00m:01s -2.36ns 202 / 106
@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9|Replicating instance CmdUFMShift (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":162:4:162:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":120:4:120:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":120:4:120:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
Timing driven replication report
Added 4 Registers via timing driven replication
Added 1 LUTs via timing driven replication
Added 5 Registers via timing driven replication
Added 3 LUTs via timing driven replication
4 0h:00m:01s -1.83ns 210 / 109
4 0h:00m:01s -1.83ns 206 / 111
5 0h:00m:01s -1.83ns 211 / 109
6 0h:00m:01s -1.83ns 212 / 109
7 0h:00m:01s -1.83ns 212 / 109
5 0h:00m:02s -1.83ns 207 / 111
6 0h:00m:02s -1.83ns 208 / 111
7 0h:00m:02s -1.83ns 208 / 111
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB)
Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB)
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB)
@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"y:\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock RCLK with period 16.00ns
@N: MT615 |Found clock PHI2 with period 350.00ns
@N: MT615 |Found clock nCRAS with period 350.00ns
@ -129,7 +130,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:0
##### START OF TIMING REPORT #####[
# Timing report written on Wed Aug 16 20:59:35 2023
# Timing report written on Sat Aug 19 21:54:55 2023
#
@ -137,7 +138,7 @@ Top view: RAM2GS
Requested Frequency: 2.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
Constraint File(s): Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@ -149,23 +150,23 @@ Performance Summary
*******************
Worst slack in design: -1.832
Worst slack in design: -1.828
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------
PHI2 2.9 MHz 1.0 MHz 350.000 991.270 -1.832 declared default_clkgroup
RCLK 62.5 MHz 22.1 MHz 16.000 45.315 -0.784 declared default_clkgroup
PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup
RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.876 declared default_clkgroup
nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
nCRAS 2.9 MHz 1.0 MHz 350.000 953.610 -1.725 declared default_clkgroup
System 100.0 MHz NA 10.000 NA 15.472 system system_clkgroup
System 100.0 MHz NA 10.000 NA 13.991 system system_clkgroup
===================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
@ -178,13 +179,13 @@ Clocks | rise to rise | fall to fall | rise to
---------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------------
System RCLK | 16.000 15.472 | No paths - | No paths - | No paths -
RCLK System | 16.000 14.892 | No paths - | No paths - | No paths -
RCLK RCLK | 16.000 8.605 | No paths - | No paths - | No paths -
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.636 | No paths -
System RCLK | 16.000 13.991 | No paths - | No paths - | No paths -
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
RCLK RCLK | 16.000 9.535 | No paths - | No paths - | No paths -
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.876 | No paths -
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.832
PHI2 PHI2 | No paths - | 350.000 346.115 | 175.000 168.921 | 175.000 173.428
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
PHI2 PHI2 | No paths - | 350.000 347.059 | 175.000 168.905 | 175.000 173.428
nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.725
===============================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
@ -211,18 +212,18 @@ Starting Points with Worst Slack
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------
CMDUFMWrite PHI2 FD1P3AX Q CMDUFMWrite 1.044 -1.832
CmdSubmitted_fast PHI2 FD1S3AX Q CmdSubmitted_fast 1.044 -1.832
CmdSubmitted PHI2 FD1S3AX Q CmdSubmitted 1.148 -1.708
------------------------------------------------------------------------------------------------
CmdUFMShift_fast PHI2 FD1P3AX Q CmdUFMShift_fast 1.044 -1.828
CmdValid_fast PHI2 FD1S3AX Q CmdValid_fast 1.044 -1.828
CmdUFMShift PHI2 FD1P3AX Q CmdUFMShift 1.108 -1.810
CmdValid PHI2 FD1S3AX Q CmdValid 1.108 -1.810
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -1.746
CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 -0.572
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -0.572
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 168.921
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 168.921
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 168.921
Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 168.921
==================================================================================================
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 168.905
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 168.905
================================================================================================
Ending Points with Worst Slack
@ -232,16 +233,16 @@ Ending Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------
wb_adr[0] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_adr[1] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_adr[2] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_adr[3] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_adr[4] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_adr[5] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_adr[6] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_adr[7] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_cyc_stb PHI2 FD1P3IX SP un1_wb_clk32_i 0.528 -1.832
wb_dati[0] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832
wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828
=======================================================================================
@ -256,26 +257,26 @@ Path information for path number 1:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.528
- Propagation time: 2.361
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -1.832
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CMDUFMWrite / Q
Starting point: CmdUFMShift_fast / Q
Ending point: wb_adr[0] / SP
The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r -
CMDUFMWrite Net - - - - 2
CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r -
CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f -
un1_wb_clk32_i Net - - - - 18
wb_adr[0] FD1P3AX SP In 0.000 2.361 f -
=======================================================================================
--------------------------------------------------------------------------------------------
CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift_fast Net - - - - 2
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r -
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i Net - - - - 17
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
============================================================================================
Path information for path number 2:
@ -284,26 +285,26 @@ Path information for path number 2:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.528
- Propagation time: 2.361
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -1.832
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdSubmitted_fast / Q
Starting point: CmdValid_fast / Q
Ending point: wb_adr[0] / SP
The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
CmdSubmitted_fast FD1S3AX Q Out 1.044 1.044 r -
CmdSubmitted_fast Net - - - - 2
CMDUFMWrite_RNIHQ1E1 ORCALUT4 B In 0.000 1.044 r -
CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 r -
un1_wb_clk32_i Net - - - - 18
wb_adr[0] FD1P3AX SP In 0.000 2.361 r -
=======================================================================================
--------------------------------------------------------------------------------------------
CmdValid_fast FD1S3AX Q Out 1.044 1.044 r -
CmdValid_fast Net - - - - 2
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 B In 0.000 1.044 r -
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i Net - - - - 17
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
============================================================================================
Path information for path number 3:
@ -312,26 +313,26 @@ Path information for path number 3:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.528
- Propagation time: 2.361
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -1.832
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CMDUFMWrite / Q
Starting point: CmdUFMShift_fast / Q
Ending point: wb_adr[7] / SP
The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r -
CMDUFMWrite Net - - - - 2
CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r -
CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f -
un1_wb_clk32_i Net - - - - 18
wb_adr[7] FD1P3AX SP In 0.000 2.361 f -
=======================================================================================
--------------------------------------------------------------------------------------------
CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift_fast Net - - - - 2
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r -
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i Net - - - - 17
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
============================================================================================
Path information for path number 4:
@ -340,26 +341,26 @@ Path information for path number 4:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.528
- Propagation time: 2.361
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -1.832
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CMDUFMWrite / Q
Starting point: CmdUFMShift_fast / Q
Ending point: wb_adr[6] / SP
The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r -
CMDUFMWrite Net - - - - 2
CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r -
CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f -
un1_wb_clk32_i Net - - - - 18
wb_adr[6] FD1P3AX SP In 0.000 2.361 f -
=======================================================================================
--------------------------------------------------------------------------------------------
CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift_fast Net - - - - 2
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r -
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i Net - - - - 17
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
============================================================================================
Path information for path number 5:
@ -368,26 +369,26 @@ Path information for path number 5:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.528
- Propagation time: 2.361
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -1.832
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CMDUFMWrite / Q
Starting point: CmdUFMShift_fast / Q
Ending point: wb_adr[5] / SP
The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r -
CMDUFMWrite Net - - - - 2
CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r -
CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f -
un1_wb_clk32_i Net - - - - 18
wb_adr[5] FD1P3AX SP In 0.000 2.361 f -
=======================================================================================
--------------------------------------------------------------------------------------------
CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift_fast Net - - - - 2
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r -
CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i Net - - - - 17
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
============================================================================================
@ -405,16 +406,16 @@ Starting Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------
LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.876
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.636
n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.044 -0.572
FS[14] RCLK FD1S3AX Q FS[14] 1.108 8.605
FS[15] RCLK FD1S3AX Q FS[15] 1.108 8.605
FS[16] RCLK FD1S3AX Q FS[16] 1.108 8.605
FS[6] RCLK FD1S3AX Q FS[6] 1.268 8.872
FS[5] RCLK FD1S3AX Q FS[5] 1.228 8.912
FS[12] RCLK FD1S3AX Q FS[12] 1.302 9.679
FS[10] RCLK FD1S3AX Q FS[10] 1.299 9.682
InitReady RCLK FD1S3AX Q InitReady 1.321 9.535
FS[15] RCLK FD1S3AX Q FS[15] 1.180 9.677
FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.677
FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.677
S[1] RCLK FD1S3IX Q S[1] 1.244 9.913
S[0] RCLK FD1S3IX Q CO0 1.228 9.929
FS[12] RCLK FD1S3AX Q FS[12] 1.284 10.121
==================================================================================
@ -425,6 +426,7 @@ Ending Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------
XOR8MEG RCLK FD1P3AX D XOR8MEG_3 1.462 -0.876
RBA_0io[0] RCLK OFS1P3DX D RBAd_0[0] 1.089 -0.784
RBA_0io[1] RCLK OFS1P3DX D RBAd_0[1] 1.089 -0.784
RowA[0] RCLK FD1S3AX D RowAd_0[0] 1.089 -0.784
@ -434,7 +436,6 @@ RowA[3] RCLK FD1S3AX D RowAd_0[3] 1.089 -0
RowA[4] RCLK FD1S3AX D RowAd_0[4] 1.089 -0.784
RowA[5] RCLK FD1S3AX D RowAd_0[5] 1.089 -0.784
RowA[6] RCLK FD1S3AX D RowAd_0[6] 1.089 -0.784
RowA[7] RCLK FD1S3AX D RowAd_0[7] 1.089 -0.784
====================================================================================
@ -445,6 +446,37 @@ Worst Path Information
Path information for path number 1:
Requested Period: 1.000
- Setup time: -0.462
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.462
- Propagation time: 2.339
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.876
Number of logic level(s): 2
Starting point: LEDEN / Q
Ending point: XOR8MEG / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------
LEDEN FD1P3AX Q Out 1.108 1.108 r -
LEDEN Net - - - - 3
XOR8MEG_3_u_0_bm ORCALUT4 A In 0.000 1.108 r -
XOR8MEG_3_u_0_bm ORCALUT4 Z Out 1.017 2.125 f -
XOR8MEG_3_u_0_bm Net - - - - 1
XOR8MEG_3_u_0 PFUMX ALUT In 0.000 2.125 f -
XOR8MEG_3_u_0 PFUMX Z Out 0.214 2.339 f -
XOR8MEG_3 Net - - - - 1
XOR8MEG FD1P3AX D In 0.000 2.339 f -
===================================================================================
Path information for path number 2:
Requested Period: 1.000
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
@ -471,7 +503,7 @@ RBA_0io[0] OFS1P3DX D In 0.000 1.873 r -
=================================================================================
Path information for path number 2:
Path information for path number 3:
Requested Period: 1.000
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
@ -499,7 +531,7 @@ RowA[9] FD1S3AX D In 0.000 1.873 f -
=================================================================================
Path information for path number 3:
Path information for path number 4:
Requested Period: 1.000
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
@ -527,7 +559,7 @@ RowA[8] FD1S3AX D In 0.000 1.873 r -
=================================================================================
Path information for path number 4:
Path information for path number 5:
Requested Period: 1.000
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
@ -555,34 +587,6 @@ RBA_0io[1] OFS1P3DX D In 0.000 1.873 r -
=================================================================================
Path information for path number 5:
Requested Period: 1.000
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 1.873
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.784
Number of logic level(s): 1
Starting point: Ready_fast / Q
Ending point: RowA[6] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
RowAd[6] ORCALUT4 B In 0.000 1.256 r -
RowAd[6] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[6] Net - - - - 1
RowA[6] FD1S3AX D In 0.000 1.873 r -
=================================================================================
====================================
@ -612,11 +616,11 @@ Ending Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
nRCAS_0io nCRAS OFS1P3BX D N_186_i 1.089 -1.725
nRWE_0io nCRAS OFS1P3BX D N_44_i 1.089 -1.725
nRCAS_0io nCRAS OFS1P3BX D N_249_i 1.089 -1.725
nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.725
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.653
nRCS_0io nCRAS OFS1P3BX D N_32_i 1.089 -1.653
nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.653
========================================================================================
@ -651,7 +655,7 @@ nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.197 r -
nRCAS_0_sqmuxa_1 Net - - - - 2
nRCAS_0io_RNO ORCALUT4 B In 0.000 2.197 r -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.813 f -
N_186_i Net - - - - 1
N_249_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.813 f -
========================================================================================
@ -682,7 +686,7 @@ nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.197 r -
nRCAS_0_sqmuxa_1 Net - - - - 2
nRWE_0io_RNO ORCALUT4 C In 0.000 2.197 r -
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.813 r -
N_44_i Net - - - - 1
N_37_i Net - - - - 1
nRWE_0io OFS1P3BX D In 0.000 2.813 r -
========================================================================================
@ -713,7 +717,7 @@ nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
nRCAS_0io_RNO_0 Net - - - - 1
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
N_186_i Net - - - - 1
N_249_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.781 r -
==================================================================================
@ -741,7 +745,7 @@ CBR FD1S3AX Q Out 1.148 1.148 r -
CBR Net - - - - 4
nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r -
nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f -
N_97 Net - - - - 1
N_265 Net - - - - 1
nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f -
nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f -
nRowColSel_0_0 Net - - - - 1
@ -795,6 +799,7 @@ Starting Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 13.991
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 15.472
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 15.472
=========================================================================================
@ -806,10 +811,13 @@ Ending Points with Worst Slack
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------
LEDEN System FD1P3AX D LEDEN_6_i_m2 16.089 15.472
n8MEGEN System FD1P3AX D n8MEGEN_6_i_m2 16.089 15.472
=====================================================================================
----------------------------------------------------------------------------------------------------------
LEDEN System FD1P3AX SP un1_FS_38_i 15.528 13.991
n8MEGEN System FD1P3AX SP un1_FS_38_i 15.528 13.991
wb_cyc_stb System FD1P3IX SP un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i 15.528 14.297
LEDEN System FD1P3AX D LEDEN_6 16.089 15.472
n8MEGEN System FD1P3AX D n8MEGEN_6 16.089 15.472
==========================================================================================================
@ -819,31 +827,34 @@ Worst Path Information
Path information for path number 1:
Requested Period: 16.000
- Setup time: -0.089
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 16.089
= Required time: 15.528
- Propagation time: 0.617
- Propagation time: 1.538
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 15.472
= Slack (non-critical) : 13.991
Number of logic level(s): 1
Starting point: ufmefb.EFBInst_0 / WBDATO0
Ending point: n8MEGEN / D
Number of logic level(s): 2
Starting point: ufmefb.EFBInst_0 / WBACKO
Ending point: LEDEN / SP
The start point is clocked by System [rising]
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
ufmefb.EFBInst_0 EFB WBDATO0 Out 0.000 0.000 r -
wb_dato[0] Net - - - - 1
n8MEGEN_6_i_m2 ORCALUT4 C In 0.000 0.000 r -
n8MEGEN_6_i_m2 ORCALUT4 Z Out 0.617 0.617 r -
n8MEGEN_6_i_m2 Net - - - - 1
n8MEGEN FD1P3AX D In 0.000 0.617 r -
======================================================================================
---------------------------------------------------------------------------------------------
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
wb_ack Net - - - - 2
ufmefb.EFBInst_0_RNI9PBJ ORCALUT4 D In 0.000 0.000 r -
ufmefb.EFBInst_0_RNI9PBJ ORCALUT4 Z Out 0.449 0.449 r -
d_N_5_mux Net - - - - 1
CmdValid_fast_RNITQBM1 ORCALUT4 C In 0.000 0.449 r -
CmdValid_fast_RNITQBM1 ORCALUT4 Z Out 1.089 1.538 r -
un1_FS_38_i Net - - - - 2
LEDEN FD1P3AX SP In 0.000 1.538 r -
=============================================================================================
@ -851,16 +862,16 @@ n8MEGEN FD1P3AX D In 0.000 0.617 r -
Timing exceptions that could not be applied
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_640hc-4
Register bits: 109 of 640 (17%)
Register bits: 111 of 640 (17%)
PIC Latch: 0
I/O cells: 63
@ -869,28 +880,28 @@ Details:
BB: 8
CCU2D: 10
EFB: 1
FD1P3AX: 27
FD1P3IX: 3
FD1S3AX: 51
FD1S3IX: 3
FD1P3AX: 28
FD1P3IX: 2
FD1S3AX: 52
FD1S3IX: 4
GSR: 1
IB: 25
IFS1P3DX: 9
INV: 8
INV: 6
OB: 30
OFS1P3BX: 4
OFS1P3DX: 11
OFS1P3JX: 1
ORCALUT4: 206
PFUMX: 1
ORCALUT4: 199
PFUMX: 3
PUR: 1
VHI: 2
VLO: 2
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Wed Aug 16 20:59:35 2023
# Sat Aug 19 21:54:55 2023
###########################################################]

BIN
CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.srr.db
View File

Binary file not shown.

BIN
CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.szr
View File

Binary file not shown.

8
CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr
View File

@ -10,19 +10,19 @@ Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEPC
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
File Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Wed Aug 16 20:58:39 2023
# Sat Aug 19 21:54:50 2023
###########################################################]

63
CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr
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@ -1,4 +1,4 @@
# Wed Aug 16 20:59:30 2023
# Sat Aug 19 21:54:50 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -11,69 +11,70 @@ Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEPC
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 139MB)
Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt
See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt
See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
@N: FX493 |Applying initial value "0" on instance InitReady.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance Ready.
@N: FX493 |Applying initial value "0" on instance RCKE.
@N: FX493 |Applying initial value "1" on instance nRCAS.
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
@N: FX493 |Applying initial value "1" on instance nRCS.
@N: FX493 |Applying initial value "0" on instance LEDEN.
@N: FX493 |Applying initial value "0" on instance n8MEGEN.
@N: FX493 |Applying initial value "1" on instance nRCAS.
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
@N: FX493 |Applying initial value "0" on instance CmdUFMShift.
@N: FX493 |Applying initial value "0" on instance CmdUFMWrite.
@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
@N: FX493 |Applying initial value "0" on instance CmdValid.
@N: FX493 |Applying initial value "1" on instance nRCS.
@N: FX493 |Applying initial value "1" on instance nRRAS.
@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
@N: FX493 |Applying initial value "0" on instance CmdUFMData.
@N: FX493 |Applying initial value "0" on instance C1Submitted.
@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
@N: FX493 |Applying initial value "0" on instance ADSubmitted.
@N: FX493 |Applying initial value "0" on instance XOR8MEG.
@N: FX493 |Applying initial value "0" on instance CmdEnable.
@N: FX493 |Applying initial value "1" on instance nRWE.
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
@ -85,7 +86,7 @@ Level Clock Frequency Period Type Group
----------------------------------------------------------------------------------------
0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 18
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19
0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14
@ -104,7 +105,7 @@ Clock Load Pin Seq Example Seq Example Comb Exam
-----------------------------------------------------------------------------------------
RCLK 65 RCLK(port) CASr2.C - -
PHI2 18 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
@ -125,7 +126,7 @@ For details review file gcc_ICG_report.rpt
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
4 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
@ -133,7 +134,7 @@ For details review file gcc_ICG_report.rpt
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 RCLK port 65 nRWE
@KP:ckid0_1 PHI2 port 18 RA11
@KP:ckid0_1 PHI2 port 19 RA11
@KP:ckid0_2 nCCAS port 8 WRD[7:0]
@KP:ckid0_3 nCRAS port 14 RowA[9:0]
=======================================================================================
@ -144,19 +145,19 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 184MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 16 20:59:32 2023
# Sat Aug 19 21:54:51 2023
###########################################################]

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CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr.db
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CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.szr
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2
CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_errors.txt
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@ -1,2 +1,2 @@
@E: CS168 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":72:15:72:15|Port WBCLKI does not exist
@E:Internal Error in c_hdl.exe

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