Thomas Harte
|
108da64562
|
Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
|
2017-06-20 22:25:00 -04:00 |
|
Thomas Harte
|
f85b46286e
|
Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter.
|
2017-06-20 22:20:58 -04:00 |
|
Thomas Harte
|
184b371649
|
Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
|
2017-06-20 21:48:50 -04:00 |
|
Thomas Harte
|
b0375bb037
|
Fixed the three LD rr, (nn) operations. Back down to four FUSE failures.
|
2017-06-20 21:32:23 -04:00 |
|
Thomas Harte
|
48942848e7
|
Fixed (Ix+d) read timing. I've put an extra wait cycle into the read, so no need to extend the refresh.
|
2017-06-20 21:15:56 -04:00 |
|
Thomas Harte
|
27ac342928
|
Corrected conditional call timing, and its test.
|
2017-06-20 20:57:23 -04:00 |
|
Thomas Harte
|
25aba16ef8
|
Quickly checking the FUSE tests, corrected a handful of instances where PC should be modified but isn't, correcting around 800 new failures.
|
2017-06-19 22:20:23 -04:00 |
|
Thomas Harte
|
a0d0f383c8
|
Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day.
|
2017-06-19 22:07:36 -04:00 |
|
Thomas Harte
|
cc8f316941
|
Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).
|
2017-06-19 20:51:28 -04:00 |
|
Thomas Harte
|
b684254908
|
Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
|
2017-06-19 20:33:34 -04:00 |
|
Thomas Harte
|
ba15371948
|
Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
|
2017-06-19 19:47:00 -04:00 |
|
Thomas Harte
|
73dbaebbc1
|
Fixed timing of EX (SP), HL/IX.
|
2017-06-19 19:25:53 -04:00 |
|
Thomas Harte
|
e3244eb68e
|
Rephrased internal operation machine cycles as having only an end. So they're now easy to count. Hence the test machine spots them, and a couple more of the current timing subset passes.
|
2017-06-19 07:39:46 -04:00 |
|
Thomas Harte
|
85c6fb1430
|
Explained refresh cycles to the all-RAM Z80.
|
2017-06-19 07:36:11 -04:00 |
|
Thomas Harte
|
54e4643396
|
Corrected non-default refresh cycle lengths. Reduces failures of the currently-tested timing subset from 10 to 4.
|
2017-06-19 07:34:23 -04:00 |
|
Thomas Harte
|
85c5c4405a
|
Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
|
2017-06-19 07:30:01 -04:00 |
|
Thomas Harte
|
d668879ba6
|
Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
|
2017-06-18 22:03:13 -04:00 |
|
Thomas Harte
|
cb140aa06e
|
Managed to navigate back to building.
|
2017-06-18 21:00:44 -04:00 |
|
Thomas Harte
|
6a769d3953
|
Finally dipped below the 20 error threshold that the compiler tops out at.
|
2017-06-18 20:34:46 -04:00 |
|
Thomas Harte
|
3be8ffd826
|
Some correct timings have gone out the window for now, but only the final quarter of the base page now contains compiler errors.
|
2017-06-18 20:31:12 -04:00 |
|
Thomas Harte
|
bb910e14a4
|
Dealt with the CB page.
|
2017-06-18 18:01:33 -04:00 |
|
Thomas Harte
|
69ebbe019a
|
Completed ED page conversion. Rolling onwards...
|
2017-06-18 17:56:48 -04:00 |
|
Thomas Harte
|
0d39672d32
|
Fixing typos here and there, persuaded the first half of the ED table to compile.
|
2017-06-18 17:48:54 -04:00 |
|
Thomas Harte
|
0d1231980a
|
Advanced to getting specific warnings in the ed-page table. So that's progress.
|
2017-06-18 17:25:15 -04:00 |
|
Thomas Harte
|
82a015892b
|
Started adapting to the newly-segmented world.
|
2017-06-18 17:18:01 -04:00 |
|
Thomas Harte
|
194b7f60c5
|
Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.
|
2017-06-18 17:08:50 -04:00 |
|
Thomas Harte
|
ebc7356db5
|
Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now.
|
2017-06-18 12:21:27 -04:00 |
|
Thomas Harte
|
e1a2580b2a
|
Renamed BusOperation to MachineCycle::Operation.
|
2017-06-17 21:53:45 -04:00 |
|
Thomas Harte
|
efc7f9df37
|
Combined I and R into a register pair.
|
2017-06-17 18:18:28 -04:00 |
|
Thomas Harte
|
aed2827e7b
|
Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
|
2017-06-12 22:22:00 -04:00 |
|
Thomas Harte
|
b9dbb6bcf8
|
Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate.
|
2017-06-12 18:55:04 -04:00 |
|
Thomas Harte
|
d12e50eb02
|
Corrected "should I adjust history?" tests.
|
2017-06-11 16:41:34 -04:00 |
|
Thomas Harte
|
db30f53ab0
|
Added the capacity to back-date interrupt line changes within a machine cycle, so that machines which time themselves entirely within perform_machine_cycle can still be cycle accurate on those changes.
|
2017-06-11 13:31:02 -04:00 |
|
Thomas Harte
|
b55579c348
|
Fixed usage of flush : the subclass version is definitively used.
|
2017-06-06 17:52:44 -04:00 |
|
Thomas Harte
|
3df6eba237
|
Fixed: my HALT line wasn't actually halting. NOPs followed, but the PC just kept counting.
|
2017-06-05 10:35:03 -04:00 |
|
Thomas Harte
|
e940e02126
|
Added a short circuit to set_interrupt_line, mostly to make breakpoints slightly more convenient to place.
|
2017-06-05 09:37:19 -04:00 |
|
Thomas Harte
|
7f743c6fb0
|
Got explicit about permitted type conversions.
|
2017-06-04 18:40:59 -04:00 |
|
Thomas Harte
|
096551ab3e
|
Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see.
|
2017-06-04 18:32:23 -04:00 |
|
Thomas Harte
|
c485c460f7
|
Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.
|
2017-06-04 18:08:35 -04:00 |
|
Thomas Harte
|
d2637123c4
|
Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.
|
2017-06-04 17:55:19 -04:00 |
|
Thomas Harte
|
0eebfdb4cc
|
Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
|
2017-06-04 15:39:37 -04:00 |
|
Thomas Harte
|
7811374b0f
|
Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
|
2017-06-04 15:07:07 -04:00 |
|
Thomas Harte
|
a2f01b4a46
|
Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now.
|
2017-06-04 14:59:18 -04:00 |
|
Thomas Harte
|
f5c910beb7
|
Fixed LDIR/LDDR bit 3/5 flags. This seems once again to satisfy FUSE.
|
2017-06-04 14:18:04 -04:00 |
|
Thomas Harte
|
4e014ca748
|
Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100?
|
2017-06-04 14:13:38 -04:00 |
|
Thomas Harte
|
1a811b1ab1
|
Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class.
|
2017-06-03 22:19:35 -04:00 |
|
Thomas Harte
|
c26349624c
|
This, of course, should be inline to gain any benefit from the slightly-tortured private implementation.
|
2017-06-03 22:00:57 -04:00 |
|
Thomas Harte
|
b642d9f712
|
Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
|
2017-06-03 21:54:42 -04:00 |
|
Thomas Harte
|
fd6623b5a5
|
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
|
2017-06-03 21:22:16 -04:00 |
|
Thomas Harte
|
b304c3a4b9
|
Eliminated the 6502's reliance on the micro-op scheduler.
|
2017-06-03 20:30:07 -04:00 |
|
Thomas Harte
|
3ceef2005b
|
Pulled the Z80 from the MicroOpScheduler inheritance tree as it barely uses the thing, and that allows me to make the MicroOp structure private.
|
2017-06-03 19:17:34 -04:00 |
|
Thomas Harte
|
24c84ca6f5
|
Commented out as-yet-unimplemented features.
|
2017-06-03 19:10:23 -04:00 |
|
Thomas Harte
|
7898f643ac
|
Added bus request/acknowledge logic.
|
2017-06-03 19:09:47 -04:00 |
|
Thomas Harte
|
7bd45d308a
|
Error was simply failure of the interrupt-mode setter. Fixed.
|
2017-06-03 18:58:13 -04:00 |
|
Thomas Harte
|
b3da16911f
|
Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
|
2017-06-03 18:42:54 -04:00 |
|
Thomas Harte
|
8c41a0f0ed
|
Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
|
2017-06-03 17:53:44 -04:00 |
|
Thomas Harte
|
3e9212aaff
|
Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
|
2017-06-03 17:41:45 -04:00 |
|
Thomas Harte
|
a2ec902773
|
Made an attempt at implementing all three modes of IRQ.
|
2017-06-03 17:07:05 -04:00 |
|
Thomas Harte
|
1c0130fd02
|
Cleaned up with a macro, and decided to make absolutely sure that DecodeOperation is functioning as intended by removing the MoveToNextProgram from fetch-decode-execute.
|
2017-06-03 12:19:25 -04:00 |
|
Thomas Harte
|
3e3d6f97f4
|
Edged towards being able to implement interrupt mode 0: created a special-case micro-op for incrementing the PC, and formalised that DecodeOperation is a terminal operation.
|
2017-06-03 12:16:21 -04:00 |
|
Thomas Harte
|
9c3bda0111
|
Attempted to round out NMI handling.
|
2017-06-03 11:30:12 -04:00 |
|
Thomas Harte
|
d14902700a
|
Minor syntax and wiring fixes.
|
2017-06-01 22:33:05 -04:00 |
|
Thomas Harte
|
c95c32a9fe
|
Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.
|
2017-06-01 22:31:04 -04:00 |
|
Thomas Harte
|
35e045d7a7
|
Made a first attempt at the correct segue into the three main kinds of interrupt, though the programs aren't written yet. So undefined behaviour would abound were an interrupt to occur. But it lets me figure out what effect the check has on performance. I hope little.
|
2017-06-01 22:16:22 -04:00 |
|
Thomas Harte
|
084e1f3d51
|
Added a latching of interrupt status before each bus operation, and reset and power-on inputs.
|
2017-06-01 21:40:08 -04:00 |
|
Thomas Harte
|
5b43cefb85
|
Started filling an appropriate mask variable with the interrupt request status right now. Which is step one towards implementing interrupts.
|
2017-06-01 20:34:52 -04:00 |
|
Thomas Harte
|
aab637c9e7
|
Made check_address_for_trap inlineable.
|
2017-06-01 18:28:34 -04:00 |
|
Thomas Harte
|
7d9b197383
|
Pulled the .get() call for fetch-decode-execute out of the main loop.
|
2017-06-01 18:28:04 -04:00 |
|
Thomas Harte
|
c9dd267ec1
|
Sketched an interface for signalling interrupts and pulled out some of the repetition in flag setting from ADD/ADC/SUB/SBC/CP.
|
2017-05-31 22:51:32 -04:00 |
|
Thomas Harte
|
a5254989f8
|
Rewired the Z80 not to use the program queue, as it's not proven a useful abstraction in practice and doing so yields an immediate 22% speed increase.
|
2017-05-31 20:15:56 -04:00 |
|
Thomas Harte
|
494ce073b5
|
Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.
|
2017-05-31 19:58:57 -04:00 |
|
Thomas Harte
|
b99e4210ba
|
Eliminated pointless abstraction; I ended up going indirect on instruction pages rather than scheduling methods.
|
2017-05-31 19:57:03 -04:00 |
|
Thomas Harte
|
d3b74cbc91
|
Set proper initial value for number_of_cycles_.
|
2017-05-31 19:55:51 -04:00 |
|
Thomas Harte
|
2f7f11e2e5
|
Added diagnosis props.
|
2017-05-31 06:54:25 -04:00 |
|
Thomas Harte
|
5119997122
|
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
|
2017-05-30 22:41:23 -04:00 |
|
Thomas Harte
|
b5c1773d59
|
Eliminated another conditional. Albeit a very predictable one.
|
2017-05-30 22:15:43 -04:00 |
|
Thomas Harte
|
dfb5057342
|
Moved repetition group conditions explicitly into the switch statement.
|
2017-05-30 22:12:10 -04:00 |
|
Thomas Harte
|
7bddd294c9
|
Resolved an unpredictable conditional and temporarily disabled the Zexalltest as part of the default suite, since it takes so long to run.
|
2017-05-30 21:03:02 -04:00 |
|
Thomas Harte
|
01f7394f7f
|
Corrected 6502 scheduling when flushing the pipeline.
|
2017-05-30 20:58:07 -04:00 |
|
Thomas Harte
|
5aa8b03349
|
Attempted to regularise the 6502 with the Z80 as to scheduling. I think that at least one bug remains.
|
2017-05-30 20:36:53 -04:00 |
|
Thomas Harte
|
b5ad910b81
|
Merge branch 'Z80' into StraightPointer
|
2017-05-30 19:25:38 -04:00 |
|
Thomas Harte
|
da65bae86e
|
Switched to supplying the bus operation by reference, go guarantee that it isn't null.
|
2017-05-30 19:24:58 -04:00 |
|
Thomas Harte
|
a0189a6fe1
|
Switched to following the current program via address.
|
2017-05-30 18:49:40 -04:00 |
|
Thomas Harte
|
c6185baa99
|
Fixed R incrementation and attempted to make the status flags cheaper to write to.
|
2017-05-29 22:23:19 -04:00 |
|
Thomas Harte
|
9d29cefe75
|
Evicted manual memory management.
|
2017-05-29 21:44:33 -04:00 |
|
Thomas Harte
|
35f535b9a3
|
Noodled around with initial state.
|
2017-05-29 19:25:08 -04:00 |
|
Thomas Harte
|
8bfaa487ce
|
Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).
|
2017-05-29 17:13:24 -04:00 |
|
Thomas Harte
|
0d067d2f01
|
Adjusted OTI/etc timing; 23 failures outstanding.
|
2017-05-29 16:54:45 -04:00 |
|
Thomas Harte
|
d66755fd1e
|
Corrected INI/D[r] timing. Down to 45 failures.
|
2017-05-29 16:50:52 -04:00 |
|
Thomas Harte
|
d290e3d99e
|
Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)
|
2017-05-29 16:35:00 -04:00 |
|
Thomas Harte
|
a6a4c5a936
|
Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.
|
2017-05-29 15:57:27 -04:00 |
|
Thomas Harte
|
8a8f0cef20
|
With all intentional opcode entry points now covered, commuted XX into NOP to give proper meaning to otherwise undefined codes.
|
2017-05-29 12:25:10 -04:00 |
|
Thomas Harte
|
91dc0d5f4a
|
Adjusted HALT to issue never-ending M1 fetches on the next instruction.
|
2017-05-29 12:20:33 -04:00 |
|
Thomas Harte
|
ed7b07c8b1
|
Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.
|
2017-05-29 11:54:27 -04:00 |
|
Thomas Harte
|
3f880fa769
|
Fixed [FD/DD][74/75], which always store H or L, never IXh, IXl, IYh or IYl.
|
2017-05-29 11:44:26 -04:00 |
|
Thomas Harte
|
d83dd17738
|
[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.
|
2017-05-29 11:40:56 -04:00 |
|
Thomas Harte
|
c322410783
|
Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
|
2017-05-29 10:52:54 -04:00 |
|
Thomas Harte
|
b67331e018
|
Fixing the OUT repetition group reduces the code to one failing test.
|
2017-05-29 10:48:53 -04:00 |
|
Thomas Harte
|
a47b339668
|
Made an attempt at OUT[I/D]R. 10 failures remaining. None of which, I guess, are due to unimplemented operations.
|
2017-05-29 10:28:04 -04:00 |
|
Thomas Harte
|
ad56a9215c
|
Implemented IN[I/D]x. 18 failures remaining.
|
2017-05-29 10:12:33 -04:00 |
|
Thomas Harte
|
c56a5344b9
|
Implemented CP[I/D]x.
|
2017-05-29 08:54:00 -04:00 |
|
Thomas Harte
|
1f62cbe21a
|
Reduced LD[I/D}{R} repetition.
|
2017-05-29 08:24:10 -04:00 |
|
Thomas Harte
|
47845f8c19
|
Tried to complete the LD[I/D]{R} group. 32 issues remain.
|
2017-05-28 23:55:54 -04:00 |
|
Thomas Harte
|
409c82ce73
|
Implemented RLD and RRD. 34 failures remaining.
|
2017-05-28 16:46:27 -04:00 |
|
Thomas Harte
|
dc3f5b6211
|
Fixed flag setting for LD A, I and LD A, R, and corrected typo affecting LD DE, (nn).
|
2017-05-28 16:32:10 -04:00 |
|
Thomas Harte
|
fb02b77e63
|
Implemented RETI/RETN. 40 warnings remaining.
|
2017-05-28 16:07:25 -04:00 |
|
Thomas Harte
|
f974d54c7a
|
Implemented IM. 48 failures remain.
|
2017-05-28 15:55:21 -04:00 |
|
Thomas Harte
|
68978c6e25
|
Implemented NEG and filled in the load/store and copy parts of the ED page that roll directly off the tongue. 53 issues outstanding.
|
2017-05-28 15:47:48 -04:00 |
|
Thomas Harte
|
5a4d448cc1
|
Corrected logical flags; now down to 68 failures, all of them on the ED page.
|
2017-05-28 15:09:58 -04:00 |
|
Thomas Harte
|
743eac8c55
|
Implemented EXX to complete the base page. 83 failures.
|
2017-05-28 14:55:14 -04:00 |
|
Thomas Harte
|
6b66c8f304
|
Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.
|
2017-05-28 14:50:51 -04:00 |
|
Thomas Harte
|
c976fbfcd5
|
Implemented the base-page IN and OUT instructions, bringing FUSE test failures down to 91.
|
2017-05-28 14:20:05 -04:00 |
|
Thomas Harte
|
ed3e38ac31
|
Performed some quick tidying.
|
2017-05-28 00:12:42 -04:00 |
|
Thomas Harte
|
76f03900d2
|
Implemented EX HL, (SP) so as, allowing for indexed pages, to bring issues below the psychological 100 barrier. To 99.
|
2017-05-28 00:02:14 -04:00 |
|
Thomas Harte
|
9759a04c7d
|
Timing fixes: the fetch-decode-execute pattern is now per-page, since that on [DD/FD]CB not only doesn't increment R but doesn't take four cycles, so is probably a normal read cycle. Adjusted timing all around.
|
2017-05-27 23:54:06 -04:00 |
|
Thomas Harte
|
0d2d04e17b
|
Seeking proper [F/D]DCB emulation: the offset comes before the final byte of opcode, and adding seems to overlap with the opcode fetch, which does not increment R. Also needs to duplicate the result to visible registers.
|
2017-05-27 21:06:56 -04:00 |
|
Thomas Harte
|
98423c6e41
|
Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.
|
2017-05-27 16:19:15 -04:00 |
|
Thomas Harte
|
33c3fa21e3
|
Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672.
|
2017-05-27 15:54:24 -04:00 |
|
Thomas Harte
|
2141d52794
|
Corrected typo. Now at 696 failures.
|
2017-05-27 15:41:26 -04:00 |
|
Thomas Harte
|
16b8021401
|
Made a stab at the CB pages.
|
2017-05-27 15:39:22 -04:00 |
|
Thomas Harte
|
151b09b5ca
|
Fixed various other obvious cases for indexing.
|
2017-05-26 23:37:17 -04:00 |
|
Thomas Harte
|
9bc2b48d9b
|
Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.
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2017-05-26 23:23:33 -04:00 |
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Thomas Harte
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ab8a98f1df
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Implemented RST.
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2017-05-26 07:29:19 -04:00 |
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Thomas Harte
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efe354a7b1
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Fixed half carry after logical operation.s
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2017-05-25 22:55:04 -04:00 |
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Thomas Harte
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d50d3fc837
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Implemented CPL, SCF and CCF.
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2017-05-25 22:51:08 -04:00 |
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Thomas Harte
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83ee92af1a
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Made DAA work sufficiently well for the FUSE test.
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2017-05-25 22:41:05 -04:00 |
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Thomas Harte
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ea0ad9fd87
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Took a shot at DAA, seemingly not to Fuse's liking though.
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2017-05-25 22:17:48 -04:00 |
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Thomas Harte
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ff3c60c0e1
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Implemented the conditional JRs.
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2017-05-25 21:51:30 -04:00 |
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Thomas Harte
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399703a471
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Implemented JR.
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2017-05-25 21:48:28 -04:00 |
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Thomas Harte
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82017c4aea
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Implemented DJNZ.
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2017-05-25 21:44:24 -04:00 |
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Thomas Harte
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bdf07c3dc9
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Implemented EX AF, AF'.
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2017-05-25 21:26:32 -04:00 |
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Thomas Harte
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598be24644
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Fixed overflow for 8-bit decrementing.
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2017-05-25 21:23:38 -04:00 |
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Thomas Harte
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c668ff9472
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Added incrementing of the refresh register.
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2017-05-25 21:01:52 -04:00 |
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Thomas Harte
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6575091a78
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Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
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2017-05-22 21:50:34 -04:00 |
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Thomas Harte
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9e25d014d2
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Made an attempt to log bus activity for comparison with FUSE results.
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2017-05-22 19:49:38 -04:00 |
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Thomas Harte
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41d5dd8679
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Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
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2017-05-22 19:24:11 -04:00 |
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Thomas Harte
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c3ea6dc1f5
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Added respect for limiting to the requested number of cycles in the Z80.
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2017-05-22 19:15:55 -04:00 |
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Thomas Harte
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22afa509ca
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Got to a parsing and towards an attempt to run FUSE tests.
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2017-05-22 19:14:46 -04:00 |
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Thomas Harte
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f2aae72cc2
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Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
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2017-05-21 20:43:36 -04:00 |
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Thomas Harte
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fe8db1873c
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Added 16-bit ADC and SBC table entries; once again extended logging.
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2017-05-21 20:32:06 -04:00 |
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Thomas Harte
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c66c715ac9
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Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets.
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2017-05-21 19:26:40 -04:00 |
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Thomas Harte
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5dcfd85642
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Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages.
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2017-05-21 19:15:52 -04:00 |
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Thomas Harte
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c70dfe1b09
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Implemented the two variations of loading between (nn) and SP.
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2017-05-21 13:20:28 -04:00 |
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Thomas Harte
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232c591655
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Threw in a little macro documentation and a missing macro.
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2017-05-21 13:13:21 -04:00 |
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Thomas Harte
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790614b544
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Added EI and DI.
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2017-05-21 12:53:17 -04:00 |
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Thomas Harte
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32c032cd97
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Implemented a couple of easy-to-add missing base page instructions.
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2017-05-21 10:18:43 -04:00 |
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Thomas Harte
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e48ee16366
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Continued cleaning efforts, added conditional RET.
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2017-05-21 10:13:59 -04:00 |
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Thomas Harte
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e92d936ce8
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Added conditional calls.
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2017-05-21 10:03:46 -04:00 |
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Thomas Harte
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4e210c5396
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Added LD A, (nn).
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2017-05-21 10:00:10 -04:00 |
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Thomas Harte
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3d3e60b1fc
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Implemented LD (HL), r.
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2017-05-21 09:56:41 -04:00 |
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