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2016-10-20

2016-11-03

2016-11-08

2016-12-06

2016-12-31

2017-01-01

2017-01-27

2017-01-30

2017-03-26

2017-03-26.2

2017-05-14

2017-05-16

2017-07-15

2017-07-30

2017-08-16

2017-08-27

2017-10-24

2017-11-03

2017-11-22

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2018-01-13

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2020-11-21

2020-11-29

2020-12-09

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2021-03-25

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2021-04-16.2

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untagged-83a648386d4da3db578a

Mono Color

• b7c978e078 Added getters for most of the input lines, and attempted to round out the ZX81's wait logic. Thomas Harte 2017-06-22 20:11:19 -04:00
• f0398a6db8 Added wait state hooks to the interrupt programs, and added an is_wait query on PartialMachineCycle. Thomas Harte 2017-06-22 20:07:47 -04:00
• f3b1ef99cc Merge pull request #134 from TomHarte/BinaryTape Thomas Harte 2017-06-21 22:25:42 -04:00
• 52d9ddf9e5 Gave the binary tape player a more logical assignment of wave level to output level. Which miraculously appears to have been the issue with the ZX80/81 tape loading — the inconsistency of silences seems to have been the issue. Thomas Harte 2017-06-21 22:13:24 -04:00
• 93f251dbcd Merge pull request #133 from TomHarte/ZX81Wait Thomas Harte 2017-06-21 21:46:08 -04:00
• a6810fc3ef Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards. Thomas Harte 2017-06-21 21:44:42 -04:00
• 15f6c51062 Added the most trivial implementation of the ZX81 wait line. Thomas Harte 2017-06-21 21:28:14 -04:00
• 5e21c706f3 Merge pull request #132 from TomHarte/MachineCycles Thomas Harte 2017-06-21 21:19:48 -04:00
• e1355d4b62 Restored proper video output. Thomas Harte 2017-06-21 21:18:09 -04:00
• 7eeac3b586 Switched R back to incrementing after the refresh cycle. It had snuck to before by virtue of subdivision of the M1 cycle. Which shortened the ZX80 line time, breaking synchronisation. Thomas Harte 2017-06-21 21:11:00 -04:00
• 4bf13610ce Reinstated interrupts by moving the refresh test back into the refresh cycle. Thomas Harte 2017-06-21 21:03:39 -04:00
• 0e0ce379b4 Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle. Thomas Harte 2017-06-21 20:38:08 -04:00
• 36e8a11505 Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line. Thomas Harte 2017-06-21 20:32:08 -04:00
• 45f442ea63 Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it. Thomas Harte 2017-06-21 19:08:48 -04:00
• db743c90d8 Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault. Thomas Harte 2017-06-21 18:58:44 -04:00
• 10cc94f581 Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached. Thomas Harte 2017-06-21 18:47:00 -04:00
• 108da64562 Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss. Thomas Harte 2017-06-20 22:25:00 -04:00
• f85b46286e Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter. Thomas Harte 2017-06-20 22:20:58 -04:00
• 184b371649 Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess. Thomas Harte 2017-06-20 21:48:50 -04:00
• b0375bb037 Fixed the three LD rr, (nn) operations. Back down to four FUSE failures. Thomas Harte 2017-06-20 21:32:23 -04:00
• 48942848e7 Fixed (Ix+d) read timing. I've put an extra wait cycle into the read, so no need to extend the refresh. Thomas Harte 2017-06-20 21:15:56 -04:00
• 27ac342928 Corrected conditional call timing, and its test. Thomas Harte 2017-06-20 20:57:23 -04:00
• 25aba16ef8 Quickly checking the FUSE tests, corrected a handful of instances where PC should be modified but isn't, correcting around 800 new failures. Thomas Harte 2017-06-19 22:20:23 -04:00
• a0d0f383c8 Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day. Thomas Harte 2017-06-19 22:07:36 -04:00
• 6752f165db Added failing tests for both kinds of CALL. Thomas Harte 2017-06-19 22:03:29 -04:00
• e05076b258 Added tests for everything except CALL. All passing. Thomas Harte 2017-06-19 22:00:04 -04:00
• fadbfdf801 Added DJNZ test. Thomas Harte 2017-06-19 21:31:56 -04:00
• cb277b8d1e Added JP and JR tests. Thomas Harte 2017-06-19 21:27:23 -04:00
• 234f14dbbe Tests were at fault; all passing now. Thomas Harte 2017-06-19 21:14:40 -04:00
• 99ede3a9ef BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d). Thomas Harte 2017-06-19 21:04:14 -04:00
• 378233f53d Extended to BITs and SETs, accruing three new failures. Thomas Harte 2017-06-19 21:01:30 -04:00
• f903408980 Caught up on comments. Thomas Harte 2017-06-19 20:53:22 -04:00
• cc8f316941 Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d). Thomas Harte 2017-06-19 20:51:28 -04:00
• b684254908 Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed. Thomas Harte 2017-06-19 20:33:34 -04:00
• 351d90ca55 Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL. Thomas Harte 2017-06-19 20:04:55 -04:00
• 23177df26a Added various tests of the basic ALU ops. Thomas Harte 2017-06-19 19:53:26 -04:00
• ba15371948 Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here. Thomas Harte 2017-06-19 19:47:00 -04:00
• 73dbaebbc1 Fixed timing of EX (SP), HL/IX. Thomas Harte 2017-06-19 19:25:53 -04:00
• 8d60734737 Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect. Thomas Harte 2017-06-19 19:17:54 -04:00
• 002098d496 The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests. Thomas Harte 2017-06-19 07:45:41 -04:00
• e3244eb68e Rephrased internal operation machine cycles as having only an end. So they're now easy to count. Hence the test machine spots them, and a couple more of the current timing subset passes. Thomas Harte 2017-06-19 07:39:46 -04:00
• 85c6fb1430 Explained refresh cycles to the all-RAM Z80. Thomas Harte 2017-06-19 07:36:11 -04:00
• 54e4643396 Corrected non-default refresh cycle lengths. Reduces failures of the currently-tested timing subset from 10 to 4. Thomas Harte 2017-06-19 07:34:23 -04:00
• 85c5c4405a Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse. Thomas Harte 2017-06-19 07:30:01 -04:00
• d668879ba6 Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates. Thomas Harte 2017-06-18 22:03:13 -04:00
• cb140aa06e Managed to navigate back to building. Thomas Harte 2017-06-18 21:00:44 -04:00
• 6a769d3953 Finally dipped below the 20 error threshold that the compiler tops out at. Thomas Harte 2017-06-18 20:34:46 -04:00
• 3be8ffd826 Some correct timings have gone out the window for now, but only the final quarter of the base page now contains compiler errors. Thomas Harte 2017-06-18 20:31:12 -04:00
• bb910e14a4 Dealt with the CB page. Thomas Harte 2017-06-18 18:01:33 -04:00
• 69ebbe019a Completed ED page conversion. Rolling onwards... Thomas Harte 2017-06-18 17:56:48 -04:00
• 0d39672d32 Fixing typos here and there, persuaded the first half of the ED table to compile. Thomas Harte 2017-06-18 17:48:54 -04:00
• 0d1231980a Advanced to getting specific warnings in the ed-page table. So that's progress. Thomas Harte 2017-06-18 17:25:15 -04:00
• 82a015892b Started adapting to the newly-segmented world. Thomas Harte 2017-06-18 17:18:01 -04:00
• 194b7f60c5 Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write. Thomas Harte 2017-06-18 17:08:50 -04:00
• ebc7356db5 Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now. Thomas Harte 2017-06-18 12:21:27 -04:00
• e1a2580b2a Renamed BusOperation to MachineCycle::Operation. Thomas Harte 2017-06-17 21:53:45 -04:00
• b6f51474ff Ensured that -description can handle the newly-captured bus actions. Thomas Harte 2017-06-17 18:20:30 -04:00
• 0f18768091 Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do. Thomas Harte 2017-06-17 18:19:25 -04:00
• efc7f9df37 Combined I and R into a register pair. Thomas Harte 2017-06-17 18:18:28 -04:00
• 50cd617bd9 Ensured test raises only the intentional failure exceptions. Thomas Harte 2017-06-15 22:33:46 -04:00
• 838b818cd3 Finished transcribing first page of machine cycle documentation; several failures contained. Thomas Harte 2017-06-15 22:19:49 -04:00
• cf795562bf Continued filling in tests, fleshing out what the test machine captures as a result. Thomas Harte 2017-06-15 20:59:59 -04:00
• ac37424878 Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on. Thomas Harte 2017-06-15 19:06:59 -04:00
• a336048c98 Merge branch 'ZX80FileFormats' Thomas Harte 2017-06-15 18:33:42 -04:00
• 87496f9978 Merge pull request #131 from TomHarte/ZX80FileFormats Thomas Harte 2017-06-15 18:32:38 -04:00
• 08a542a324 Reenabled the fast-loading hack. Thomas Harte 2017-06-15 18:30:12 -04:00
• 9b3d05e05f Simplified decoding logic. Thomas Harte 2017-06-14 22:24:44 -04:00
• d8e3103a2b Fixes: switched ZX80 and ZX81 timing to the correct way around, ensured that my wait takes effect if HALT **isn't** set, and made sure to recover from it. Thomas Harte 2017-06-13 21:48:17 -04:00
• 76a64d13a0 Made a first attempt at ZX81 emulation. Thomas Harte 2017-06-13 21:25:55 -04:00
• 1e975859c2 Started splitting ZX80 and ZX81 paths. Also the '80 fires its horizontal sync a little earlier than the '81, so pulled that back a little. Thomas Harte 2017-06-13 20:09:09 -04:00
• 4c5261bfa0 Made first attempt to use the horizontal counter for something; here for sync timing only, even though I've gone exclusively with '81-style timing for now. Thomas Harte 2017-06-12 22:28:30 -04:00
• aed2827e7b Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected. Thomas Harte 2017-06-12 22:22:00 -04:00
• e6e6e4e62b Adds an extra character for padding the ZX81 table. Thomas Harte 2017-06-12 22:08:11 -04:00
• 8b09b4180b This now at least remembers whether it is meant to be a ZX81 and has storage for a horizontal counter. Thomas Harte 2017-06-12 21:33:16 -04:00
• 626737b9fa Started mucking about with some string conversion routines. Not finished yet. Thomas Harte 2017-06-12 21:32:36 -04:00
• 22de481557 Made an attempt to get .p/.80 checked and as far as the emulated machine. Thomas Harte 2017-06-12 19:41:59 -04:00
• b9dbb6bcf8 Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate. Thomas Harte 2017-06-12 18:55:04 -04:00
• a48616a138 Fixed reference to Swift-world MachineDocument for the ZX81 file type. Thomas Harte 2017-06-12 18:51:11 -04:00
• 8222aac9e3 Added an official declaration of support for ZX81 files. Thomas Harte 2017-06-11 21:40:41 -04:00
• 77aa3c187e Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately. Thomas Harte 2017-06-11 21:38:32 -04:00
• ee0283c985 Modified to use an in-memory buffer for file contents. Thomas Harte 2017-06-11 21:35:09 -04:00
• 302c2e94de Corrected lingering hard-coded mask. So titles for memory configurations above 1kb now load. Thomas Harte 2017-06-11 21:27:46 -04:00
• 06fe07932a While tidying up, killed an unused instance variable. Thomas Harte 2017-06-11 21:21:26 -04:00
• 6913c7a018 This also can just use rom_mask_. Thomas Harte 2017-06-11 19:29:20 -04:00
• 6b602c74b7 Made an attempt to support memory maps other than the unexpanded default of 1kb. Thomas Harte 2017-06-11 19:29:02 -04:00
• 8116f85479 Allowed the static analyser to specify a ZX80 or 81, and a memory model. Neither is respected yet in the machine. Thomas Harte 2017-06-11 19:12:20 -04:00
• e40d553045 Bumped the tape parser up into the machine to ensure a maintained state. Temporarily disabled normally-timed tape playback. Thomas Harte 2017-06-11 18:31:43 -04:00
• 2c6414ce11 Adjusted to allow inspect_waves to swallow a gap before a bit if necessary, increasing the opportunities for its call. Thomas Harte 2017-06-11 18:31:09 -04:00
• e5aea632ee Updated curly bracket placement. Thomas Harte 2017-06-11 17:29:22 -04:00
• e5b30cdfbb Attempted to ensure appropriate resumption of processing after quick-reading a tape byte. Thomas Harte 2017-06-11 17:28:47 -04:00
• ba5f34f827 Narrowed view to the centre 80% of a frame. Thomas Harte 2017-06-11 17:24:32 -04:00
• 84d2feb2e6 Cleaned up and implemented fast-tape hack. I've decided it'd be better to test some other software, potentially to give multiple issues to think about, rather than sitting around with just the one. Thomas Harte 2017-06-11 16:42:49 -04:00
• d12e50eb02 Corrected "should I adjust history?" tests. Thomas Harte 2017-06-11 16:41:34 -04:00
• c2bc9a8c62 Ensured no namespace collision in double-include guards. Thomas Harte 2017-06-11 16:41:15 -04:00
• d910a4fd38 Adjusted to signal an interrupt during the refresh cycle rather than weirdly just afterwards. Which cuts video timing down by 4 cycles a line. There still might be a problem here somewhere though, as I'm getting 206 cycles/line and the internet states it should be 207. Thomas Harte 2017-06-11 13:32:20 -04:00
• db30f53ab0 Added the capacity to back-date interrupt line changes within a machine cycle, so that machines which time themselves entirely within perform_machine_cycle can still be cycle accurate on those changes. Thomas Harte 2017-06-11 13:31:02 -04:00
• 50be3a24fe Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be. Thomas Harte 2017-06-11 13:30:08 -04:00
• 256ba4028b Rejigged to eliminate semi-duplication of the is-a-file test. Thomas Harte 2017-06-08 21:52:13 -04:00
• b07af2660d Adjusted to make sure that the very end of a tape is properly measured. Thomas Harte 2017-06-08 21:33:35 -04:00
• bc0d70b2f7 Added: a shout-out when the tape has been exhausted. Thomas Harte 2017-06-08 21:32:27 -04:00