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2016-10-20

2016-11-03

2016-11-08

2016-12-06

2016-12-31

2017-01-01

2017-01-27

2017-01-30

2017-03-26

2017-03-26.2

2017-05-14

2017-05-16

2017-07-15

2017-07-30

2017-08-16

2017-08-27

2017-10-24

2017-11-03

2017-11-22

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2018-01-13

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2020-11-21

2020-11-29

2020-12-09

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2021-03-25

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2021-04-16.2

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untagged-83a648386d4da3db578a

Mono Color

• 35f535b9a3 Noodled around with initial state. Thomas Harte 2017-05-29 19:25:08 -04:00
• 6d22f6fcd5 Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being. Thomas Harte 2017-05-29 17:17:17 -04:00
• 8bfaa487ce Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit). Thomas Harte 2017-05-29 17:13:24 -04:00
• 0d067d2f01 Adjusted OTI/etc timing; 23 failures outstanding. Thomas Harte 2017-05-29 16:54:45 -04:00
• d66755fd1e Corrected INI/D[r] timing. Down to 45 failures. Thomas Harte 2017-05-29 16:50:52 -04:00
• 267b2add9a Adjusted for where FUSE nominally places timestamps. Down to 92 failures. Thomas Harte 2017-05-29 16:44:07 -04:00
• d290e3d99e Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!) Thomas Harte 2017-05-29 16:35:00 -04:00
• a6a4c5a936 Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures. Thomas Harte 2017-05-29 15:57:27 -04:00
• 8a8f0cef20 With all intentional opcode entry points now covered, commuted XX into NOP to give proper meaning to otherwise undefined codes. Thomas Harte 2017-05-29 12:25:10 -04:00
• 91dc0d5f4a Adjusted HALT to issue never-ending M1 fetches on the next instruction. Thomas Harte 2017-05-29 12:20:33 -04:00
• ed7b07c8b1 Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct. Thomas Harte 2017-05-29 11:54:27 -04:00
• 3f880fa769 Fixed [FD/DD][74/75], which always store H or L, never IXh, IXl, IYh or IYl. Thomas Harte 2017-05-29 11:44:26 -04:00
• d83dd17738 [DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed. Thomas Harte 2017-05-29 11:40:56 -04:00
• 9ade0dcae3 One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison. Thomas Harte 2017-05-29 11:06:23 -04:00
• a329d85697 Instituted memory value checks, flushing out seven new failures. Thomas Harte 2017-05-29 11:01:45 -04:00
• c322410783 Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation. Thomas Harte 2017-05-29 10:52:54 -04:00
• b67331e018 Fixing the OUT repetition group reduces the code to one failing test. Thomas Harte 2017-05-29 10:48:53 -04:00
• a47b339668 Made an attempt at OUT[I/D]R. 10 failures remaining. None of which, I guess, are due to unimplemented operations. Thomas Harte 2017-05-29 10:28:04 -04:00
• ad56a9215c Implemented IN[I/D]x. 18 failures remaining. Thomas Harte 2017-05-29 10:12:33 -04:00
• c56a5344b9 Implemented CP[I/D]x. Thomas Harte 2017-05-29 08:54:00 -04:00
• 1f62cbe21a Reduced LD[I/D}{R} repetition. Thomas Harte 2017-05-29 08:24:10 -04:00
• 47845f8c19 Tried to complete the LD[I/D]{R} group. 32 issues remain. Thomas Harte 2017-05-28 23:55:54 -04:00
• 409c82ce73 Implemented RLD and RRD. 34 failures remaining. Thomas Harte 2017-05-28 16:46:27 -04:00
• dc3f5b6211 Fixed flag setting for LD A, I and LD A, R, and corrected typo affecting LD DE, (nn). Thomas Harte 2017-05-28 16:32:10 -04:00
• fb02b77e63 Implemented RETI/RETN. 40 warnings remaining. Thomas Harte 2017-05-28 16:07:25 -04:00
• f974d54c7a Implemented IM. 48 failures remain. Thomas Harte 2017-05-28 15:55:21 -04:00
• 68978c6e25 Implemented NEG and filled in the load/store and copy parts of the ED page that roll directly off the tongue. 53 issues outstanding. Thomas Harte 2017-05-28 15:47:48 -04:00
• 6e83b7d6df Attempted to add a proper exit condition for Zexall. Thomas Harte 2017-05-28 15:13:47 -04:00
• 5a4d448cc1 Corrected logical flags; now down to 68 failures, all of them on the ED page. Thomas Harte 2017-05-28 15:09:58 -04:00
• 743eac8c55 Implemented EXX to complete the base page. 83 failures. Thomas Harte 2017-05-28 14:55:14 -04:00
• 6b66c8f304 Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84. Thomas Harte 2017-05-28 14:50:51 -04:00
• c976fbfcd5 Implemented the base-page IN and OUT instructions, bringing FUSE test failures down to 91. Thomas Harte 2017-05-28 14:20:05 -04:00
• ed3e38ac31 Performed some quick tidying. Thomas Harte 2017-05-28 00:12:42 -04:00
• 76f03900d2 Implemented EX HL, (SP) so as, allowing for indexed pages, to bring issues below the psychological 100 barrier. To 99. Thomas Harte 2017-05-28 00:02:14 -04:00
• 035df316aa FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures. Thomas Harte 2017-05-27 23:54:53 -04:00
• 9759a04c7d Timing fixes: the fetch-decode-execute pattern is now per-page, since that on [DD/FD]CB not only doesn't increment R but doesn't take four cycles, so is probably a normal read cycle. Adjusted timing all around. Thomas Harte 2017-05-27 23:54:06 -04:00
• c7cb47a1d8 Readded and then disabled my temporary one-test-only patch. Failures are currently at 237. Thomas Harte 2017-05-27 21:10:25 -04:00
• 0d2d04e17b Seeking proper [F/D]DCB emulation: the offset comes before the final byte of opcode, and adding seems to overlap with the opcode fetch, which does not increment R. Also needs to duplicate the result to visible registers. Thomas Harte 2017-05-27 21:06:56 -04:00
• 98423c6e41 Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues. Thomas Harte 2017-05-27 16:19:15 -04:00
• 33c3fa21e3 Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672. Thomas Harte 2017-05-27 15:54:24 -04:00
• 2141d52794 Corrected typo. Now at 696 failures. Thomas Harte 2017-05-27 15:41:26 -04:00
• 16b8021401 Made a stab at the CB pages. Thomas Harte 2017-05-27 15:39:22 -04:00
• 151b09b5ca Fixed various other obvious cases for indexing. Thomas Harte 2017-05-26 23:37:17 -04:00
• 9bc2b48d9b Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures. Thomas Harte 2017-05-26 23:23:33 -04:00
• ab8a98f1df Implemented RST. Thomas Harte 2017-05-26 07:29:19 -04:00
• efe354a7b1 Fixed half carry after logical operation.s Thomas Harte 2017-05-25 22:55:04 -04:00
• d50d3fc837 Implemented CPL, SCF and CCF. Thomas Harte 2017-05-25 22:51:08 -04:00
• 83ee92af1a Made DAA work sufficiently well for the FUSE test. Thomas Harte 2017-05-25 22:41:05 -04:00
• ea0ad9fd87 Took a shot at DAA, seemingly not to Fuse's liking though. Thomas Harte 2017-05-25 22:17:48 -04:00
• ff3c60c0e1 Implemented the conditional JRs. Thomas Harte 2017-05-25 21:51:30 -04:00
• 399703a471 Implemented JR. Thomas Harte 2017-05-25 21:48:28 -04:00
• 82017c4aea Implemented DJNZ. Thomas Harte 2017-05-25 21:44:24 -04:00
• bdf07c3dc9 Implemented EX AF, AF'. Thomas Harte 2017-05-25 21:26:32 -04:00
• 598be24644 Fixed overflow for 8-bit decrementing. Thomas Harte 2017-05-25 21:23:38 -04:00
• e4e71a1e5f Switched back to descriptive failures, but put a cap on them. Thomas Harte 2017-05-25 21:08:24 -04:00
• fba5af280e Shortened failure message, at least for now. Thomas Harte 2017-05-25 21:05:47 -04:00
• c668ff9472 Added incrementing of the refresh register. Thomas Harte 2017-05-25 21:01:52 -04:00
• 2cadc706e2 Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started. Thomas Harte 2017-05-25 21:00:33 -04:00
• 3c6f63abcc Started towards running the FUSE tests. Just need to deal with the memory segments. Thomas Harte 2017-05-25 19:12:59 -04:00
• 00cd7e7e9c After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON. Thomas Harte 2017-05-25 18:20:13 -04:00
• 055c860b43 Sealed off RegisterState as immutable, and started trying to parse the .expected file. Thomas Harte 2017-05-23 22:32:36 -04:00
• 454c8628c3 Implemented an additional constructor for RegisterStates, pulling it out into file-level scope and implementing Equatable. Thomas Harte 2017-05-23 22:05:33 -04:00
• a23a6db4d6 Tidied up, creating a holder for RegisterState and giving it deserialisation logic. This makes sense because a register state will also need to be taken from the outputScanner, and from the machine. Thomas Harte 2017-05-23 08:13:24 -04:00
• 6575091a78 Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly. Thomas Harte 2017-05-22 21:50:34 -04:00
• 9e25d014d2 Made an attempt to log bus activity for comparison with FUSE results. Thomas Harte 2017-05-22 19:49:38 -04:00
• 41d5dd8679 Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured. Thomas Harte 2017-05-22 19:24:11 -04:00
• c3ea6dc1f5 Added respect for limiting to the requested number of cycles in the Z80. Thomas Harte 2017-05-22 19:15:55 -04:00
• 22afa509ca Got to a parsing and towards an attempt to run FUSE tests. Thomas Harte 2017-05-22 19:14:46 -04:00
• 3fb3cc8269 Got explicit about encodings. Thomas Harte 2017-05-21 22:53:06 -04:00
• e3e461d7cb Added a test class for running the FUSE tests. With nothing much in it. Thomas Harte 2017-05-21 22:49:24 -04:00
• c16fccb317 Fixed file names. Thomas Harte 2017-05-21 22:43:07 -04:00
• b9cffdf2bd Imported the FUSE tests. Thomas Harte 2017-05-21 22:42:20 -04:00
• f2aae72cc2 Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least. Thomas Harte 2017-05-21 20:43:36 -04:00
• fe8db1873c Added 16-bit ADC and SBC table entries; once again extended logging. Thomas Harte 2017-05-21 20:32:06 -04:00
• c66c715ac9 Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets. Thomas Harte 2017-05-21 19:26:40 -04:00
• 5dcfd85642 Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages. Thomas Harte 2017-05-21 19:15:52 -04:00
• c70dfe1b09 Implemented the two variations of loading between (nn) and SP. Thomas Harte 2017-05-21 13:20:28 -04:00
• 232c591655 Threw in a little macro documentation and a missing macro. Thomas Harte 2017-05-21 13:13:21 -04:00
• 790614b544 Added EI and DI. Thomas Harte 2017-05-21 12:53:17 -04:00
• 32c032cd97 Implemented a couple of easy-to-add missing base page instructions. Thomas Harte 2017-05-21 10:18:43 -04:00
• e48ee16366 Continued cleaning efforts, added conditional RET. Thomas Harte 2017-05-21 10:13:59 -04:00
• e92d936ce8 Added conditional calls. Thomas Harte 2017-05-21 10:03:46 -04:00
• 4e210c5396 Added LD A, (nn). Thomas Harte 2017-05-21 10:00:10 -04:00
• 3d3e60b1fc Implemented LD (HL), r. Thomas Harte 2017-05-21 09:56:41 -04:00
• f3f0e2f1a9 Implemented RRA and RRCA. Thomas Harte 2017-05-21 09:52:19 -04:00
• 08206eea56 This logging has outlived its usefulness for now. Thomas Harte 2017-05-21 09:47:53 -04:00
• 78296246e8 Added ALU n. Thomas Harte 2017-05-21 09:46:18 -04:00
• 85b5dd35b1 Took a shot at 8-bit arithmetic. Thomas Harte 2017-05-21 09:43:17 -04:00
• 11cfaa3e3d Performed light syntactic cleaning on the first part of the base page table, eliminated redundant temporary variables, implemented 8-bit increment and decrement. Thomas Harte 2017-05-21 09:17:30 -04:00
• 103c863534 Through temporarily dramatically increased logging, fixed conditional JP. Thomas Harte 2017-05-20 23:03:52 -04:00
• 6688f83226 Took a shot at LDIR. Thomas Harte 2017-05-20 21:58:24 -04:00
• 01a064dd63 Added an empty ED page. Thomas Harte 2017-05-20 17:29:30 -04:00
• 7b234078ae Implemented EX DE, HL and shuffled to allow instruction pages. Thomas Harte 2017-05-20 17:04:25 -04:00
• add02a7897 Added LD (nn), A, and reduced double logging to single for now. Thomas Harte 2017-05-19 23:13:28 -04:00
• 19167df692 Consolidated and filled in AND and XOR. Thomas Harte 2017-05-19 23:03:34 -04:00
• 6766845e21 Filled in most of the loads. Thomas Harte 2017-05-19 22:57:43 -04:00
• bc3b5f3e35 Added 16-bit INCs and DECs. Which don't set flags, so are easy. Thomas Harte 2017-05-19 22:13:36 -04:00
• 5fe23113ec Moved RET to the correct place, implemented POP AF. Thomas Harte 2017-05-19 22:03:12 -04:00
• c55e1c1d17 Implemented POP and therefore RET; corrected timing of PUSH. Thomas Harte 2017-05-19 21:59:45 -04:00
• d910405648 Added enough infrastructure to be able to react to the two CP/M calls this cares about. Thomas Harte 2017-05-19 21:53:39 -04:00