2012-02-18 12:03:15 +00:00
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//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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//===----------------------------------------------------------------------===//
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//
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2008-02-10 18:45:23 +00:00
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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2004-08-17 04:55:41 +00:00
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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2012-03-17 18:46:09 +00:00
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#include "PPCRegisterInfo.h"
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2005-10-14 23:51:18 +00:00
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#include "PPC.h"
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2012-12-03 16:50:05 +00:00
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#include "PPCFrameLowering.h"
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2005-10-14 23:45:43 +00:00
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#include "PPCInstrBuilder.h"
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2006-11-16 22:43:37 +00:00
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#include "PPCMachineFunctionInfo.h"
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2006-07-11 00:48:23 +00:00
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#include "PPCSubtarget.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2004-08-17 04:55:41 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-01-26 21:22:28 +00:00
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-03-03 22:19:16 +00:00
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#include "llvm/CodeGen/RegisterScavenging.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/CodeGen/ValueTypes.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2009-07-08 20:53:28 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2005-11-06 09:00:38 +00:00
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#include "llvm/Support/MathExtras.h"
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2009-07-08 20:53:28 +00:00
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#include "llvm/Support/raw_ostream.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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2004-08-17 04:55:41 +00:00
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#include <cstdlib>
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2011-06-27 18:32:37 +00:00
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#define GET_REGINFO_TARGET_DESC
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2011-06-24 01:44:41 +00:00
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#include "PPCGenRegisterInfo.inc"
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2004-08-17 04:55:41 +00:00
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2010-04-15 17:20:57 +00:00
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using namespace llvm;
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2006-11-13 23:36:35 +00:00
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
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const TargetInstrInfo &tii)
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2011-07-18 20:57:22 +00:00
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: PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
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ST.isPPC64() ? 0 : 1,
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ST.isPPC64() ? 0 : 1),
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2013-02-24 17:34:50 +00:00
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Subtarget(ST), TII(tii) {
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2005-04-21 23:30:14 +00:00
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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2004-08-17 04:55:41 +00:00
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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2005-10-18 00:28:58 +00:00
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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2007-09-07 22:01:02 +00:00
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// 64-bit
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ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
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ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
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ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
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ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
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2013-03-31 01:58:02 +00:00
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ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
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2004-08-17 04:55:41 +00:00
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}
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2009-02-06 17:43:24 +00:00
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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2009-07-29 20:31:52 +00:00
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const TargetRegisterClass *
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2012-05-07 22:10:26 +00:00
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PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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const {
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2013-04-06 19:30:30 +00:00
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// Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
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// when it checks for ZERO folding.
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Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:51:05 +00:00
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if (Kind == 1) {
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if (Subtarget.isPPC64())
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return &PPC::G8RC_NOX0RegClass;
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return &PPC::GPRC_NOR0RegClass;
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}
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2009-02-06 17:43:24 +00:00
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if (Subtarget.isPPC64())
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return &PPC::G8RCRegClass;
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2009-07-29 20:31:52 +00:00
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return &PPC::GPRCRegClass;
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2009-02-06 17:43:24 +00:00
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}
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2012-03-04 03:33:22 +00:00
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const uint16_t*
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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2012-03-06 16:41:49 +00:00
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if (Subtarget.isDarwinABI())
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return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
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CSR_Darwin32_SaveList;
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2009-08-15 11:54:46 +00:00
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2012-03-06 16:41:49 +00:00
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return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
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}
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2009-08-15 11:54:46 +00:00
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2012-09-16 18:10:23 +00:00
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const uint32_t*
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2012-03-06 16:41:49 +00:00
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PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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2009-07-03 06:47:08 +00:00
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if (Subtarget.isDarwinABI())
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2012-03-06 16:41:49 +00:00
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return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
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CSR_Darwin32_RegMask;
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2009-08-15 11:54:46 +00:00
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2012-03-06 16:41:49 +00:00
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return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
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2006-05-18 00:12:58 +00:00
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}
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2013-03-21 21:37:52 +00:00
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const uint32_t*
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PPCRegisterInfo::getNoPreservedMask() const {
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// The naming here is inverted: The CSR_NoRegs_Altivec has the
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// Altivec registers masked so that they're not saved and restored around
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// instructions with this preserved mask.
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if (!Subtarget.hasAltivec())
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return CSR_NoRegs_Altivec_RegMask;
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2013-03-27 00:02:20 +00:00
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if (Subtarget.isDarwin())
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return CSR_NoRegs_Darwin_RegMask;
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2013-03-21 21:37:52 +00:00
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return CSR_NoRegs_RegMask;
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}
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2007-02-19 21:49:54 +00:00
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BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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2011-01-10 12:39:04 +00:00
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const PPCFrameLowering *PPCFI =
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static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
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2010-11-18 21:19:35 +00:00
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Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:51:05 +00:00
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// The ZERO register is not really a register, but the representation of r0
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// when used in instructions that treat r0 as the constant 0.
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Reserved.set(PPC::ZERO);
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2013-03-21 23:45:03 +00:00
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Reserved.set(PPC::ZERO8);
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Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:51:05 +00:00
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2013-03-21 19:03:19 +00:00
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// The FP register is also not really a register, but is the representation
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// of the frame pointer register used by ISD::FRAMEADDR.
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Reserved.set(PPC::FP);
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Reserved.set(PPC::FP8);
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Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15 21:37:41 +00:00
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// The counter registers must be reserved so that counter-based loops can
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// be correctly formed (and the mtctr instructions are not DCE'd).
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Reserved.set(PPC::CTR);
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Reserved.set(PPC::CTR8);
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2007-02-19 21:49:54 +00:00
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Reserved.set(PPC::R1);
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Reserved.set(PPC::LR);
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2008-03-03 22:19:16 +00:00
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Reserved.set(PPC::LR8);
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2008-10-29 18:26:45 +00:00
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Reserved.set(PPC::RM);
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2008-03-03 22:19:16 +00:00
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2009-07-03 06:45:56 +00:00
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// The SVR4 ABI reserves r2 and r13
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2009-07-03 06:47:08 +00:00
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if (Subtarget.isSVR4ABI()) {
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2009-07-03 06:45:56 +00:00
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Reserved.set(PPC::R2); // System-reserved register
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Reserved.set(PPC::R13); // Small Data Area pointer register
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}
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2009-08-15 11:54:46 +00:00
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// On PPC64, r13 is the thread pointer. Never allocate this register.
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2007-02-19 21:49:54 +00:00
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if (Subtarget.isPPC64()) {
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Reserved.set(PPC::R13);
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2008-03-03 22:19:16 +00:00
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Reserved.set(PPC::X1);
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Reserved.set(PPC::X13);
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2013-03-19 08:09:38 +00:00
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if (PPCFI->needsFP(MF))
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Reserved.set(PPC::X31);
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2009-08-15 11:54:46 +00:00
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// The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
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if (Subtarget.isSVR4ABI()) {
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Reserved.set(PPC::X2);
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}
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2007-02-19 21:49:54 +00:00
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}
|
2008-03-03 22:19:16 +00:00
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2010-12-18 19:53:14 +00:00
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if (PPCFI->needsFP(MF))
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2007-02-19 21:49:54 +00:00
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Reserved.set(PPC::R31);
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2008-03-03 22:19:16 +00:00
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2007-02-19 21:49:54 +00:00
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return Reserved;
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}
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2011-11-22 16:21:04 +00:00
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unsigned
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PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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const unsigned DefaultSafety = 1;
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switch (RC->getID()) {
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default:
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return 0;
|
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:51:05 +00:00
|
|
|
case PPC::G8RC_NOX0RegClassID:
|
|
|
|
case PPC::GPRC_NOR0RegClassID:
|
2011-11-22 16:21:04 +00:00
|
|
|
case PPC::G8RCRegClassID:
|
|
|
|
case PPC::GPRCRegClassID: {
|
|
|
|
unsigned FP = TFI->hasFP(MF) ? 1 : 0;
|
|
|
|
return 32 - FP - DefaultSafety;
|
|
|
|
}
|
|
|
|
case PPC::F8RCRegClassID:
|
|
|
|
case PPC::F4RCRegClassID:
|
|
|
|
case PPC::VRRCRegClassID:
|
|
|
|
return 32 - DefaultSafety;
|
2011-12-05 17:54:17 +00:00
|
|
|
case PPC::CRRCRegClassID:
|
|
|
|
return 8 - DefaultSafety;
|
2011-11-22 16:21:04 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Stack Frame Processing methods
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2008-03-03 22:19:16 +00:00
|
|
|
/// lowerDynamicAlloc - Generate the code for allocating an object in the
|
2006-11-16 22:43:37 +00:00
|
|
|
/// current frame. The sequence of code with be in the general form
|
|
|
|
///
|
2009-03-03 02:55:14 +00:00
|
|
|
/// addi R0, SP, \#frameSize ; get the address of the previous frame
|
2006-11-16 22:43:37 +00:00
|
|
|
/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
|
2009-03-03 02:55:14 +00:00
|
|
|
/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
|
2006-11-16 22:43:37 +00:00
|
|
|
///
|
2013-03-23 19:36:47 +00:00
|
|
|
void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
|
2006-11-16 22:43:37 +00:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II;
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
// Get the basic block's function.
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
// Get the frame info.
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// Determine whether 64-bit pointers are used.
|
|
|
|
bool LP64 = Subtarget.isPPC64();
|
2009-02-13 02:27:39 +00:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
2006-11-16 22:43:37 +00:00
|
|
|
|
2007-01-25 22:48:25 +00:00
|
|
|
// Get the maximum call stack size.
|
2006-11-16 22:43:37 +00:00
|
|
|
unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
|
|
|
|
// Get the total frame size.
|
|
|
|
unsigned FrameSize = MFI->getStackSize();
|
|
|
|
|
|
|
|
// Get stack alignments.
|
2011-01-10 12:39:04 +00:00
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
|
2006-11-16 22:43:37 +00:00
|
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
2010-07-30 21:09:48 +00:00
|
|
|
if (MaxAlign > TargetAlign)
|
|
|
|
report_fatal_error("Dynamic alloca with large aligns not supported");
|
2006-11-16 22:43:37 +00:00
|
|
|
|
|
|
|
// Determine the previous frame's address. If FrameSize can't be
|
|
|
|
// represented as 16 bits or we need special alignment, then we load the
|
|
|
|
// previous frame's address from 0(SP). Why not do an addis of the hi?
|
|
|
|
// Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
|
|
|
|
// Constructing the constant and adding would take 3 instructions.
|
|
|
|
// Fortunately, a frame greater than 32K is rare.
|
2008-03-03 22:19:16 +00:00
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
2013-03-14 20:21:47 +00:00
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2010-03-29 21:13:41 +00:00
|
|
|
if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
|
2009-02-13 02:27:39 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
|
2006-11-16 22:43:37 +00:00
|
|
|
.addReg(PPC::R31)
|
|
|
|
.addImm(FrameSize);
|
|
|
|
} else if (LP64) {
|
2013-03-12 14:12:16 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
|
|
|
|
.addImm(0)
|
|
|
|
.addReg(PPC::X1);
|
2006-11-16 22:43:37 +00:00
|
|
|
} else {
|
2009-02-13 02:27:39 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
|
2006-11-16 22:43:37 +00:00
|
|
|
.addImm(0)
|
|
|
|
.addReg(PPC::R1);
|
|
|
|
}
|
|
|
|
|
2008-03-03 22:19:16 +00:00
|
|
|
// Grow the stack and update the stack pointer link, then determine the
|
|
|
|
// address of new allocated space.
|
2006-11-16 22:43:37 +00:00
|
|
|
if (LP64) {
|
2013-03-12 14:12:16 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
|
|
|
|
.addReg(Reg, RegState::Kill)
|
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addReg(MI.getOperand(1).getReg());
|
2008-03-03 22:19:16 +00:00
|
|
|
if (!MI.getOperand(1).isKill())
|
2009-02-13 02:27:39 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
|
2008-03-20 01:22:40 +00:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addImm(maxCallFrameSize);
|
2008-03-03 22:19:16 +00:00
|
|
|
else
|
|
|
|
// Implicitly kill the register.
|
2009-02-13 02:27:39 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
|
2008-03-20 01:22:40 +00:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addImm(maxCallFrameSize)
|
2009-05-13 21:33:08 +00:00
|
|
|
.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
|
2006-11-16 22:43:37 +00:00
|
|
|
} else {
|
2012-06-19 02:34:32 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
|
2009-05-13 21:33:08 +00:00
|
|
|
.addReg(Reg, RegState::Kill)
|
2012-06-19 02:34:32 +00:00
|
|
|
.addReg(PPC::R1)
|
2006-11-16 22:43:37 +00:00
|
|
|
.addReg(MI.getOperand(1).getReg());
|
2008-03-03 22:19:16 +00:00
|
|
|
|
|
|
|
if (!MI.getOperand(1).isKill())
|
2009-02-13 02:27:39 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
|
2008-03-20 01:22:40 +00:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addImm(maxCallFrameSize);
|
2008-03-03 22:19:16 +00:00
|
|
|
else
|
|
|
|
// Implicitly kill the register.
|
2009-02-13 02:27:39 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
|
2008-03-20 01:22:40 +00:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addImm(maxCallFrameSize)
|
2009-05-13 21:33:08 +00:00
|
|
|
.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
|
2006-11-16 22:43:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Discard the DYNALLOC instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2008-03-03 22:19:16 +00:00
|
|
|
/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
|
|
|
|
/// reserving a whole register (R0), we scrounge for one here. This generates
|
|
|
|
/// code like this:
|
|
|
|
///
|
|
|
|
/// mfcr rA ; Move the conditional register into GPR rA.
|
|
|
|
/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
|
|
|
|
/// stw rA, FI ; Store rA to the frame.
|
|
|
|
///
|
|
|
|
void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
|
2013-03-23 19:36:47 +00:00
|
|
|
unsigned FrameIndex) const {
|
2008-03-03 22:19:16 +00:00
|
|
|
// Get the instruction.
|
2011-12-06 20:55:36 +00:00
|
|
|
MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
|
2008-03-03 22:19:16 +00:00
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2013-03-26 18:57:22 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2009-02-13 02:27:39 +00:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2011-06-17 15:21:10 +00:00
|
|
|
bool LP64 = Subtarget.isPPC64();
|
2013-03-26 18:57:22 +00:00
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
|
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
2011-12-10 04:50:53 +00:00
|
|
|
unsigned SrcReg = MI.getOperand(0).getReg();
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2008-03-04 23:27:33 +00:00
|
|
|
// We need to store the CR in the low 4-bits of the saved value. First, issue
|
2010-05-20 17:48:26 +00:00
|
|
|
// an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
|
2011-12-07 06:34:06 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
|
2010-05-20 17:48:26 +00:00
|
|
|
.addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
|
2008-03-04 23:27:33 +00:00
|
|
|
|
2008-03-03 22:19:16 +00:00
|
|
|
// If the saved register wasn't CR0, shift the bits left so that they are in
|
|
|
|
// CR0's slot.
|
2013-03-26 18:57:22 +00:00
|
|
|
if (SrcReg != PPC::CR0) {
|
|
|
|
unsigned Reg1 = Reg;
|
|
|
|
Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
|
|
|
|
2008-03-03 22:19:16 +00:00
|
|
|
// rlwinm rA, rA, ShiftBits, 0, 31.
|
2011-12-07 06:34:06 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
|
2013-03-26 18:57:22 +00:00
|
|
|
.addReg(Reg1, RegState::Kill)
|
2013-03-26 20:08:20 +00:00
|
|
|
.addImm(getEncodingValue(SrcReg) * 4)
|
2008-03-03 22:19:16 +00:00
|
|
|
.addImm(0)
|
|
|
|
.addImm(31);
|
2013-03-26 18:57:22 +00:00
|
|
|
}
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2011-06-17 15:21:10 +00:00
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
|
2013-03-28 03:38:16 +00:00
|
|
|
.addReg(Reg, RegState::Kill),
|
2008-03-03 22:19:16 +00:00
|
|
|
FrameIndex);
|
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2011-12-06 20:55:36 +00:00
|
|
|
void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
|
2013-03-23 19:36:47 +00:00
|
|
|
unsigned FrameIndex) const {
|
2011-12-06 20:55:36 +00:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2013-03-26 18:57:22 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2011-12-06 20:55:36 +00:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
|
2011-12-10 04:50:53 +00:00
|
|
|
bool LP64 = Subtarget.isPPC64();
|
2013-03-26 18:57:22 +00:00
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
|
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
2011-12-06 20:55:36 +00:00
|
|
|
unsigned DestReg = MI.getOperand(0).getReg();
|
|
|
|
assert(MI.definesRegister(DestReg) &&
|
|
|
|
"RESTORE_CR does not define its destination");
|
|
|
|
|
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
|
|
|
|
Reg), FrameIndex);
|
|
|
|
|
|
|
|
// If the reloaded register isn't CR0, shift the bits right so that they are
|
|
|
|
// in the right CR's slot.
|
|
|
|
if (DestReg != PPC::CR0) {
|
2013-03-26 18:57:22 +00:00
|
|
|
unsigned Reg1 = Reg;
|
|
|
|
Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
|
|
|
|
2013-03-26 20:08:20 +00:00
|
|
|
unsigned ShiftBits = getEncodingValue(DestReg)*4;
|
2011-12-06 20:55:36 +00:00
|
|
|
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
|
2012-01-16 23:22:50 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
|
2013-03-26 18:57:22 +00:00
|
|
|
.addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
|
2011-12-06 20:55:36 +00:00
|
|
|
.addImm(31);
|
|
|
|
}
|
|
|
|
|
2011-12-07 06:34:06 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
|
2013-03-26 18:57:22 +00:00
|
|
|
.addReg(Reg, RegState::Kill);
|
2011-12-06 20:55:36 +00:00
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2013-03-21 19:03:21 +00:00
|
|
|
void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
|
2013-03-23 19:36:47 +00:00
|
|
|
unsigned FrameIndex) const {
|
2013-03-21 19:03:21 +00:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2013-03-26 18:57:22 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2013-03-21 19:03:21 +00:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
|
2013-03-26 18:57:22 +00:00
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
|
2013-03-21 19:03:21 +00:00
|
|
|
unsigned SrcReg = MI.getOperand(0).getReg();
|
|
|
|
|
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
|
|
|
|
.addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
|
|
|
|
|
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
|
2013-03-28 03:38:16 +00:00
|
|
|
.addReg(Reg, RegState::Kill),
|
2013-03-21 19:03:21 +00:00
|
|
|
FrameIndex);
|
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
|
|
|
void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
|
2013-03-23 19:36:47 +00:00
|
|
|
unsigned FrameIndex) const {
|
2013-03-21 19:03:21 +00:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2013-03-26 18:57:22 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2013-03-21 19:03:21 +00:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
|
2013-03-26 18:57:22 +00:00
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
|
2013-03-21 19:03:21 +00:00
|
|
|
unsigned DestReg = MI.getOperand(0).getReg();
|
|
|
|
assert(MI.definesRegister(DestReg) &&
|
|
|
|
"RESTORE_VRSAVE does not define its destination");
|
|
|
|
|
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
|
|
|
|
Reg), FrameIndex);
|
|
|
|
|
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
|
2013-03-26 18:57:22 +00:00
|
|
|
.addReg(Reg, RegState::Kill);
|
2013-03-21 19:03:21 +00:00
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2012-09-12 14:47:47 +00:00
|
|
|
bool
|
|
|
|
PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
|
|
|
|
unsigned Reg, int &FrameIdx) const {
|
|
|
|
|
|
|
|
// For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
|
|
|
|
// ABI, return true to prevent allocating an additional frame slot.
|
|
|
|
// For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
|
2013-02-24 17:34:50 +00:00
|
|
|
// is arbitrary and will be subsequently ignored. For 32-bit, we have
|
|
|
|
// previously created the stack slot if needed, so return its FrameIdx.
|
2012-09-12 14:47:47 +00:00
|
|
|
if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
|
2013-02-24 17:34:50 +00:00
|
|
|
if (Subtarget.isPPC64())
|
2012-09-12 14:47:47 +00:00
|
|
|
FrameIdx = 0;
|
2013-02-24 17:34:50 +00:00
|
|
|
else {
|
|
|
|
const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
FrameIdx = FI->getCRSpillFrameIndex();
|
2012-09-12 14:47:47 +00:00
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-05-16 17:58:02 +00:00
|
|
|
// Figure out if the offset in the instruction must be a multiple of 4.
|
|
|
|
// This is true for instructions like "STD".
|
2013-04-09 17:27:09 +00:00
|
|
|
static bool usesIXAddr(const MachineInstr &MI) {
|
|
|
|
unsigned OpC = MI.getOpcode();
|
|
|
|
|
|
|
|
switch (OpC) {
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
case PPC::LWA:
|
|
|
|
case PPC::LD:
|
|
|
|
case PPC::STD:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Return the OffsetOperandNo given the FIOperandNum (and the instruction).
|
|
|
|
static unsigned getOffsetONFromFION(const MachineInstr &MI,
|
|
|
|
unsigned FIOperandNum) {
|
|
|
|
// Take into account whether it's an add or mem instruction
|
|
|
|
unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
|
|
|
|
if (MI.isInlineAsm())
|
|
|
|
OffsetOperandNo = FIOperandNum-1;
|
|
|
|
|
|
|
|
return OffsetOperandNo;
|
|
|
|
}
|
|
|
|
|
2010-08-26 23:32:16 +00:00
|
|
|
void
|
2009-10-07 17:12:56 +00:00
|
|
|
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
2013-01-31 20:02:54 +00:00
|
|
|
int SPAdj, unsigned FIOperandNum,
|
|
|
|
RegScavenger *RS) const {
|
2007-05-01 09:13:03 +00:00
|
|
|
assert(SPAdj == 0 && "Unexpected");
|
|
|
|
|
2006-11-16 22:43:37 +00:00
|
|
|
// Get the instruction.
|
2004-08-17 04:55:41 +00:00
|
|
|
MachineInstr &MI = *II;
|
2006-11-16 22:43:37 +00:00
|
|
|
// Get the instruction's basic block.
|
2004-08-17 04:55:41 +00:00
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2006-11-16 22:43:37 +00:00
|
|
|
// Get the basic block's function.
|
2004-08-17 04:55:41 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2006-11-16 22:43:37 +00:00
|
|
|
// Get the frame info.
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2011-01-10 12:39:04 +00:00
|
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
2009-02-13 02:27:39 +00:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
2005-04-21 23:30:14 +00:00
|
|
|
|
2013-04-09 17:27:09 +00:00
|
|
|
unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2006-11-16 22:43:37 +00:00
|
|
|
// Get the frame index.
|
2013-01-31 20:02:54 +00:00
|
|
|
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2006-11-16 22:43:37 +00:00
|
|
|
// Get the frame pointer save index. Users of this index are primarily
|
|
|
|
// DYNALLOC instructions.
|
|
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
int FPSI = FI->getFramePointerSaveIndex();
|
|
|
|
// Get the instruction opcode.
|
|
|
|
unsigned OpC = MI.getOpcode();
|
|
|
|
|
|
|
|
// Special case for dynamic alloca.
|
|
|
|
if (FPSI && FrameIndex == FPSI &&
|
|
|
|
(OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
|
2013-03-23 19:36:47 +00:00
|
|
|
lowerDynamicAlloc(II);
|
2010-08-26 23:32:16 +00:00
|
|
|
return;
|
2008-03-03 22:19:16 +00:00
|
|
|
}
|
|
|
|
|
2013-03-21 19:03:21 +00:00
|
|
|
// Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
|
2013-03-12 14:12:16 +00:00
|
|
|
if (OpC == PPC::SPILL_CR) {
|
2013-03-23 19:36:47 +00:00
|
|
|
lowerCRSpilling(II, FrameIndex);
|
2013-03-12 14:12:16 +00:00
|
|
|
return;
|
|
|
|
} else if (OpC == PPC::RESTORE_CR) {
|
2013-03-23 19:36:47 +00:00
|
|
|
lowerCRRestore(II, FrameIndex);
|
2013-03-12 14:12:16 +00:00
|
|
|
return;
|
2013-03-21 19:03:21 +00:00
|
|
|
} else if (OpC == PPC::SPILL_VRSAVE) {
|
2013-03-23 19:36:47 +00:00
|
|
|
lowerVRSAVESpilling(II, FrameIndex);
|
2013-03-21 19:03:21 +00:00
|
|
|
return;
|
|
|
|
} else if (OpC == PPC::RESTORE_VRSAVE) {
|
2013-03-23 19:36:47 +00:00
|
|
|
lowerVRSAVERestore(II, FrameIndex);
|
2013-03-21 19:03:21 +00:00
|
|
|
return;
|
2011-12-06 20:55:36 +00:00
|
|
|
}
|
2004-08-17 04:55:41 +00:00
|
|
|
|
|
|
|
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
|
2011-12-07 06:34:02 +00:00
|
|
|
|
|
|
|
bool is64Bit = Subtarget.isPPC64();
|
2013-01-31 20:02:54 +00:00
|
|
|
MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
|
2011-12-07 06:34:02 +00:00
|
|
|
(is64Bit ? PPC::X31 : PPC::R31) :
|
|
|
|
(is64Bit ? PPC::X1 : PPC::R1),
|
2007-10-16 18:00:18 +00:00
|
|
|
false);
|
2004-08-17 04:55:41 +00:00
|
|
|
|
2013-04-09 17:27:09 +00:00
|
|
|
// Figure out if the offset in the instruction is shifted right two bits.
|
|
|
|
bool isIXAddr = usesIXAddr(MI);
|
2013-03-17 04:43:44 +00:00
|
|
|
|
2013-03-31 14:43:31 +00:00
|
|
|
// If the instruction is not present in ImmToIdxMap, then it has no immediate
|
|
|
|
// form (and must be r+r).
|
2013-04-01 17:02:06 +00:00
|
|
|
bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC);
|
2013-03-17 04:43:44 +00:00
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
// Now add the frame object offset to the offset from r1.
|
2006-11-16 22:43:37 +00:00
|
|
|
int Offset = MFI->getObjectOffset(FrameIndex);
|
2013-05-16 17:58:02 +00:00
|
|
|
Offset += MI.getOperand(OffsetOperandNo).getImm();
|
2004-08-17 04:55:41 +00:00
|
|
|
|
|
|
|
// If we're not using a Frame Pointer that has been set to the value of the
|
|
|
|
// SP before having the stack size subtracted from it, then add the stack size
|
|
|
|
// to Offset to get the correct offset.
|
2010-04-29 19:32:19 +00:00
|
|
|
// Naked functions have stack size 0, although getStackSize may not reflect that
|
|
|
|
// because we didn't call all the pieces that compute it for naked functions.
|
2012-12-30 10:32:01 +00:00
|
|
|
if (!MF.getFunction()->getAttributes().
|
|
|
|
hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked))
|
2010-04-29 19:32:19 +00:00
|
|
|
Offset += MFI->getStackSize();
|
2005-04-21 23:30:14 +00:00
|
|
|
|
2007-11-27 22:14:42 +00:00
|
|
|
// If we can, encode the offset directly into the instruction. If this is a
|
|
|
|
// normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
|
|
|
|
// this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
|
|
|
|
// clear can be encoded. This is extremely uncommon, because normally you
|
|
|
|
// only "std" to a stack slot that is at least 4-byte aligned, but it can
|
|
|
|
// happen in invalid code.
|
2012-03-22 05:28:19 +00:00
|
|
|
if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
|
2013-03-17 04:43:44 +00:00
|
|
|
(!noImmForm &&
|
|
|
|
isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
|
2007-10-16 18:00:18 +00:00
|
|
|
MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
|
2010-08-26 23:32:16 +00:00
|
|
|
return;
|
2007-11-27 22:14:42 +00:00
|
|
|
}
|
2008-03-03 22:19:16 +00:00
|
|
|
|
|
|
|
// The offset doesn't fit into a single register, scavenge one to build the
|
|
|
|
// offset in.
|
|
|
|
|
2013-03-12 14:12:16 +00:00
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
2013-03-26 18:57:20 +00:00
|
|
|
const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
|
|
|
|
unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
|
|
|
|
SReg = MF.getRegInfo().createVirtualRegister(RC);
|
2008-03-03 22:19:16 +00:00
|
|
|
|
|
|
|
// Insert a set of rA with the full offset value before the ld, st, or add
|
2013-03-26 18:57:20 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
|
2008-03-03 22:19:16 +00:00
|
|
|
.addImm(Offset >> 16);
|
2011-12-07 06:34:02 +00:00
|
|
|
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
|
2013-03-26 18:57:20 +00:00
|
|
|
.addReg(SRegHi, RegState::Kill)
|
2008-03-03 22:19:16 +00:00
|
|
|
.addImm(Offset);
|
|
|
|
|
|
|
|
// Convert into indexed form of the instruction:
|
|
|
|
//
|
|
|
|
// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
|
|
|
|
// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
|
2007-11-27 22:14:42 +00:00
|
|
|
unsigned OperandBase;
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2013-03-17 04:43:44 +00:00
|
|
|
if (noImmForm)
|
|
|
|
OperandBase = 1;
|
|
|
|
else if (OpC != TargetOpcode::INLINEASM) {
|
2007-11-27 22:14:42 +00:00
|
|
|
assert(ImmToIdxMap.count(OpC) &&
|
|
|
|
"No indexed form of load or store available!");
|
|
|
|
unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
|
2008-01-11 18:10:50 +00:00
|
|
|
MI.setDesc(TII.get(NewOpcode));
|
2007-11-27 22:14:42 +00:00
|
|
|
OperandBase = 1;
|
2007-10-16 18:00:18 +00:00
|
|
|
} else {
|
2007-11-27 22:14:42 +00:00
|
|
|
OperandBase = OffsetOperandNo;
|
2004-08-17 04:55:41 +00:00
|
|
|
}
|
2010-08-26 23:32:16 +00:00
|
|
|
|
2013-01-31 20:02:54 +00:00
|
|
|
unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
|
2007-11-27 22:14:42 +00:00
|
|
|
MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
|
2011-12-30 00:34:00 +00:00
|
|
|
MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
|
2004-08-17 04:55:41 +00:00
|
|
|
}
|
|
|
|
|
2009-11-12 20:49:22 +00:00
|
|
|
unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
2011-01-10 12:39:04 +00:00
|
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
2010-11-18 21:19:35 +00:00
|
|
|
|
2006-11-11 19:05:28 +00:00
|
|
|
if (!Subtarget.isPPC64())
|
2010-11-18 21:19:35 +00:00
|
|
|
return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
|
2006-11-11 19:05:28 +00:00
|
|
|
else
|
2010-11-18 21:19:35 +00:00
|
|
|
return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
|
2006-04-07 16:34:46 +00:00
|
|
|
}
|
|
|
|
|
2007-02-21 22:54:50 +00:00
|
|
|
unsigned PPCRegisterInfo::getEHExceptionRegister() const {
|
|
|
|
return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCRegisterInfo::getEHHandlerRegister() const {
|
|
|
|
return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
|
|
|
|
}
|
2013-04-09 17:27:09 +00:00
|
|
|
|
|
|
|
/// Returns true if the instruction's frame index
|
|
|
|
/// reference would be better served by a base register other than FP
|
|
|
|
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
|
|
|
|
/// references it should create new base registers for.
|
|
|
|
bool PPCRegisterInfo::
|
|
|
|
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
|
|
|
|
assert(Offset < 0 && "Local offset must be negative");
|
|
|
|
|
|
|
|
unsigned FIOperandNum = 0;
|
|
|
|
while (!MI->getOperand(FIOperandNum).isFI()) {
|
|
|
|
++FIOperandNum;
|
|
|
|
assert(FIOperandNum < MI->getNumOperands() &&
|
|
|
|
"Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
|
2013-05-16 17:58:02 +00:00
|
|
|
Offset += MI->getOperand(OffsetOperandNo).getImm();
|
2013-04-09 17:27:09 +00:00
|
|
|
|
|
|
|
// It's the load/store FI references that cause issues, as it can be difficult
|
|
|
|
// to materialize the offset if it won't fit in the literal field. Estimate
|
|
|
|
// based on the size of the local frame and some conservative assumptions
|
|
|
|
// about the rest of the stack frame (note, this is pre-regalloc, so
|
|
|
|
// we don't know everything for certain yet) whether this offset is likely
|
|
|
|
// to be out of range of the immediate. Return true if so.
|
|
|
|
|
|
|
|
// We only generate virtual base registers for loads and stores that have
|
|
|
|
// an r+i form. Return false for everything else.
|
|
|
|
unsigned OpC = MI->getOpcode();
|
|
|
|
if (!ImmToIdxMap.count(OpC))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Don't generate a new virtual base register just to add zero to it.
|
|
|
|
if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
|
|
|
|
MI->getOperand(2).getImm() == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineBasicBlock &MBB = *MI->getParent();
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
|
|
|
|
const PPCFrameLowering *PPCFI =
|
|
|
|
static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
|
|
|
|
unsigned StackEst =
|
|
|
|
PPCFI->determineFrameLayout(MF, false, true);
|
|
|
|
|
|
|
|
// If we likely don't need a stack frame, then we probably don't need a
|
|
|
|
// virtual base register either.
|
|
|
|
if (!StackEst)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Estimate an offset from the stack pointer.
|
|
|
|
// The incoming offset is relating to the SP at the start of the function,
|
|
|
|
// but when we access the local it'll be relative to the SP after local
|
|
|
|
// allocation, so adjust our SP-relative offset by that allocation size.
|
|
|
|
Offset += StackEst;
|
|
|
|
|
|
|
|
// The frame pointer will point to the end of the stack, so estimate the
|
|
|
|
// offset as the difference between the object offset and the FP location.
|
|
|
|
return !isFrameOffsetLegal(MI, Offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Insert defining instruction(s) for BaseReg to
|
|
|
|
/// be a pointer to FrameIdx at the beginning of the basic block.
|
|
|
|
void PPCRegisterInfo::
|
|
|
|
materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
|
|
|
unsigned BaseReg, int FrameIdx,
|
|
|
|
int64_t Offset) const {
|
|
|
|
unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
|
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MachineBasicBlock::iterator Ins = MBB->begin();
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DebugLoc DL; // Defaults to "unknown"
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if (Ins != MBB->end())
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DL = Ins->getDebugLoc();
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const MCInstrDesc &MCID = TII.get(ADDriOpc);
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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const MachineFunction &MF = *MBB->getParent();
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MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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BuildMI(*MBB, Ins, DL, MCID, BaseReg)
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.addFrameIndex(FrameIdx).addImm(Offset);
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}
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void
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PPCRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
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unsigned BaseReg, int64_t Offset) const {
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MachineInstr &MI = *I;
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unsigned FIOperandNum = 0;
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while (!MI.getOperand(FIOperandNum).isFI()) {
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++FIOperandNum;
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assert(FIOperandNum < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
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unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
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2013-05-16 17:58:02 +00:00
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Offset += MI.getOperand(OffsetOperandNo).getImm();
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2013-04-09 17:27:09 +00:00
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MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
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}
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bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
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int64_t Offset) const {
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return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
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(isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));
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}
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