2005-11-16 22:59:19 +00:00
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//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
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2005-11-16 01:54:32 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-11-16 01:54:32 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a DAG pattern matching instruction selector for X86,
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// converting from a legalized dag to a X86 dag.
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//
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//===----------------------------------------------------------------------===//
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2006-08-07 22:28:20 +00:00
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#define DEBUG_TYPE "x86-isel"
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2005-11-16 01:54:32 +00:00
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#include "X86.h"
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2006-01-11 06:09:51 +00:00
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#include "X86InstrBuilder.h"
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2006-03-13 23:20:37 +00:00
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#include "X86ISelLowering.h"
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2008-01-05 00:41:47 +00:00
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#include "X86MachineFunctionInfo.h"
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2006-01-11 01:15:34 +00:00
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#include "X86RegisterInfo.h"
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2005-11-16 01:54:32 +00:00
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#include "X86Subtarget.h"
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2006-03-13 23:20:37 +00:00
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#include "X86TargetMachine.h"
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2005-11-19 02:11:08 +00:00
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#include "llvm/GlobalValue.h"
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2006-01-11 01:15:34 +00:00
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#include "llvm/Instructions.h"
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2006-03-25 06:47:10 +00:00
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#include "llvm/Intrinsics.h"
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2006-01-11 01:15:34 +00:00
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#include "llvm/Support/CFG.h"
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2007-01-12 23:22:14 +00:00
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#include "llvm/Type.h"
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2005-11-19 02:11:08 +00:00
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#include "llvm/CodeGen/MachineConstantPool.h"
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2005-11-16 01:54:32 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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2006-01-10 20:26:56 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2006-01-11 01:15:34 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2005-11-16 01:54:32 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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2006-08-27 12:54:02 +00:00
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#include "llvm/Support/Compiler.h"
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2006-09-08 06:48:29 +00:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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2008-04-25 08:22:20 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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2005-11-16 01:54:32 +00:00
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#include "llvm/ADT/Statistic.h"
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2006-08-07 22:28:20 +00:00
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#include <queue>
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2006-02-05 06:46:41 +00:00
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#include <set>
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2005-11-16 01:54:32 +00:00
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using namespace llvm;
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2006-12-19 22:59:26 +00:00
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STATISTIC(NumFPKill , "Number of FP_REG_KILL instructions added");
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STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
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2005-11-16 01:54:32 +00:00
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//===----------------------------------------------------------------------===//
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// Pattern Matcher Implementation
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//===----------------------------------------------------------------------===//
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2005-11-19 02:11:08 +00:00
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namespace {
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/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
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2008-07-27 21:46:04 +00:00
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/// SDValue's instead of register numbers for the leaves of the matched
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2005-11-19 02:11:08 +00:00
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/// tree.
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struct X86ISelAddressMode {
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enum {
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RegBase,
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2006-05-24 17:04:05 +00:00
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FrameIndexBase
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2005-11-19 02:11:08 +00:00
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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2008-07-27 21:46:04 +00:00
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SDValue Reg;
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2005-11-19 02:11:08 +00:00
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int FrameIndex;
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} Base;
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Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
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bool isRIPRel; // RIP as base?
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2005-11-19 02:11:08 +00:00
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unsigned Scale;
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2008-07-27 21:46:04 +00:00
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SDValue IndexReg;
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2005-11-19 02:11:08 +00:00
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unsigned Disp;
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GlobalValue *GV;
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2006-02-25 10:09:08 +00:00
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Constant *CP;
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2006-09-08 06:48:29 +00:00
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const char *ES;
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int JT;
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2006-02-25 10:09:08 +00:00
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unsigned Align; // CP alignment.
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2005-11-19 02:11:08 +00:00
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X86ISelAddressMode()
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2006-09-08 06:48:29 +00:00
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: BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
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GV(0), CP(0), ES(0), JT(-1), Align(0) {
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2005-11-19 02:11:08 +00:00
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}
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};
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}
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2005-11-16 01:54:32 +00:00
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namespace {
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//===--------------------------------------------------------------------===//
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/// ISel - X86 specific code to select X86 machine instructions for
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/// SelectionDAG operations.
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///
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2006-06-28 23:27:49 +00:00
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class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
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2005-11-16 01:54:32 +00:00
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/// ContainsFPCode - Every instruction we select that uses or defines a FP
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/// register should set this to true.
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bool ContainsFPCode;
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2006-09-08 06:48:29 +00:00
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/// TM - Keep a reference to X86TargetMachine.
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///
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X86TargetMachine &TM;
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2005-11-16 01:54:32 +00:00
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/// X86Lowering - This object fully describes how to lower LLVM code to an
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/// X86-specific SelectionDAG.
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X86TargetLowering X86Lowering;
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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2006-02-18 00:15:05 +00:00
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2006-09-08 06:48:29 +00:00
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/// GlobalBaseReg - keeps track of the virtual register mapped onto global
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/// base register.
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2006-02-18 00:15:05 +00:00
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unsigned GlobalBaseReg;
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2006-07-27 16:44:36 +00:00
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2008-06-30 20:45:06 +00:00
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/// CurBB - Current BB being isel'd.
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///
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MachineBasicBlock *CurBB;
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2005-11-16 01:54:32 +00:00
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public:
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2006-09-08 06:48:29 +00:00
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X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
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2008-07-01 18:05:03 +00:00
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: SelectionDAGISel(X86Lowering, fast),
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ContainsFPCode(false), TM(tm),
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2006-07-27 16:44:36 +00:00
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X86Lowering(*TM.getTargetLowering()),
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2006-08-08 00:31:00 +00:00
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Subtarget(&TM.getSubtarget<X86Subtarget>()) {}
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2005-11-16 01:54:32 +00:00
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2006-02-18 00:15:05 +00:00
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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return SelectionDAGISel::runOnFunction(Fn);
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}
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2005-11-16 01:54:32 +00:00
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virtual const char *getPassName() const {
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return "X86 DAG->DAG Instruction Selection";
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}
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2008-06-30 20:45:06 +00:00
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/// InstructionSelect - This callback is invoked by
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2005-11-16 01:54:32 +00:00
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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2008-06-30 20:45:06 +00:00
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virtual void InstructionSelect(SelectionDAG &DAG);
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/// InstructionSelectPostProcessing - Post processing of selected and
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/// scheduled basic blocks.
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2008-07-21 20:00:07 +00:00
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virtual void InstructionSelectPostProcessing();
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2005-11-16 01:54:32 +00:00
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2007-09-25 21:52:30 +00:00
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
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2007-07-24 23:00:27 +00:00
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virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const;
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2006-07-27 16:44:36 +00:00
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2005-11-16 01:54:32 +00:00
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// Include the pieces autogenerated from the target description.
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#include "X86GenDAGISel.inc"
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private:
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2008-07-27 21:46:04 +00:00
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SDNode *Select(SDValue N);
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2005-11-16 01:54:32 +00:00
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2008-07-27 21:46:04 +00:00
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bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
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2007-03-28 18:38:33 +00:00
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bool isRoot = true, unsigned Depth = 0);
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2008-07-27 21:46:04 +00:00
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bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
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2007-08-13 20:03:06 +00:00
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bool isRoot, unsigned Depth);
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2008-07-27 21:46:04 +00:00
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bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp);
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bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp);
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bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
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SDValue N, SDValue &Base, SDValue &Scale,
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SDValue &Index, SDValue &Disp,
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SDValue &InChain, SDValue &OutChain);
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bool TryFoldLoad(SDValue P, SDValue N,
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SDValue &Base, SDValue &Scale,
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SDValue &Index, SDValue &Disp);
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Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
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void PreprocessForRMW(SelectionDAG &DAG);
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void PreprocessForFPConvert(SelectionDAG &DAG);
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2006-08-07 22:28:20 +00:00
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2006-06-08 18:03:49 +00:00
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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2008-07-27 21:46:04 +00:00
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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2006-06-08 18:03:49 +00:00
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char ConstraintCode,
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2008-07-27 21:46:04 +00:00
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std::vector<SDValue> &OutOps,
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2006-06-08 18:03:49 +00:00
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SelectionDAG &DAG);
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2007-09-25 21:52:30 +00:00
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void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
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2008-07-27 21:46:04 +00:00
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inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
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SDValue &Scale, SDValue &Index,
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SDValue &Disp) {
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2005-12-12 21:49:40 +00:00
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Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
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2006-09-08 06:48:29 +00:00
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CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
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AM.Base.Reg;
|
2005-12-17 09:13:43 +00:00
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Scale = getI8Imm(AM.Scale);
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2005-12-12 21:49:40 +00:00
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Index = AM.IndexReg;
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2006-09-08 06:48:29 +00:00
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// These are 32-bit even in 64-bit mode since RIP relative offset
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// is 32-bit.
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if (AM.GV)
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Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
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else if (AM.CP)
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Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp);
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else if (AM.ES)
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Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
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else if (AM.JT != -1)
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Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
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else
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Disp = getI32Imm(AM.Disp);
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2005-12-12 21:49:40 +00:00
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}
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2005-11-19 02:11:08 +00:00
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/// getI8Imm - Return a target constant with the specified value, of type
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/// i8.
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2008-07-27 21:46:04 +00:00
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inline SDValue getI8Imm(unsigned Imm) {
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2005-11-19 02:11:08 +00:00
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return CurDAG->getTargetConstant(Imm, MVT::i8);
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}
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2005-11-16 01:54:32 +00:00
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/// getI16Imm - Return a target constant with the specified value, of type
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/// i16.
|
2008-07-27 21:46:04 +00:00
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inline SDValue getI16Imm(unsigned Imm) {
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2005-11-16 01:54:32 +00:00
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return CurDAG->getTargetConstant(Imm, MVT::i16);
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
|
2008-07-27 21:46:04 +00:00
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inline SDValue getI32Imm(unsigned Imm) {
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2005-11-16 01:54:32 +00:00
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
|
2006-02-10 22:24:32 +00:00
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2006-02-18 00:15:05 +00:00
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/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
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/// base register. Return the virtual register that holds this value.
|
2006-08-26 05:34:46 +00:00
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SDNode *getGlobalBaseReg();
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2006-02-18 00:15:05 +00:00
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2007-08-10 21:48:46 +00:00
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/// getTruncate - return an SDNode that implements a subreg based truncate
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/// of the specified operand to the the specified value type.
|
2008-07-27 21:46:04 +00:00
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SDNode *getTruncate(SDValue N0, MVT VT);
|
2007-08-10 21:48:46 +00:00
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2006-02-10 22:46:26 +00:00
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#ifndef NDEBUG
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unsigned Indent;
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#endif
|
2005-11-16 01:54:32 +00:00
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};
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}
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2008-04-25 08:22:20 +00:00
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/// findFlagUse - Return use of MVT::Flag value produced by the specified SDNode.
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///
|
2006-10-10 01:46:56 +00:00
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static SDNode *findFlagUse(SDNode *N) {
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unsigned FlagResNo = N->getNumValues()-1;
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|
|
for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
|
2008-07-27 20:43:25 +00:00
|
|
|
SDNode *User = *I;
|
2006-10-10 01:46:56 +00:00
|
|
|
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Op = User->getOperand(i);
|
2006-10-12 19:13:59 +00:00
|
|
|
if (Op.Val == N && Op.ResNo == FlagResNo)
|
2006-10-10 01:46:56 +00:00
|
|
|
return User;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2008-04-25 08:22:20 +00:00
|
|
|
/// findNonImmUse - Return true by reference in "found" if "Use" is an
|
|
|
|
/// non-immediate use of "Def". This function recursively traversing
|
|
|
|
/// up the operand chain ignoring certain nodes.
|
2006-10-14 08:33:25 +00:00
|
|
|
static void findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
|
|
|
|
SDNode *Root, SDNode *Skip, bool &found,
|
2008-04-25 08:22:20 +00:00
|
|
|
SmallPtrSet<SDNode*, 16> &Visited) {
|
2006-08-08 00:31:00 +00:00
|
|
|
if (found ||
|
|
|
|
Use->getNodeId() > Def->getNodeId() ||
|
2008-04-25 08:22:20 +00:00
|
|
|
!Visited.insert(Use))
|
2006-08-08 00:31:00 +00:00
|
|
|
return;
|
2008-04-25 08:22:20 +00:00
|
|
|
|
2006-10-14 08:33:25 +00:00
|
|
|
for (unsigned i = 0, e = Use->getNumOperands(); !found && i != e; ++i) {
|
2006-08-08 00:31:00 +00:00
|
|
|
SDNode *N = Use->getOperand(i).Val;
|
2006-10-14 08:33:25 +00:00
|
|
|
if (N == Skip)
|
2006-10-10 01:46:56 +00:00
|
|
|
continue;
|
2006-10-14 08:33:25 +00:00
|
|
|
if (N == Def) {
|
|
|
|
if (Use == ImmedUse)
|
2008-04-25 08:55:28 +00:00
|
|
|
continue; // We are not looking for immediate use.
|
2006-10-14 08:33:25 +00:00
|
|
|
if (Use == Root) {
|
2008-04-25 08:55:28 +00:00
|
|
|
// Must be a chain reading node where it is possible to reach its own
|
|
|
|
// chain operand through a path started from another operand.
|
2006-10-14 08:33:25 +00:00
|
|
|
assert(Use->getOpcode() == ISD::STORE ||
|
2008-04-25 05:13:01 +00:00
|
|
|
Use->getOpcode() == X86ISD::CMP ||
|
|
|
|
Use->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
|
|
|
|
Use->getOpcode() == ISD::INTRINSIC_VOID);
|
2006-10-14 08:33:25 +00:00
|
|
|
continue;
|
|
|
|
}
|
2006-08-08 00:31:00 +00:00
|
|
|
found = true;
|
|
|
|
break;
|
|
|
|
}
|
2008-04-25 08:22:20 +00:00
|
|
|
|
|
|
|
// Traverse up the operand chain.
|
2006-10-14 08:33:25 +00:00
|
|
|
findNonImmUse(N, Def, ImmedUse, Root, Skip, found, Visited);
|
2006-08-08 00:31:00 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-10-14 08:33:25 +00:00
|
|
|
/// isNonImmUse - Start searching from Root up the DAG to check is Def can
|
|
|
|
/// be reached. Return true if that's the case. However, ignore direct uses
|
|
|
|
/// by ImmedUse (which would be U in the example illustrated in
|
|
|
|
/// CanBeFoldedBy) and by Root (which can happen in the store case).
|
|
|
|
/// FIXME: to be really generic, we should allow direct use by any node
|
|
|
|
/// that is being folded. But realisticly since we only fold loads which
|
|
|
|
/// have one non-chain use, we only need to watch out for load/op/store
|
|
|
|
/// and load/op/cmp case where the root (store / cmp) may reach the load via
|
|
|
|
/// its chain operand.
|
|
|
|
static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse,
|
|
|
|
SDNode *Skip = NULL) {
|
2008-04-25 08:22:20 +00:00
|
|
|
SmallPtrSet<SDNode*, 16> Visited;
|
2006-08-08 00:31:00 +00:00
|
|
|
bool found = false;
|
2006-10-14 08:33:25 +00:00
|
|
|
findNonImmUse(Root, Def, ImmedUse, Root, Skip, found, Visited);
|
2006-08-08 00:31:00 +00:00
|
|
|
return found;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-07-24 23:00:27 +00:00
|
|
|
bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
|
2006-10-14 08:33:25 +00:00
|
|
|
if (FastISel) return false;
|
|
|
|
|
2006-07-27 16:44:36 +00:00
|
|
|
// If U use can somehow reach N through another path then U can't fold N or
|
|
|
|
// it will create a cycle. e.g. In the following diagram, U can reach N
|
2006-07-28 06:33:41 +00:00
|
|
|
// through X. If N is folded into into U, then X is both a predecessor and
|
2006-07-27 16:44:36 +00:00
|
|
|
// a successor of U.
|
|
|
|
//
|
|
|
|
// [ N ]
|
|
|
|
// ^ ^
|
|
|
|
// | |
|
|
|
|
// / \---
|
|
|
|
// / [X]
|
|
|
|
// | ^
|
|
|
|
// [U]--------|
|
2006-10-14 08:33:25 +00:00
|
|
|
|
|
|
|
if (isNonImmUse(Root, N, U))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If U produces a flag, then it gets (even more) interesting. Since it
|
|
|
|
// would have been "glued" together with its flag use, we need to check if
|
|
|
|
// it might reach N:
|
|
|
|
//
|
|
|
|
// [ N ]
|
|
|
|
// ^ ^
|
|
|
|
// | |
|
|
|
|
// [U] \--
|
|
|
|
// ^ [TF]
|
|
|
|
// | ^
|
|
|
|
// | |
|
|
|
|
// \ /
|
|
|
|
// [FU]
|
|
|
|
//
|
|
|
|
// If FU (flag use) indirectly reach N (the load), and U fold N (call it
|
|
|
|
// NU), then TF is a predecessor of FU and a successor of NU. But since
|
|
|
|
// NU and FU are flagged together, this effectively creates a cycle.
|
|
|
|
bool HasFlagUse = false;
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Root->getValueType(Root->getNumValues()-1);
|
2006-10-14 08:33:25 +00:00
|
|
|
while ((VT == MVT::Flag && !Root->use_empty())) {
|
|
|
|
SDNode *FU = findFlagUse(Root);
|
|
|
|
if (FU == NULL)
|
|
|
|
break;
|
|
|
|
else {
|
|
|
|
Root = FU;
|
|
|
|
HasFlagUse = true;
|
2006-10-10 01:46:56 +00:00
|
|
|
}
|
2006-10-14 08:33:25 +00:00
|
|
|
VT = Root->getValueType(Root->getNumValues()-1);
|
2006-10-10 01:46:56 +00:00
|
|
|
}
|
2006-10-14 08:33:25 +00:00
|
|
|
|
|
|
|
if (HasFlagUse)
|
|
|
|
return !isNonImmUse(Root, N, Root, U);
|
|
|
|
return true;
|
2006-07-27 16:44:36 +00:00
|
|
|
}
|
|
|
|
|
2006-08-28 20:10:17 +00:00
|
|
|
/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
|
|
|
|
/// and move load below the TokenFactor. Replace store's chain operand with
|
|
|
|
/// load's chain result.
|
2008-07-27 21:46:04 +00:00
|
|
|
static void MoveBelowTokenFactor(SelectionDAG &DAG, SDValue Load,
|
|
|
|
SDValue Store, SDValue TF) {
|
|
|
|
std::vector<SDValue> Ops;
|
2006-08-28 20:10:17 +00:00
|
|
|
for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
|
|
|
|
if (Load.Val == TF.Val->getOperand(i).Val)
|
|
|
|
Ops.push_back(Load.Val->getOperand(0));
|
|
|
|
else
|
|
|
|
Ops.push_back(TF.Val->getOperand(i));
|
|
|
|
DAG.UpdateNodeOperands(TF, &Ops[0], Ops.size());
|
|
|
|
DAG.UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
|
|
|
|
DAG.UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
|
|
|
|
Store.getOperand(2), Store.getOperand(3));
|
|
|
|
}
|
|
|
|
|
2008-05-23 21:23:16 +00:00
|
|
|
/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
|
|
|
|
///
|
2008-07-27 21:46:04 +00:00
|
|
|
static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
|
|
|
|
SDValue &Load) {
|
2008-05-23 21:23:16 +00:00
|
|
|
if (N.getOpcode() == ISD::BIT_CONVERT)
|
|
|
|
N = N.getOperand(0);
|
|
|
|
|
|
|
|
LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
|
|
|
|
if (!LD || LD->isVolatile())
|
|
|
|
return false;
|
|
|
|
if (LD->getAddressingMode() != ISD::UNINDEXED)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
ISD::LoadExtType ExtType = LD->getExtensionType();
|
|
|
|
if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (N.hasOneUse() &&
|
|
|
|
N.getOperand(1) == Address &&
|
|
|
|
N.Val->isOperandOf(Chain.Val)) {
|
|
|
|
Load = N;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
/// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
|
|
|
|
/// This is only run if not in -fast mode (aka -O0).
|
|
|
|
/// This allows the instruction selector to pick more read-modify-write
|
|
|
|
/// instructions. This is a common case:
|
2006-08-28 20:10:17 +00:00
|
|
|
///
|
|
|
|
/// [Load chain]
|
|
|
|
/// ^
|
|
|
|
/// |
|
|
|
|
/// [Load]
|
|
|
|
/// ^ ^
|
|
|
|
/// | |
|
|
|
|
/// / \-
|
|
|
|
/// / |
|
|
|
|
/// [TokenFactor] [Op]
|
|
|
|
/// ^ ^
|
|
|
|
/// | |
|
|
|
|
/// \ /
|
|
|
|
/// \ /
|
|
|
|
/// [Store]
|
|
|
|
///
|
|
|
|
/// The fact the store's chain operand != load's chain will prevent the
|
|
|
|
/// (store (op (load))) instruction from being selected. We can transform it to:
|
|
|
|
///
|
|
|
|
/// [Load chain]
|
|
|
|
/// ^
|
|
|
|
/// |
|
|
|
|
/// [TokenFactor]
|
|
|
|
/// ^
|
|
|
|
/// |
|
|
|
|
/// [Load]
|
|
|
|
/// ^ ^
|
|
|
|
/// | |
|
|
|
|
/// | \-
|
|
|
|
/// | |
|
|
|
|
/// | [Op]
|
|
|
|
/// | ^
|
|
|
|
/// | |
|
|
|
|
/// \ /
|
|
|
|
/// \ /
|
|
|
|
/// [Store]
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
|
2006-08-28 20:10:17 +00:00
|
|
|
for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
|
|
|
|
E = DAG.allnodes_end(); I != E; ++I) {
|
2006-10-13 21:14:26 +00:00
|
|
|
if (!ISD::isNON_TRUNCStore(I))
|
2006-08-28 20:10:17 +00:00
|
|
|
continue;
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Chain = I->getOperand(0);
|
2006-08-28 20:10:17 +00:00
|
|
|
if (Chain.Val->getOpcode() != ISD::TokenFactor)
|
|
|
|
continue;
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N1 = I->getOperand(1);
|
|
|
|
SDValue N2 = I->getOperand(2);
|
2008-06-06 12:08:01 +00:00
|
|
|
if ((N1.getValueType().isFloatingPoint() &&
|
|
|
|
!N1.getValueType().isVector()) ||
|
2006-08-29 18:37:37 +00:00
|
|
|
!N1.hasOneUse())
|
2006-08-28 20:10:17 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
bool RModW = false;
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Load;
|
2006-08-28 20:10:17 +00:00
|
|
|
unsigned Opcode = N1.Val->getOpcode();
|
|
|
|
switch (Opcode) {
|
|
|
|
case ISD::ADD:
|
|
|
|
case ISD::MUL:
|
|
|
|
case ISD::AND:
|
|
|
|
case ISD::OR:
|
|
|
|
case ISD::XOR:
|
|
|
|
case ISD::ADDC:
|
2008-05-23 21:23:16 +00:00
|
|
|
case ISD::ADDE:
|
|
|
|
case ISD::VECTOR_SHUFFLE: {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N10 = N1.getOperand(0);
|
|
|
|
SDValue N11 = N1.getOperand(1);
|
2008-05-23 21:23:16 +00:00
|
|
|
RModW = isRMWLoad(N10, Chain, N2, Load);
|
|
|
|
if (!RModW)
|
|
|
|
RModW = isRMWLoad(N11, Chain, N2, Load);
|
2006-08-28 20:10:17 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SUB:
|
|
|
|
case ISD::SHL:
|
|
|
|
case ISD::SRA:
|
|
|
|
case ISD::SRL:
|
|
|
|
case ISD::ROTL:
|
|
|
|
case ISD::ROTR:
|
|
|
|
case ISD::SUBC:
|
|
|
|
case ISD::SUBE:
|
|
|
|
case X86ISD::SHLD:
|
|
|
|
case X86ISD::SHRD: {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N10 = N1.getOperand(0);
|
2008-05-23 21:23:16 +00:00
|
|
|
RModW = isRMWLoad(N10, Chain, N2, Load);
|
2006-08-28 20:10:17 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-08-29 06:44:17 +00:00
|
|
|
if (RModW) {
|
2008-07-27 21:46:04 +00:00
|
|
|
MoveBelowTokenFactor(DAG, Load, SDValue(I, 0), Chain);
|
2006-08-29 06:44:17 +00:00
|
|
|
++NumLoadMoved;
|
|
|
|
}
|
2006-08-28 20:10:17 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
|
|
|
|
/// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
|
|
|
|
/// nodes that target the FP stack to be store and load to the stack. This is a
|
|
|
|
/// gross hack. We would like to simply mark these as being illegal, but when
|
|
|
|
/// we do that, legalize produces these when it expands calls, then expands
|
|
|
|
/// these in the same legalize pass. We would like dag combine to be able to
|
|
|
|
/// hack on these between the call expansion and the node legalization. As such
|
|
|
|
/// this pass basically does "really late" legalization of these inline with the
|
|
|
|
/// X86 isel pass.
|
|
|
|
void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
|
|
|
|
for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
|
|
|
|
E = DAG.allnodes_end(); I != E; ) {
|
|
|
|
SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
|
|
|
|
if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// If the source and destination are SSE registers, then this is a legal
|
|
|
|
// conversion that should not be lowered.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT SrcVT = N->getOperand(0).getValueType();
|
|
|
|
MVT DstVT = N->getValueType(0);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
|
|
|
|
bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
|
|
|
|
if (SrcIsSSE && DstIsSSE)
|
|
|
|
continue;
|
|
|
|
|
2008-03-09 07:05:32 +00:00
|
|
|
if (!SrcIsSSE && !DstIsSSE) {
|
|
|
|
// If this is an FPStack extension, it is a noop.
|
|
|
|
if (N->getOpcode() == ISD::FP_EXTEND)
|
|
|
|
continue;
|
|
|
|
// If this is a value-preserving FPStack truncation, it is a noop.
|
|
|
|
if (N->getConstantOperandVal(1))
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
// Here we could have an FP stack truncation or an FPStack <-> SSE convert.
|
|
|
|
// FPStack has extload and truncstore. SSE can fold direct loads into other
|
|
|
|
// operations. Based on this, decide what we want to do.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT MemVT;
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
if (N->getOpcode() == ISD::FP_ROUND)
|
|
|
|
MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
|
|
|
|
else
|
|
|
|
MemVT = SrcIsSSE ? SrcVT : DstVT;
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MemTmp = DAG.CreateStackTemporary(MemVT);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
|
|
|
|
// FIXME: optimize the case where the src/dest is a load or store?
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0),
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
MemTmp, NULL, 0, MemVT);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
NULL, 0, MemVT);
|
|
|
|
|
|
|
|
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
|
|
|
|
// extload we created. This will cause general havok on the dag because
|
|
|
|
// anything below the conversion could be folded into other existing nodes.
|
|
|
|
// To avoid invalidating 'I', back it up to the convert node.
|
|
|
|
--I;
|
2008-07-27 21:46:04 +00:00
|
|
|
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
|
|
|
|
// Now that we did that, the node is dead. Increment the iterator to the
|
|
|
|
// next node to process, then delete N.
|
|
|
|
++I;
|
|
|
|
DAG.DeleteNode(N);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
|
|
|
|
/// when it has created a SelectionDAG for us to codegen.
|
2008-06-30 20:45:06 +00:00
|
|
|
void X86DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
|
|
|
|
CurBB = BB; // BB can change as result of isel.
|
2005-11-16 01:54:32 +00:00
|
|
|
|
2008-06-30 20:45:06 +00:00
|
|
|
DEBUG(BB->dump());
|
2006-08-29 18:28:33 +00:00
|
|
|
if (!FastISel)
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
PreprocessForRMW(DAG);
|
|
|
|
|
|
|
|
// FIXME: This should only happen when not -fast.
|
|
|
|
PreprocessForFPConvert(DAG);
|
2006-08-28 20:10:17 +00:00
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
// Codegen the basic block.
|
2006-02-10 22:24:32 +00:00
|
|
|
#ifndef NDEBUG
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << "===== Instruction selection begins:\n";
|
2006-02-10 22:46:26 +00:00
|
|
|
Indent = 0;
|
2006-02-10 22:24:32 +00:00
|
|
|
#endif
|
2006-02-05 06:46:41 +00:00
|
|
|
DAG.setRoot(SelectRoot(DAG.getRoot()));
|
2006-02-10 22:24:32 +00:00
|
|
|
#ifndef NDEBUG
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << "===== Instruction selection ends:\n";
|
2006-02-10 22:24:32 +00:00
|
|
|
#endif
|
2006-07-28 00:10:59 +00:00
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
DAG.RemoveDeadNodes();
|
2008-06-30 20:45:06 +00:00
|
|
|
}
|
2005-11-16 01:54:32 +00:00
|
|
|
|
2008-07-21 20:00:07 +00:00
|
|
|
void X86DAGToDAGISel::InstructionSelectPostProcessing() {
|
2006-01-11 01:15:34 +00:00
|
|
|
// If we are emitting FP stack code, scan the basic block to determine if this
|
|
|
|
// block defines any FP values. If so, put an FP_REG_KILL instruction before
|
|
|
|
// the terminator of the block.
|
2007-08-07 20:29:26 +00:00
|
|
|
|
2007-09-24 22:52:39 +00:00
|
|
|
// Note that FP stack instructions are used in all modes for long double,
|
|
|
|
// so we always need to do this check.
|
|
|
|
// Also note that it's possible for an FP stack register to be live across
|
|
|
|
// an instruction that produces multiple basic blocks (SSE CMOV) so we
|
|
|
|
// must check all the generated basic blocks.
|
2007-08-07 20:29:26 +00:00
|
|
|
|
|
|
|
// Scan all of the machine instructions in these MBBs, checking for FP
|
|
|
|
// stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
|
2008-06-30 20:45:06 +00:00
|
|
|
MachineFunction::iterator MBBI = CurBB;
|
2008-03-10 23:34:12 +00:00
|
|
|
MachineFunction::iterator EndMBB = BB; ++EndMBB;
|
|
|
|
for (; MBBI != EndMBB; ++MBBI) {
|
|
|
|
MachineBasicBlock *MBB = MBBI;
|
|
|
|
|
|
|
|
// If this block returns, ignore it. We don't want to insert an FP_REG_KILL
|
|
|
|
// before the return.
|
|
|
|
if (!MBB->empty()) {
|
|
|
|
MachineBasicBlock::iterator EndI = MBB->end();
|
|
|
|
--EndI;
|
|
|
|
if (EndI->getDesc().isReturn())
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2007-09-24 22:52:39 +00:00
|
|
|
bool ContainsFPCode = false;
|
2008-03-10 23:34:12 +00:00
|
|
|
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
|
2007-08-07 20:29:26 +00:00
|
|
|
!ContainsFPCode && I != E; ++I) {
|
|
|
|
if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) {
|
|
|
|
const TargetRegisterClass *clas;
|
|
|
|
for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
|
|
|
|
if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
|
2008-03-10 23:34:12 +00:00
|
|
|
TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
|
2007-12-31 04:13:23 +00:00
|
|
|
((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) ==
|
2007-08-07 20:29:26 +00:00
|
|
|
X86::RFP32RegisterClass ||
|
|
|
|
clas == X86::RFP64RegisterClass ||
|
|
|
|
clas == X86::RFP80RegisterClass)) {
|
2006-01-11 01:15:34 +00:00
|
|
|
ContainsFPCode = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2007-09-24 22:52:39 +00:00
|
|
|
// Check PHI nodes in successor blocks. These PHI's will be lowered to have
|
|
|
|
// a copy of the input value in this block. In SSE mode, we only care about
|
|
|
|
// 80-bit values.
|
|
|
|
if (!ContainsFPCode) {
|
|
|
|
// Final check, check LLVM BB's that are successors to the LLVM BB
|
|
|
|
// corresponding to BB for FP PHI nodes.
|
|
|
|
const BasicBlock *LLVMBB = BB->getBasicBlock();
|
|
|
|
const PHINode *PN;
|
|
|
|
for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
|
|
|
|
!ContainsFPCode && SI != E; ++SI) {
|
|
|
|
for (BasicBlock::const_iterator II = SI->begin();
|
|
|
|
(PN = dyn_cast<PHINode>(II)); ++II) {
|
|
|
|
if (PN->getType()==Type::X86_FP80Ty ||
|
|
|
|
(!Subtarget->hasSSE1() && PN->getType()->isFloatingPoint()) ||
|
|
|
|
(!Subtarget->hasSSE2() && PN->getType()==Type::DoubleTy)) {
|
|
|
|
ContainsFPCode = true;
|
|
|
|
break;
|
|
|
|
}
|
2007-08-07 20:29:26 +00:00
|
|
|
}
|
|
|
|
}
|
2006-01-11 01:15:34 +00:00
|
|
|
}
|
2007-09-24 22:52:39 +00:00
|
|
|
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
|
|
|
|
if (ContainsFPCode) {
|
2008-03-10 23:34:12 +00:00
|
|
|
BuildMI(*MBB, MBBI->getFirstTerminator(),
|
2007-09-24 22:52:39 +00:00
|
|
|
TM.getInstrInfo()->get(X86::FP_REG_KILL));
|
|
|
|
++NumFPKill;
|
|
|
|
}
|
2008-03-10 23:34:12 +00:00
|
|
|
}
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
|
|
|
|
2007-09-25 21:52:30 +00:00
|
|
|
/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
|
|
|
|
/// the main function.
|
|
|
|
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
|
|
|
|
MachineFrameInfo *MFI) {
|
|
|
|
const TargetInstrInfo *TII = TM.getInstrInfo();
|
|
|
|
if (Subtarget->isTargetCygMing())
|
|
|
|
BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
|
|
|
|
}
|
|
|
|
|
|
|
|
void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
|
|
|
|
// If this is main, emit special code for main.
|
|
|
|
MachineBasicBlock *BB = MF.begin();
|
|
|
|
if (Fn.hasExternalLinkage() && Fn.getName() == "main")
|
|
|
|
EmitSpecialCodeForMain(BB, MF.getFrameInfo());
|
|
|
|
}
|
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
/// MatchAddress - Add the specified node to the specified addressing mode,
|
|
|
|
/// returning true if it cannot be done. This just pattern matches for the
|
2007-12-08 07:22:58 +00:00
|
|
|
/// addressing mode.
|
2008-07-27 21:46:04 +00:00
|
|
|
bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
|
2007-03-28 18:36:33 +00:00
|
|
|
bool isRoot, unsigned Depth) {
|
2007-08-13 20:03:06 +00:00
|
|
|
// Limit recursion.
|
|
|
|
if (Depth > 5)
|
|
|
|
return MatchAddressBase(N, AM, isRoot, Depth);
|
2007-03-28 18:36:33 +00:00
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
// RIP relative addressing: %rip + 32-bit displacement!
|
|
|
|
if (AM.isRIPRel) {
|
|
|
|
if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
|
Fix a regression in the 32-bit port from the 64-bit port landing.
We now compile CodeGen/X86/lea-2.ll into:
_test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
leal -5(%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal (,%eax,4), %eax
addl 8(%esp), %eax
addl $4294967291, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30288 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-13 04:45:25 +00:00
|
|
|
int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
|
2006-09-08 06:48:29 +00:00
|
|
|
if (isInt32(AM.Disp + Val)) {
|
|
|
|
AM.Disp += Val;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-08-07 22:28:20 +00:00
|
|
|
int id = N.Val->getNodeId();
|
2007-12-13 00:43:27 +00:00
|
|
|
bool AlreadySelected = isSelected(id); // Already selected, not yet replaced.
|
2006-02-11 02:05:36 +00:00
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
switch (N.getOpcode()) {
|
|
|
|
default: break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case ISD::Constant: {
|
Fix a regression in the 32-bit port from the 64-bit port landing.
We now compile CodeGen/X86/lea-2.ll into:
_test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
leal -5(%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal (,%eax,4), %eax
addl 8(%esp), %eax
addl $4294967291, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30288 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-13 04:45:25 +00:00
|
|
|
int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
|
2006-09-08 06:48:29 +00:00
|
|
|
if (isInt32(AM.Disp + Val)) {
|
|
|
|
AM.Disp += Val;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2006-12-05 04:01:03 +00:00
|
|
|
case X86ISD::Wrapper: {
|
|
|
|
bool is64Bit = Subtarget->is64Bit();
|
2006-11-30 21:55:46 +00:00
|
|
|
// Under X86-64 non-small code model, GV (and friends) are 64-bits.
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
// Also, base and index reg must be 0 in order to use rip as base.
|
|
|
|
if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
|
|
|
|
AM.Base.Reg.Val || AM.IndexReg.Val))
|
2006-11-30 21:55:46 +00:00
|
|
|
break;
|
2006-12-05 19:50:18 +00:00
|
|
|
if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
|
|
|
|
break;
|
2006-09-08 06:48:29 +00:00
|
|
|
// If value is available in a register both base and index components have
|
|
|
|
// been picked, we can't fit the result available in the register in the
|
|
|
|
// addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
|
2007-12-13 00:43:27 +00:00
|
|
|
if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N0 = N.getOperand(0);
|
2006-12-05 19:50:18 +00:00
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
|
|
|
|
GlobalValue *GV = G->getGlobal();
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
AM.GV = GV;
|
|
|
|
AM.Disp += G->getOffset();
|
2008-02-12 19:20:46 +00:00
|
|
|
AM.isRIPRel = TM.getRelocationModel() != Reloc::Static &&
|
|
|
|
Subtarget->isPICStyleRIPRel();
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
return false;
|
2006-12-05 19:50:18 +00:00
|
|
|
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
AM.CP = CP->getConstVal();
|
|
|
|
AM.Align = CP->getAlignment();
|
|
|
|
AM.Disp += CP->getOffset();
|
2008-02-12 19:20:46 +00:00
|
|
|
AM.isRIPRel = TM.getRelocationModel() != Reloc::Static &&
|
|
|
|
Subtarget->isPICStyleRIPRel();
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
return false;
|
2006-12-05 19:50:18 +00:00
|
|
|
} else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
AM.ES = S->getSymbol();
|
2008-02-12 19:20:46 +00:00
|
|
|
AM.isRIPRel = TM.getRelocationModel() != Reloc::Static &&
|
|
|
|
Subtarget->isPICStyleRIPRel();
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
return false;
|
2006-12-05 19:50:18 +00:00
|
|
|
} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
AM.JT = J->getIndex();
|
2008-02-12 19:20:46 +00:00
|
|
|
AM.isRIPRel = TM.getRelocationModel() != Reloc::Static &&
|
|
|
|
Subtarget->isPICStyleRIPRel();
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
return false;
|
2005-12-08 02:01:35 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2006-11-30 21:55:46 +00:00
|
|
|
}
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2006-02-25 10:09:08 +00:00
|
|
|
case ISD::FrameIndex:
|
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
|
|
|
|
AM.BaseType = X86ISelAddressMode::FrameIndexBase;
|
|
|
|
AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
|
2005-12-17 09:13:43 +00:00
|
|
|
return false;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
break;
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
case ISD::SHL:
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1 || AM.isRIPRel)
|
2007-12-08 07:22:58 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
|
|
|
|
unsigned Val = CN->getValue();
|
|
|
|
if (Val == 1 || Val == 2 || Val == 3) {
|
|
|
|
AM.Scale = 1 << Val;
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ShVal = N.Val->getOperand(0);
|
2007-12-08 07:22:58 +00:00
|
|
|
|
|
|
|
// Okay, we know that we have a scale by now. However, if the scaled
|
|
|
|
// value is an add of something and a constant, we can fold the
|
|
|
|
// constant into the disp field here.
|
|
|
|
if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
|
|
|
|
isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
|
|
|
|
AM.IndexReg = ShVal.Val->getOperand(0);
|
|
|
|
ConstantSDNode *AddVal =
|
|
|
|
cast<ConstantSDNode>(ShVal.Val->getOperand(1));
|
|
|
|
uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
|
|
|
|
if (isInt32(Disp))
|
|
|
|
AM.Disp = Disp;
|
|
|
|
else
|
2005-11-19 02:11:08 +00:00
|
|
|
AM.IndexReg = ShVal;
|
2007-12-08 07:22:58 +00:00
|
|
|
} else {
|
|
|
|
AM.IndexReg = ShVal;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
2007-12-08 07:22:58 +00:00
|
|
|
return false;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
break;
|
2007-12-08 07:22:58 +00:00
|
|
|
}
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2007-10-22 20:22:24 +00:00
|
|
|
case ISD::SMUL_LOHI:
|
|
|
|
case ISD::UMUL_LOHI:
|
|
|
|
// A mul_lohi where we need the low part can be folded as a plain multiply.
|
|
|
|
if (N.ResNo != 0) break;
|
|
|
|
// FALL THROUGH
|
2005-11-19 02:11:08 +00:00
|
|
|
case ISD::MUL:
|
|
|
|
// X*[3,5,9] -> X+X*[2,4,8]
|
2007-12-13 00:43:27 +00:00
|
|
|
if (!AlreadySelected &&
|
2006-02-25 10:09:08 +00:00
|
|
|
AM.BaseType == X86ISelAddressMode::RegBase &&
|
|
|
|
AM.Base.Reg.Val == 0 &&
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
AM.IndexReg.Val == 0 &&
|
|
|
|
!AM.isRIPRel) {
|
2005-11-19 02:11:08 +00:00
|
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
|
|
|
|
if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
|
|
|
|
AM.Scale = unsigned(CN->getValue())-1;
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MulVal = N.Val->getOperand(0);
|
|
|
|
SDValue Reg;
|
2005-11-19 02:11:08 +00:00
|
|
|
|
|
|
|
// Okay, we know that we have a scale by now. However, if the scaled
|
|
|
|
// value is an add of something and a constant, we can fold the
|
|
|
|
// constant into the disp field here.
|
|
|
|
if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
|
|
|
|
isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
|
|
|
|
Reg = MulVal.Val->getOperand(0);
|
|
|
|
ConstantSDNode *AddVal =
|
|
|
|
cast<ConstantSDNode>(MulVal.Val->getOperand(1));
|
2006-09-08 06:48:29 +00:00
|
|
|
uint64_t Disp = AM.Disp + AddVal->getValue() * CN->getValue();
|
|
|
|
if (isInt32(Disp))
|
|
|
|
AM.Disp = Disp;
|
|
|
|
else
|
|
|
|
Reg = N.Val->getOperand(0);
|
2005-11-19 02:11:08 +00:00
|
|
|
} else {
|
|
|
|
Reg = N.Val->getOperand(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
AM.IndexReg = AM.Base.Reg = Reg;
|
|
|
|
return false;
|
|
|
|
}
|
2007-02-04 20:18:17 +00:00
|
|
|
}
|
2005-11-19 02:11:08 +00:00
|
|
|
break;
|
|
|
|
|
2007-02-04 20:18:17 +00:00
|
|
|
case ISD::ADD:
|
2007-12-13 00:43:27 +00:00
|
|
|
if (!AlreadySelected) {
|
2006-02-11 02:05:36 +00:00
|
|
|
X86ISelAddressMode Backup = AM;
|
2007-03-28 18:36:33 +00:00
|
|
|
if (!MatchAddress(N.Val->getOperand(0), AM, false, Depth+1) &&
|
|
|
|
!MatchAddress(N.Val->getOperand(1), AM, false, Depth+1))
|
2006-02-11 02:05:36 +00:00
|
|
|
return false;
|
|
|
|
AM = Backup;
|
2007-03-28 18:36:33 +00:00
|
|
|
if (!MatchAddress(N.Val->getOperand(1), AM, false, Depth+1) &&
|
|
|
|
!MatchAddress(N.Val->getOperand(0), AM, false, Depth+1))
|
2006-02-11 02:05:36 +00:00
|
|
|
return false;
|
|
|
|
AM = Backup;
|
|
|
|
}
|
2005-11-19 02:11:08 +00:00
|
|
|
break;
|
2006-05-30 06:59:36 +00:00
|
|
|
|
2007-02-04 20:18:17 +00:00
|
|
|
case ISD::OR:
|
|
|
|
// Handle "X | C" as "X + C" iff X is known to have C bits clear.
|
2007-12-13 00:43:27 +00:00
|
|
|
if (AlreadySelected) break;
|
2007-12-08 07:22:58 +00:00
|
|
|
|
|
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
|
|
|
|
X86ISelAddressMode Backup = AM;
|
|
|
|
// Start with the LHS as an addr mode.
|
|
|
|
if (!MatchAddress(N.getOperand(0), AM, false) &&
|
|
|
|
// Address could not have picked a GV address for the displacement.
|
|
|
|
AM.GV == NULL &&
|
|
|
|
// On x86-64, the resultant disp must fit in 32-bits.
|
|
|
|
isInt32(AM.Disp + CN->getSignExtended()) &&
|
|
|
|
// Check to see if the LHS & C is zero.
|
2008-02-25 21:11:39 +00:00
|
|
|
CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
|
2007-12-08 07:22:58 +00:00
|
|
|
AM.Disp += CN->getValue();
|
|
|
|
return false;
|
2006-05-30 06:59:36 +00:00
|
|
|
}
|
2007-12-08 07:22:58 +00:00
|
|
|
AM = Backup;
|
2006-05-30 06:59:36 +00:00
|
|
|
}
|
|
|
|
break;
|
2007-12-13 00:43:27 +00:00
|
|
|
|
|
|
|
case ISD::AND: {
|
|
|
|
// Handle "(x << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
|
|
|
|
// allows us to fold the shift into this addressing mode.
|
|
|
|
if (AlreadySelected) break;
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Shift = N.getOperand(0);
|
2007-12-13 00:43:27 +00:00
|
|
|
if (Shift.getOpcode() != ISD::SHL) break;
|
|
|
|
|
|
|
|
// Scale must not be used already.
|
|
|
|
if (AM.IndexReg.Val != 0 || AM.Scale != 1) break;
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
|
|
|
|
// Not when RIP is used as the base.
|
|
|
|
if (AM.isRIPRel) break;
|
2007-12-13 00:43:27 +00:00
|
|
|
|
|
|
|
ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
|
|
|
|
ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
|
|
|
|
if (!C1 || !C2) break;
|
|
|
|
|
|
|
|
// Not likely to be profitable if either the AND or SHIFT node has more
|
|
|
|
// than one use (unless all uses are for address computation). Besides,
|
|
|
|
// isel mechanism requires their node ids to be reused.
|
|
|
|
if (!N.hasOneUse() || !Shift.hasOneUse())
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Verify that the shift amount is something we can fold.
|
|
|
|
unsigned ShiftCst = C1->getValue();
|
|
|
|
if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Get the new AND mask, this folds to a constant.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
|
|
|
|
SDValue(C2, 0), SDValue(C1, 0));
|
|
|
|
SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
|
2007-12-13 00:43:27 +00:00
|
|
|
Shift.getOperand(0), NewANDMask);
|
|
|
|
NewANDMask.Val->setNodeId(Shift.Val->getNodeId());
|
|
|
|
NewAND.Val->setNodeId(N.Val->getNodeId());
|
|
|
|
|
|
|
|
AM.Scale = 1 << ShiftCst;
|
|
|
|
AM.IndexReg = NewAND;
|
|
|
|
return false;
|
|
|
|
}
|
2006-05-30 06:59:36 +00:00
|
|
|
}
|
2005-11-19 02:11:08 +00:00
|
|
|
|
2007-08-13 20:03:06 +00:00
|
|
|
return MatchAddressBase(N, AM, isRoot, Depth);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
|
|
|
|
/// specified addressing mode without any further recursion.
|
2008-07-27 21:46:04 +00:00
|
|
|
bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
|
2007-08-13 20:03:06 +00:00
|
|
|
bool isRoot, unsigned Depth) {
|
2005-11-19 02:11:08 +00:00
|
|
|
// Is the base register already occupied?
|
|
|
|
if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
|
|
|
|
// If so, check to see if the scale index register is set.
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
if (AM.IndexReg.Val == 0 && !AM.isRIPRel) {
|
2005-11-19 02:11:08 +00:00
|
|
|
AM.IndexReg = N;
|
|
|
|
AM.Scale = 1;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we cannot select it.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Default, generate it as a register.
|
|
|
|
AM.BaseType = X86ISelAddressMode::RegBase;
|
|
|
|
AM.Base.Reg = N;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-12-08 02:01:35 +00:00
|
|
|
/// SelectAddr - returns true if it is able pattern match an addressing mode.
|
|
|
|
/// It returns the operands which make up the maximal addressing mode it can
|
|
|
|
/// match by reference.
|
2008-07-27 21:46:04 +00:00
|
|
|
bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
|
|
|
|
SDValue &Scale, SDValue &Index,
|
|
|
|
SDValue &Disp) {
|
2005-12-08 02:01:35 +00:00
|
|
|
X86ISelAddressMode AM;
|
2006-01-11 06:09:51 +00:00
|
|
|
if (MatchAddress(N, AM))
|
|
|
|
return false;
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = N.getValueType();
|
2006-01-11 06:09:51 +00:00
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase) {
|
2006-02-05 05:25:07 +00:00
|
|
|
if (!AM.Base.Reg.Val)
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.Base.Reg = CurDAG->getRegister(0, VT);
|
2005-12-08 02:01:35 +00:00
|
|
|
}
|
2006-01-11 06:09:51 +00:00
|
|
|
|
2006-02-05 05:25:07 +00:00
|
|
|
if (!AM.IndexReg.Val)
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(0, VT);
|
2006-01-11 06:09:51 +00:00
|
|
|
|
|
|
|
getAddressOperands(AM, Base, Scale, Index, Disp);
|
|
|
|
return true;
|
2005-12-08 02:01:35 +00:00
|
|
|
}
|
|
|
|
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
/// isZeroNode - Returns true if Elt is a constant zero or a floating point
|
|
|
|
/// constant +0.0.
|
2008-07-27 21:46:04 +00:00
|
|
|
static inline bool isZeroNode(SDValue Elt) {
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
return ((isa<ConstantSDNode>(Elt) &&
|
|
|
|
cast<ConstantSDNode>(Elt)->getValue() == 0) ||
|
|
|
|
(isa<ConstantFPSDNode>(Elt) &&
|
2007-08-31 04:03:46 +00:00
|
|
|
cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-10-07 21:55:32 +00:00
|
|
|
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
|
|
|
|
/// match a load whose top elements are either undef or zeros. The load flavor
|
|
|
|
/// is derived from the type of N, which is either v4f32 or v2f64.
|
2008-07-27 21:46:04 +00:00
|
|
|
bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
|
|
|
|
SDValue N, SDValue &Base,
|
|
|
|
SDValue &Scale, SDValue &Index,
|
|
|
|
SDValue &Disp, SDValue &InChain,
|
|
|
|
SDValue &OutChain) {
|
2006-10-07 21:55:32 +00:00
|
|
|
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
InChain = N.getOperand(0).getValue(1);
|
2006-10-16 06:34:55 +00:00
|
|
|
if (ISD::isNON_EXTLoad(InChain.Val) &&
|
|
|
|
InChain.getValue(0).hasOneUse() &&
|
2006-11-10 21:23:04 +00:00
|
|
|
N.hasOneUse() &&
|
2006-11-08 20:34:28 +00:00
|
|
|
CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
|
2006-10-11 21:06:01 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(InChain);
|
2006-11-08 20:34:28 +00:00
|
|
|
if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
|
2006-10-07 21:55:32 +00:00
|
|
|
return false;
|
2006-10-11 21:06:01 +00:00
|
|
|
OutChain = LD->getChain();
|
2006-10-07 21:55:32 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
|
|
|
|
// Also handle the case where we explicitly require zeros in the top
|
2006-10-07 21:55:32 +00:00
|
|
|
// elements. This is a vector shuffle from the zero vector.
|
2008-05-09 21:53:03 +00:00
|
|
|
if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.Val->hasOneUse() &&
|
Fix a long standing deficiency in the X86 backend: we would
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44310 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-25 00:24:49 +00:00
|
|
|
// Check to see if the top elements are all zeros (or bitcast of zeros).
|
2008-05-08 00:57:18 +00:00
|
|
|
N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
|
|
|
|
N.getOperand(0).Val->hasOneUse() &&
|
|
|
|
ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).Val) &&
|
|
|
|
N.getOperand(0).getOperand(0).hasOneUse()) {
|
|
|
|
// Okay, this is a zero extending load. Fold it.
|
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
|
|
|
|
if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
|
|
|
|
return false;
|
|
|
|
OutChain = LD->getChain();
|
2008-07-27 21:46:04 +00:00
|
|
|
InChain = SDValue(LD, 1);
|
2008-05-08 00:57:18 +00:00
|
|
|
return true;
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
}
|
2006-10-07 21:55:32 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-02-25 10:09:08 +00:00
|
|
|
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
|
|
|
|
/// mode it matches can be cost effectively emitted as an LEA instruction.
|
2008-07-27 21:46:04 +00:00
|
|
|
bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
|
|
|
|
SDValue &Base, SDValue &Scale,
|
|
|
|
SDValue &Index, SDValue &Disp) {
|
2006-02-25 10:09:08 +00:00
|
|
|
X86ISelAddressMode AM;
|
|
|
|
if (MatchAddress(N, AM))
|
|
|
|
return false;
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = N.getValueType();
|
2006-02-25 10:09:08 +00:00
|
|
|
unsigned Complexity = 0;
|
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase)
|
|
|
|
if (AM.Base.Reg.Val)
|
|
|
|
Complexity = 1;
|
|
|
|
else
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.Base.Reg = CurDAG->getRegister(0, VT);
|
2006-02-25 10:09:08 +00:00
|
|
|
else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
|
|
|
|
Complexity = 4;
|
|
|
|
|
|
|
|
if (AM.IndexReg.Val)
|
|
|
|
Complexity++;
|
|
|
|
else
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(0, VT);
|
2006-02-25 10:09:08 +00:00
|
|
|
|
Two changes:
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2, #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 06:08:29 +00:00
|
|
|
// Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
|
|
|
|
// a simple shift.
|
|
|
|
if (AM.Scale > 1)
|
2006-02-28 21:13:57 +00:00
|
|
|
Complexity++;
|
2006-02-25 10:09:08 +00:00
|
|
|
|
|
|
|
// FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
|
|
|
|
// to a LEA. This is determined with some expermentation but is by no means
|
|
|
|
// optimal (especially for code size consideration). LEA is nice because of
|
|
|
|
// its three-address nature. Tweak the cost function again when we can run
|
|
|
|
// convertToThreeAddress() at register allocation time.
|
2006-09-08 06:48:29 +00:00
|
|
|
if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
|
|
|
|
// For X86-64, we should always use lea to materialize RIP relative
|
|
|
|
// addresses.
|
2006-12-05 22:03:40 +00:00
|
|
|
if (Subtarget->is64Bit())
|
2006-09-08 06:48:29 +00:00
|
|
|
Complexity = 4;
|
|
|
|
else
|
|
|
|
Complexity += 2;
|
|
|
|
}
|
2006-02-25 10:09:08 +00:00
|
|
|
|
|
|
|
if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
|
|
|
|
Complexity++;
|
|
|
|
|
|
|
|
if (Complexity > 2) {
|
|
|
|
getAddressOperands(AM, Base, Scale, Index, Disp);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
|
|
|
|
SDValue &Base, SDValue &Scale,
|
|
|
|
SDValue &Index, SDValue &Disp) {
|
2006-10-09 20:57:25 +00:00
|
|
|
if (ISD::isNON_EXTLoad(N.Val) &&
|
2006-02-06 06:02:33 +00:00
|
|
|
N.hasOneUse() &&
|
2006-10-14 08:33:25 +00:00
|
|
|
CanBeFoldedBy(N.Val, P.Val, P.Val))
|
2006-11-08 20:34:28 +00:00
|
|
|
return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
|
2006-01-06 20:36:21 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-02-18 00:15:05 +00:00
|
|
|
/// getGlobalBaseReg - Output the instructions required to put the
|
|
|
|
/// base address to use for accessing globals into a register.
|
|
|
|
///
|
2006-08-26 05:34:46 +00:00
|
|
|
SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
|
2006-09-08 06:48:29 +00:00
|
|
|
assert(!Subtarget->is64Bit() && "X86-64 PIC uses RIP relative addressing");
|
2006-02-18 00:15:05 +00:00
|
|
|
if (!GlobalBaseReg) {
|
|
|
|
// Insert the set of GlobalBaseReg into the first MBB of the function
|
2008-01-05 00:41:47 +00:00
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineBasicBlock &FirstMBB = MF->front();
|
2006-02-18 00:15:05 +00:00
|
|
|
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
|
2008-01-05 00:41:47 +00:00
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
2007-12-31 04:13:23 +00:00
|
|
|
unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
|
2007-01-12 19:20:47 +00:00
|
|
|
|
2006-11-27 23:37:22 +00:00
|
|
|
const TargetInstrInfo *TII = TM.getInstrInfo();
|
2007-12-22 02:26:46 +00:00
|
|
|
// Operand of MovePCtoStack is completely ignored by asm printer. It's
|
|
|
|
// only used in JIT code emission as displacement to pc.
|
2008-01-05 00:41:47 +00:00
|
|
|
BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0);
|
2007-01-12 19:20:47 +00:00
|
|
|
|
|
|
|
// If we're using vanilla 'GOT' PIC style, we should use relative addressing
|
|
|
|
// not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
|
2007-01-22 21:34:25 +00:00
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_ &&
|
|
|
|
Subtarget->isPICStyleGOT()) {
|
2007-12-31 04:13:23 +00:00
|
|
|
GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
|
2008-01-05 00:41:47 +00:00
|
|
|
BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg)
|
|
|
|
.addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
|
2007-01-12 19:20:47 +00:00
|
|
|
} else {
|
|
|
|
GlobalBaseReg = PC;
|
|
|
|
}
|
|
|
|
|
2006-02-18 00:15:05 +00:00
|
|
|
}
|
2006-09-08 06:48:29 +00:00
|
|
|
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
|
2006-02-18 00:15:05 +00:00
|
|
|
}
|
|
|
|
|
2006-05-20 01:36:52 +00:00
|
|
|
static SDNode *FindCallStartFromCall(SDNode *Node) {
|
|
|
|
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
|
|
|
|
assert(Node->getOperand(0).getValueType() == MVT::Other &&
|
|
|
|
"Node doesn't have a token chain argument!");
|
|
|
|
return FindCallStartFromCall(Node->getOperand(0).Val);
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDNode *X86DAGToDAGISel::getTruncate(SDValue N0, MVT VT) {
|
|
|
|
SDValue SRIdx;
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (VT.getSimpleVT()) {
|
|
|
|
default: assert(0 && "Unknown truncate!");
|
2007-08-10 21:48:46 +00:00
|
|
|
case MVT::i8:
|
|
|
|
SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
|
|
|
|
// Ensure that the source register has an 8-bit subreg on 32-bit targets
|
|
|
|
if (!Subtarget->is64Bit()) {
|
|
|
|
unsigned Opc;
|
2008-07-16 16:20:48 +00:00
|
|
|
MVT N0VT = N0.getValueType();
|
|
|
|
switch (N0VT.getSimpleVT()) {
|
2007-08-10 21:48:46 +00:00
|
|
|
default: assert(0 && "Unknown truncate!");
|
|
|
|
case MVT::i16:
|
|
|
|
Opc = X86::MOV16to16_;
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
Opc = X86::MOV32to32_;
|
|
|
|
break;
|
|
|
|
}
|
2008-07-27 21:46:04 +00:00
|
|
|
N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
|
2007-10-12 07:55:53 +00:00
|
|
|
return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
|
|
|
|
VT, N0, SRIdx, N0.getValue(1));
|
2007-08-10 21:48:46 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MVT::i16:
|
|
|
|
SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
|
|
|
|
break;
|
|
|
|
}
|
2007-10-12 07:55:53 +00:00
|
|
|
return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, VT, N0, SRIdx);
|
2007-08-10 21:48:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDNode *X86DAGToDAGISel::Select(SDValue N) {
|
2005-12-15 01:02:48 +00:00
|
|
|
SDNode *Node = N.Val;
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT NVT = Node->getValueType(0);
|
2006-01-06 20:36:21 +00:00
|
|
|
unsigned Opc, MOpc;
|
|
|
|
unsigned Opcode = Node->getOpcode();
|
2005-11-16 01:54:32 +00:00
|
|
|
|
2006-02-10 22:24:32 +00:00
|
|
|
#ifndef NDEBUG
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << std::string(Indent, ' ') << "Selecting: ";
|
2006-02-10 22:24:32 +00:00
|
|
|
DEBUG(Node->dump(CurDAG));
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << "\n";
|
2006-02-10 22:46:26 +00:00
|
|
|
Indent += 2;
|
2006-02-10 22:24:32 +00:00
|
|
|
#endif
|
|
|
|
|
2008-07-17 19:10:17 +00:00
|
|
|
if (Node->isMachineOpcode()) {
|
2006-02-10 22:24:32 +00:00
|
|
|
#ifndef NDEBUG
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << std::string(Indent-2, ' ') << "== ";
|
2006-02-10 22:24:32 +00:00
|
|
|
DEBUG(Node->dump(CurDAG));
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << "\n";
|
2006-02-10 22:46:26 +00:00
|
|
|
Indent -= 2;
|
2006-02-10 22:24:32 +00:00
|
|
|
#endif
|
2006-08-11 09:08:15 +00:00
|
|
|
return NULL; // Already selected.
|
2006-02-09 00:37:58 +00:00
|
|
|
}
|
2006-01-11 22:15:18 +00:00
|
|
|
|
2006-01-06 20:36:21 +00:00
|
|
|
switch (Opcode) {
|
2005-11-16 01:54:32 +00:00
|
|
|
default: break;
|
2006-02-23 20:41:18 +00:00
|
|
|
case X86ISD::GlobalBaseReg:
|
2006-08-26 05:34:46 +00:00
|
|
|
return getGlobalBaseReg();
|
2006-02-23 20:41:18 +00:00
|
|
|
|
2006-02-25 10:09:08 +00:00
|
|
|
case ISD::ADD: {
|
|
|
|
// Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
|
|
|
|
// code and is matched first so to prevent it from being turned into
|
|
|
|
// LEA32r X+c.
|
2008-01-08 02:06:11 +00:00
|
|
|
// In 64-bit small code size mode, use LEA to take advantage of
|
|
|
|
// RIP-relative addressing.
|
|
|
|
if (TM.getCodeModel() != CodeModel::Small)
|
|
|
|
break;
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = TLI.getPointerTy();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N0 = N.getOperand(0);
|
|
|
|
SDValue N1 = N.getOperand(1);
|
2006-09-08 06:48:29 +00:00
|
|
|
if (N.Val->getValueType(0) == PtrVT &&
|
2006-12-05 04:01:03 +00:00
|
|
|
N0.getOpcode() == X86ISD::Wrapper &&
|
2006-02-25 10:09:08 +00:00
|
|
|
N1.getOpcode() == ISD::Constant) {
|
|
|
|
unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue C(0, 0);
|
2006-02-25 10:09:08 +00:00
|
|
|
// TODO: handle ExternalSymbolSDNode.
|
|
|
|
if (GlobalAddressSDNode *G =
|
|
|
|
dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
|
2006-09-08 06:48:29 +00:00
|
|
|
C = CurDAG->getTargetGlobalAddress(G->getGlobal(), PtrVT,
|
2006-02-25 10:09:08 +00:00
|
|
|
G->getOffset() + Offset);
|
|
|
|
} else if (ConstantPoolSDNode *CP =
|
|
|
|
dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
|
2006-09-12 21:04:05 +00:00
|
|
|
C = CurDAG->getTargetConstantPool(CP->getConstVal(), PtrVT,
|
2006-02-25 10:09:08 +00:00
|
|
|
CP->getAlignment(),
|
|
|
|
CP->getOffset()+Offset);
|
|
|
|
}
|
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
if (C.Val) {
|
|
|
|
if (Subtarget->is64Bit()) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
|
2006-09-08 06:48:29 +00:00
|
|
|
CurDAG->getRegister(0, PtrVT), C };
|
|
|
|
return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4);
|
|
|
|
} else
|
|
|
|
return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, PtrVT, C);
|
|
|
|
}
|
2006-02-25 10:09:08 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Other cases are handled by auto-generated code.
|
|
|
|
break;
|
2006-02-23 02:43:52 +00:00
|
|
|
}
|
2006-02-23 20:41:18 +00:00
|
|
|
|
2007-10-08 18:33:35 +00:00
|
|
|
case ISD::SMUL_LOHI:
|
|
|
|
case ISD::UMUL_LOHI: {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
2007-10-08 18:33:35 +00:00
|
|
|
|
|
|
|
bool isSigned = Opcode == ISD::SMUL_LOHI;
|
|
|
|
if (!isSigned)
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (NVT.getSimpleVT()) {
|
2006-01-06 20:36:21 +00:00
|
|
|
default: assert(0 && "Unsupported VT!");
|
|
|
|
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
|
|
|
|
case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
|
|
|
|
case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
|
2006-01-06 20:36:21 +00:00
|
|
|
}
|
|
|
|
else
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (NVT.getSimpleVT()) {
|
2006-01-06 20:36:21 +00:00
|
|
|
default: assert(0 && "Unsupported VT!");
|
|
|
|
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
|
|
|
|
case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
|
|
|
|
case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
|
2006-01-06 20:36:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned LoReg, HiReg;
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (NVT.getSimpleVT()) {
|
2006-01-06 20:36:21 +00:00
|
|
|
default: assert(0 && "Unsupported VT!");
|
|
|
|
case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
|
|
|
|
case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
|
|
|
|
case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
|
2006-01-06 20:36:21 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3;
|
2007-08-02 05:48:35 +00:00
|
|
|
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
|
2007-10-08 18:33:35 +00:00
|
|
|
// multiplty is commmutative
|
2006-01-06 23:19:29 +00:00
|
|
|
if (!foldedLoad) {
|
2006-02-06 06:02:33 +00:00
|
|
|
foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
|
2007-08-02 05:48:35 +00:00
|
|
|
if (foldedLoad)
|
|
|
|
std::swap(N0, N1);
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
|
|
|
|
2006-08-26 01:05:16 +00:00
|
|
|
AddToISelQueue(N0);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
|
|
|
|
N0, SDValue()).getValue(1);
|
2006-01-06 20:36:21 +00:00
|
|
|
|
|
|
|
if (foldedLoad) {
|
2007-10-08 18:33:35 +00:00
|
|
|
AddToISelQueue(N1.getOperand(0));
|
2006-08-26 01:05:16 +00:00
|
|
|
AddToISelQueue(Tmp0);
|
|
|
|
AddToISelQueue(Tmp1);
|
|
|
|
AddToISelQueue(Tmp2);
|
|
|
|
AddToISelQueue(Tmp3);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
|
2006-02-09 07:17:49 +00:00
|
|
|
SDNode *CNode =
|
2006-08-27 08:14:06 +00:00
|
|
|
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
|
2008-07-27 21:46:04 +00:00
|
|
|
InFlag = SDValue(CNode, 1);
|
2007-10-08 18:33:35 +00:00
|
|
|
// Update the chain.
|
2008-07-27 21:46:04 +00:00
|
|
|
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
|
2006-01-06 20:36:21 +00:00
|
|
|
} else {
|
2006-08-26 01:05:16 +00:00
|
|
|
AddToISelQueue(N1);
|
2006-02-09 07:17:49 +00:00
|
|
|
InFlag =
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
|
2006-01-06 20:36:21 +00:00
|
|
|
}
|
|
|
|
|
2007-10-08 18:33:35 +00:00
|
|
|
// Copy the low half of the result, if it is needed.
|
|
|
|
if (!N.getValue(0).use_empty()) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
2007-10-08 18:33:35 +00:00
|
|
|
LoReg, NVT, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
|
|
|
ReplaceUses(N.getValue(0), Result);
|
|
|
|
#ifndef NDEBUG
|
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
|
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
|
|
DOUT << "\n";
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
// Copy the high half of the result, if it is needed.
|
|
|
|
if (!N.getValue(1).use_empty()) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Result;
|
2007-10-08 18:33:35 +00:00
|
|
|
if (HiReg == X86::AH && Subtarget->is64Bit()) {
|
|
|
|
// Prevent use of AH in a REX instruction by referencing AX instead.
|
|
|
|
// Shift it down 8 bits.
|
|
|
|
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
|
|
|
X86::AX, MVT::i16, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
2008-07-27 21:46:04 +00:00
|
|
|
Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
|
2007-10-08 18:33:35 +00:00
|
|
|
CurDAG->getTargetConstant(8, MVT::i8)), 0);
|
|
|
|
// Then truncate it down to i8.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
|
|
|
|
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
|
2007-10-08 18:33:35 +00:00
|
|
|
MVT::i8, Result, SRIdx), 0);
|
|
|
|
} else {
|
|
|
|
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
|
|
|
HiReg, NVT, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
|
|
|
}
|
|
|
|
ReplaceUses(N.getValue(1), Result);
|
|
|
|
#ifndef NDEBUG
|
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
|
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
|
|
DOUT << "\n";
|
|
|
|
#endif
|
2007-08-09 21:59:35 +00:00
|
|
|
}
|
2006-02-09 00:37:58 +00:00
|
|
|
|
2006-02-10 22:24:32 +00:00
|
|
|
#ifndef NDEBUG
|
2006-02-10 22:46:26 +00:00
|
|
|
Indent -= 2;
|
2006-02-10 22:24:32 +00:00
|
|
|
#endif
|
2007-10-08 18:33:35 +00:00
|
|
|
|
2006-08-11 09:08:15 +00:00
|
|
|
return NULL;
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
2006-02-18 00:15:05 +00:00
|
|
|
|
2007-10-08 18:33:35 +00:00
|
|
|
case ISD::SDIVREM:
|
|
|
|
case ISD::UDIVREM: {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
2007-10-08 18:33:35 +00:00
|
|
|
|
|
|
|
bool isSigned = Opcode == ISD::SDIVREM;
|
2006-01-06 23:19:29 +00:00
|
|
|
if (!isSigned)
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (NVT.getSimpleVT()) {
|
2006-01-06 23:19:29 +00:00
|
|
|
default: assert(0 && "Unsupported VT!");
|
|
|
|
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
|
|
|
|
case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
|
|
|
|
case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
|
|
|
else
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (NVT.getSimpleVT()) {
|
2006-01-06 23:19:29 +00:00
|
|
|
default: assert(0 && "Unsupported VT!");
|
|
|
|
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
|
|
|
|
case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
|
|
|
|
case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned LoReg, HiReg;
|
|
|
|
unsigned ClrOpcode, SExtOpcode;
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (NVT.getSimpleVT()) {
|
2006-01-06 23:19:29 +00:00
|
|
|
default: assert(0 && "Unsupported VT!");
|
|
|
|
case MVT::i8:
|
|
|
|
LoReg = X86::AL; HiReg = X86::AH;
|
2006-11-17 22:10:14 +00:00
|
|
|
ClrOpcode = 0;
|
2006-01-06 23:19:29 +00:00
|
|
|
SExtOpcode = X86::CBW;
|
|
|
|
break;
|
|
|
|
case MVT::i16:
|
|
|
|
LoReg = X86::AX; HiReg = X86::DX;
|
2006-06-02 21:20:34 +00:00
|
|
|
ClrOpcode = X86::MOV16r0;
|
2006-01-06 23:19:29 +00:00
|
|
|
SExtOpcode = X86::CWD;
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
LoReg = X86::EAX; HiReg = X86::EDX;
|
2006-06-02 21:20:34 +00:00
|
|
|
ClrOpcode = X86::MOV32r0;
|
2006-01-06 23:19:29 +00:00
|
|
|
SExtOpcode = X86::CDQ;
|
|
|
|
break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case MVT::i64:
|
|
|
|
LoReg = X86::RAX; HiReg = X86::RDX;
|
|
|
|
ClrOpcode = X86::MOV64r0;
|
|
|
|
SExtOpcode = X86::CQO;
|
|
|
|
break;
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3;
|
2007-10-08 18:33:35 +00:00
|
|
|
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue InFlag;
|
2006-11-17 22:10:14 +00:00
|
|
|
if (NVT == MVT::i8 && !isSigned) {
|
|
|
|
// Special case for div8, just use a move with zero extension to AX to
|
|
|
|
// clear the upper 8 bits (AH).
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
|
2006-11-17 22:10:14 +00:00
|
|
|
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
|
2006-11-17 22:10:14 +00:00
|
|
|
AddToISelQueue(N0.getOperand(0));
|
|
|
|
AddToISelQueue(Tmp0);
|
|
|
|
AddToISelQueue(Tmp1);
|
|
|
|
AddToISelQueue(Tmp2);
|
|
|
|
AddToISelQueue(Tmp3);
|
|
|
|
Move =
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
|
2006-11-17 22:10:14 +00:00
|
|
|
Ops, 5), 0);
|
|
|
|
Chain = Move.getValue(1);
|
|
|
|
ReplaceUses(N0.getValue(1), Chain);
|
|
|
|
} else {
|
|
|
|
AddToISelQueue(N0);
|
|
|
|
Move =
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
|
2006-11-17 22:10:14 +00:00
|
|
|
Chain = CurDAG->getEntryNode();
|
|
|
|
}
|
2008-07-27 21:46:04 +00:00
|
|
|
Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue());
|
2006-01-06 23:19:29 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
2006-11-17 22:10:14 +00:00
|
|
|
} else {
|
|
|
|
AddToISelQueue(N0);
|
|
|
|
InFlag =
|
2007-10-08 18:33:35 +00:00
|
|
|
CurDAG->getCopyToReg(CurDAG->getEntryNode(),
|
2008-07-27 21:46:04 +00:00
|
|
|
LoReg, N0, SDValue()).getValue(1);
|
2006-11-17 22:10:14 +00:00
|
|
|
if (isSigned) {
|
|
|
|
// Sign extend the low part into the high part.
|
|
|
|
InFlag =
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
|
2006-11-17 22:10:14 +00:00
|
|
|
} else {
|
|
|
|
// Zero out the high part, effectively zero extending the input.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
|
2007-10-08 18:33:35 +00:00
|
|
|
InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
|
|
|
|
ClrNode, InFlag).getValue(1);
|
2006-11-17 22:10:14 +00:00
|
|
|
}
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (foldedLoad) {
|
2006-11-17 22:10:14 +00:00
|
|
|
AddToISelQueue(N1.getOperand(0));
|
2006-08-26 01:05:16 +00:00
|
|
|
AddToISelQueue(Tmp0);
|
|
|
|
AddToISelQueue(Tmp1);
|
|
|
|
AddToISelQueue(Tmp2);
|
|
|
|
AddToISelQueue(Tmp3);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
|
2006-02-09 07:17:49 +00:00
|
|
|
SDNode *CNode =
|
2006-08-27 08:14:06 +00:00
|
|
|
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
|
2008-07-27 21:46:04 +00:00
|
|
|
InFlag = SDValue(CNode, 1);
|
2007-10-08 18:33:35 +00:00
|
|
|
// Update the chain.
|
2008-07-27 21:46:04 +00:00
|
|
|
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
|
2006-01-06 23:19:29 +00:00
|
|
|
} else {
|
2006-08-26 01:05:16 +00:00
|
|
|
AddToISelQueue(N1);
|
2006-02-09 07:17:49 +00:00
|
|
|
InFlag =
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
|
|
|
|
2007-09-25 18:23:27 +00:00
|
|
|
// Copy the division (low) result, if it is needed.
|
|
|
|
if (!N.getValue(0).use_empty()) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
2007-10-08 18:33:35 +00:00
|
|
|
LoReg, NVT, InFlag);
|
2007-09-25 18:23:27 +00:00
|
|
|
InFlag = Result.getValue(2);
|
|
|
|
ReplaceUses(N.getValue(0), Result);
|
|
|
|
#ifndef NDEBUG
|
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
|
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
|
|
DOUT << "\n";
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
// Copy the remainder (high) result, if it is needed.
|
|
|
|
if (!N.getValue(1).use_empty()) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Result;
|
2007-09-25 18:23:27 +00:00
|
|
|
if (HiReg == X86::AH && Subtarget->is64Bit()) {
|
|
|
|
// Prevent use of AH in a REX instruction by referencing AX instead.
|
|
|
|
// Shift it down 8 bits.
|
2007-10-08 18:33:35 +00:00
|
|
|
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
|
|
|
X86::AX, MVT::i16, InFlag);
|
2007-09-25 18:23:27 +00:00
|
|
|
InFlag = Result.getValue(2);
|
2008-07-27 21:46:04 +00:00
|
|
|
Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
|
2007-09-25 18:23:27 +00:00
|
|
|
CurDAG->getTargetConstant(8, MVT::i8)), 0);
|
|
|
|
// Then truncate it down to i8.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
|
|
|
|
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
|
2007-09-25 18:23:27 +00:00
|
|
|
MVT::i8, Result, SRIdx), 0);
|
|
|
|
} else {
|
2007-10-08 18:33:35 +00:00
|
|
|
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
|
|
|
HiReg, NVT, InFlag);
|
2007-09-25 18:23:27 +00:00
|
|
|
InFlag = Result.getValue(2);
|
|
|
|
}
|
|
|
|
ReplaceUses(N.getValue(1), Result);
|
|
|
|
#ifndef NDEBUG
|
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
|
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
|
|
DOUT << "\n";
|
|
|
|
#endif
|
2007-08-09 21:59:35 +00:00
|
|
|
}
|
2006-02-10 22:24:32 +00:00
|
|
|
|
|
|
|
#ifndef NDEBUG
|
2006-02-10 22:46:26 +00:00
|
|
|
Indent -= 2;
|
2006-02-10 22:24:32 +00:00
|
|
|
#endif
|
2006-08-11 09:08:15 +00:00
|
|
|
|
|
|
|
return NULL;
|
2005-12-17 02:02:50 +00:00
|
|
|
}
|
2007-08-10 22:22:41 +00:00
|
|
|
|
|
|
|
case ISD::ANY_EXTEND: {
|
2008-03-16 03:12:01 +00:00
|
|
|
// Check if the type extended to supports subregs.
|
|
|
|
if (NVT == MVT::i8)
|
|
|
|
break;
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N0 = Node->getOperand(0);
|
2008-03-16 03:12:01 +00:00
|
|
|
// Get the subregsiter index for the type to extend.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT N0VT = N0.getValueType();
|
2008-03-16 03:12:01 +00:00
|
|
|
unsigned Idx = (N0VT == MVT::i32) ? X86::SUBREG_32BIT :
|
|
|
|
(N0VT == MVT::i16) ? X86::SUBREG_16BIT :
|
|
|
|
(Subtarget->is64Bit()) ? X86::SUBREG_8BIT : 0;
|
|
|
|
|
|
|
|
// If we don't have a subreg Idx, let generated ISel have a try.
|
|
|
|
if (Idx == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
// If we have an index, generate an insert_subreg into undef.
|
2007-08-10 22:22:41 +00:00
|
|
|
AddToISelQueue(N0);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Undef =
|
|
|
|
SDValue(CurDAG->getTargetNode(X86::IMPLICIT_DEF, NVT), 0);
|
|
|
|
SDValue SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32);
|
2008-03-16 03:12:01 +00:00
|
|
|
SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG,
|
2008-04-03 07:45:18 +00:00
|
|
|
NVT, Undef, N0, SRIdx);
|
2007-08-10 22:22:41 +00:00
|
|
|
|
|
|
|
#ifndef NDEBUG
|
2008-03-16 03:12:01 +00:00
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
|
|
|
DEBUG(ResNode->dump(CurDAG));
|
|
|
|
DOUT << "\n";
|
|
|
|
Indent -= 2;
|
2007-08-10 22:22:41 +00:00
|
|
|
#endif
|
2008-03-16 03:12:01 +00:00
|
|
|
return ResNode;
|
2007-08-10 22:22:41 +00:00
|
|
|
}
|
2007-08-10 21:48:46 +00:00
|
|
|
|
|
|
|
case ISD::SIGN_EXTEND_INREG: {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N0 = Node->getOperand(0);
|
2007-08-10 21:48:46 +00:00
|
|
|
AddToISelQueue(N0);
|
2007-07-29 01:24:57 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue TruncOp = SDValue(getTruncate(N0, SVT), 0);
|
2007-11-01 08:51:44 +00:00
|
|
|
unsigned Opc = 0;
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (NVT.getSimpleVT()) {
|
|
|
|
default: assert(0 && "Unknown sign_extend_inreg!");
|
2007-07-29 01:24:57 +00:00
|
|
|
case MVT::i16:
|
2007-08-10 21:48:46 +00:00
|
|
|
if (SVT == MVT::i8) Opc = X86::MOVSX16rr8;
|
|
|
|
else assert(0 && "Unknown sign_extend_inreg!");
|
2007-07-29 01:24:57 +00:00
|
|
|
break;
|
|
|
|
case MVT::i32:
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (SVT.getSimpleVT()) {
|
|
|
|
default: assert(0 && "Unknown sign_extend_inreg!");
|
2007-08-10 21:48:46 +00:00
|
|
|
case MVT::i8: Opc = X86::MOVSX32rr8; break;
|
|
|
|
case MVT::i16: Opc = X86::MOVSX32rr16; break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (SVT.getSimpleVT()) {
|
|
|
|
default: assert(0 && "Unknown sign_extend_inreg!");
|
2007-08-10 21:48:46 +00:00
|
|
|
case MVT::i8: Opc = X86::MOVSX64rr8; break;
|
|
|
|
case MVT::i16: Opc = X86::MOVSX64rr16; break;
|
|
|
|
case MVT::i32: Opc = X86::MOVSX64rr32; break;
|
|
|
|
}
|
2007-07-29 01:24:57 +00:00
|
|
|
break;
|
|
|
|
}
|
2007-08-10 21:48:46 +00:00
|
|
|
|
|
|
|
SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
|
|
|
DEBUG(TruncOp.Val->dump(CurDAG));
|
|
|
|
DOUT << "\n";
|
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
|
|
|
DEBUG(ResNode->dump(CurDAG));
|
|
|
|
DOUT << "\n";
|
|
|
|
Indent -= 2;
|
|
|
|
#endif
|
|
|
|
return ResNode;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case ISD::TRUNCATE: {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Input = Node->getOperand(0);
|
2007-08-10 21:48:46 +00:00
|
|
|
AddToISelQueue(Node->getOperand(0));
|
|
|
|
SDNode *ResNode = getTruncate(Input, NVT);
|
|
|
|
|
2006-05-08 08:01:26 +00:00
|
|
|
#ifndef NDEBUG
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
2006-08-26 05:34:46 +00:00
|
|
|
DEBUG(ResNode->dump(CurDAG));
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << "\n";
|
2006-05-08 08:01:26 +00:00
|
|
|
Indent -= 2;
|
|
|
|
#endif
|
2007-07-29 01:24:57 +00:00
|
|
|
return ResNode;
|
2006-05-20 07:44:28 +00:00
|
|
|
break;
|
2006-05-08 08:01:26 +00:00
|
|
|
}
|
2008-06-17 02:01:22 +00:00
|
|
|
|
|
|
|
case ISD::DECLARE: {
|
|
|
|
// Handle DECLARE nodes here because the second operand may have been
|
|
|
|
// wrapped in X86ISD::Wrapper.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Chain = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
|
|
|
SDValue N2 = Node->getOperand(2);
|
2008-06-18 02:48:27 +00:00
|
|
|
if (!isa<FrameIndexSDNode>(N1))
|
|
|
|
break;
|
|
|
|
int FI = cast<FrameIndexSDNode>(N1)->getIndex();
|
|
|
|
if (N2.getOpcode() == ISD::ADD &&
|
|
|
|
N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg)
|
|
|
|
N2 = N2.getOperand(1);
|
|
|
|
if (N2.getOpcode() == X86ISD::Wrapper &&
|
2008-06-17 02:01:22 +00:00
|
|
|
isa<GlobalAddressSDNode>(N2.getOperand(0))) {
|
|
|
|
GlobalValue *GV =
|
|
|
|
cast<GlobalAddressSDNode>(N2.getOperand(0))->getGlobal();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
|
|
|
|
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
|
2008-06-17 02:01:22 +00:00
|
|
|
AddToISelQueue(Chain);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Ops[] = { Tmp1, Tmp2, Chain };
|
2008-06-17 02:01:22 +00:00
|
|
|
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
|
|
|
|
MVT::Other, Ops, 3);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
|
|
|
|
2006-08-26 05:34:46 +00:00
|
|
|
SDNode *ResNode = SelectCode(N);
|
2006-08-11 09:08:15 +00:00
|
|
|
|
2006-02-10 22:24:32 +00:00
|
|
|
#ifndef NDEBUG
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << std::string(Indent-2, ' ') << "=> ";
|
2006-08-26 05:34:46 +00:00
|
|
|
if (ResNode == NULL || ResNode == N.Val)
|
|
|
|
DEBUG(N.Val->dump(CurDAG));
|
|
|
|
else
|
|
|
|
DEBUG(ResNode->dump(CurDAG));
|
2006-11-17 07:52:03 +00:00
|
|
|
DOUT << "\n";
|
2006-02-10 22:46:26 +00:00
|
|
|
Indent -= 2;
|
2006-02-10 22:24:32 +00:00
|
|
|
#endif
|
2006-08-11 09:08:15 +00:00
|
|
|
|
|
|
|
return ResNode;
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
|
|
|
|
2006-06-08 18:03:49 +00:00
|
|
|
bool X86DAGToDAGISel::
|
2008-07-27 21:46:04 +00:00
|
|
|
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
|
|
|
|
std::vector<SDValue> &OutOps, SelectionDAG &DAG){
|
|
|
|
SDValue Op0, Op1, Op2, Op3;
|
2006-06-08 18:03:49 +00:00
|
|
|
switch (ConstraintCode) {
|
|
|
|
case 'o': // offsetable ??
|
|
|
|
case 'v': // not offsetable ??
|
|
|
|
default: return true;
|
|
|
|
case 'm': // memory
|
2006-11-08 20:34:28 +00:00
|
|
|
if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
|
2006-06-08 18:03:49 +00:00
|
|
|
return true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-08-26 01:05:16 +00:00
|
|
|
OutOps.push_back(Op0);
|
|
|
|
OutOps.push_back(Op1);
|
|
|
|
OutOps.push_back(Op2);
|
|
|
|
OutOps.push_back(Op3);
|
|
|
|
AddToISelQueue(Op0);
|
|
|
|
AddToISelQueue(Op1);
|
|
|
|
AddToISelQueue(Op2);
|
|
|
|
AddToISelQueue(Op3);
|
2006-06-08 18:03:49 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
/// createX86ISelDag - This pass converts a legalized DAG into a
|
|
|
|
/// X86-specific DAG, ready for instruction scheduling.
|
|
|
|
///
|
2006-08-29 18:28:33 +00:00
|
|
|
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
|
|
|
|
return new X86DAGToDAGISel(TM, Fast);
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|