2012-02-17 08:55:11 +00:00
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//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MIPS assembly language.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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#define DEBUG_TYPE "mips-asm-printer"
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2012-03-17 18:46:09 +00:00
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#include "Mips.h"
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2012-07-16 15:14:51 +00:00
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#include "MipsAsmPrinter.h"
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2007-06-06 07:42:06 +00:00
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#include "MipsInstrInfo.h"
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2012-07-16 15:14:51 +00:00
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#include "MipsMCInstLower.h"
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2011-07-07 23:56:50 +00:00
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#include "InstPrinter/MipsInstPrinter.h"
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2011-11-11 22:58:42 +00:00
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#include "MCTargetDesc/MipsBaseInfo.h"
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2011-11-08 22:26:47 +00:00
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Twine.h"
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2012-07-05 23:58:21 +00:00
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#include "llvm/BasicBlock.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/MachineConstantPool.h"
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2007-07-11 23:24:41 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2012-07-05 23:58:21 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/MachineInstr.h"
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2011-08-12 21:30:06 +00:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2012-07-05 23:58:21 +00:00
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#include "llvm/InlineAsm.h"
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2011-11-08 22:26:47 +00:00
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#include "llvm/Instructions.h"
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2009-08-22 20:48:53 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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2011-07-07 23:56:50 +00:00
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#include "llvm/MC/MCInst.h"
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2012-07-05 23:58:21 +00:00
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#include "llvm/MC/MCStreamer.h"
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2009-09-13 17:14:04 +00:00
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#include "llvm/MC/MCSymbol.h"
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2011-11-08 22:26:47 +00:00
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#include "llvm/Support/raw_ostream.h"
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2012-07-05 23:58:21 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2010-03-12 21:19:23 +00:00
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#include "llvm/Target/Mangler.h"
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2012-10-08 16:38:25 +00:00
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#include "llvm/DataLayout.h"
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2011-03-04 17:51:39 +00:00
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#include "llvm/Target/TargetLoweringObjectFile.h"
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2007-11-12 19:49:57 +00:00
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#include "llvm/Target/TargetOptions.h"
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2011-07-01 01:04:43 +00:00
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2007-06-06 07:42:06 +00:00
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using namespace llvm;
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2012-03-28 00:22:50 +00:00
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bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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MipsFI = MF.getInfo<MipsFunctionInfo>();
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AsmPrinter::runOnMachineFunction(MF);
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return true;
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2011-11-08 22:26:47 +00:00
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}
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2012-09-27 01:59:07 +00:00
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bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
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MCOp = MCInstLowering.LowerOperand(MO);
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return MCOp.isValid();
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}
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#include "MipsGenMCPseudoLowering.inc"
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2011-07-07 20:10:52 +00:00
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void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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if (MI->isDebugValue()) {
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2011-12-30 21:09:41 +00:00
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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2011-07-07 20:10:52 +00:00
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PrintDebugValueComment(MI, OS);
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return;
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}
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2007-06-06 07:42:06 +00:00
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2012-09-27 01:59:07 +00:00
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// Do any auto-generated pseudo lowerings.
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if (emitPseudoExpansionLowering(OutStreamer, MI))
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return;
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2012-06-13 23:25:52 +00:00
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MachineBasicBlock::const_instr_iterator I = MI;
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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MCInst TmpInst0;
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2012-09-06 02:31:34 +00:00
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MCInstLowering.Lower(I++, TmpInst0);
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2012-08-28 19:07:39 +00:00
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2012-06-13 23:25:52 +00:00
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OutStreamer.EmitInstruction(TmpInst0);
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2012-08-28 19:07:39 +00:00
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} while ((I != E) && I->isInsideBundle()); // Delay slot check
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2011-07-07 20:10:52 +00:00
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}
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2007-06-06 07:42:06 +00:00
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-08-28 05:06:17 +00:00
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//
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// Mips Asm Directives
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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2011-03-04 17:51:39 +00:00
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// -- Mask directives "(f)mask bitmask, offset"
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2007-08-28 05:06:17 +00:00
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// Tells the assembler which registers are saved and where.
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2011-03-04 17:51:39 +00:00
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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2007-08-28 05:06:17 +00:00
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// assembler knows the register 31 (RA) is saved at prologue.
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2011-03-04 17:51:39 +00:00
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// offset - the position before stack pointer subtraction indicating where
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2007-08-28 05:06:17 +00:00
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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//
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2008-02-27 06:33:05 +00:00
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// .frame $fp,48,$ra
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// .mask 0xc0000000,-8
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// addiu $sp, $sp, -48
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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2007-08-28 05:06:17 +00:00
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//
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2011-03-04 17:51:39 +00:00
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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2007-08-28 05:06:17 +00:00
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-07-11 23:24:41 +00:00
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2008-07-14 14:42:54 +00:00
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// Mask directives
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2008-07-14 14:42:54 +00:00
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2011-03-04 17:51:39 +00:00
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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2008-08-06 06:14:43 +00:00
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// registers. For CPU registers consider RA, GP and FP for saving if necessary.
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2010-04-04 04:47:45 +00:00
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void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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2008-08-06 06:14:43 +00:00
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// CPU and FPU Saved Registers Bitmasks
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2011-05-23 20:34:30 +00:00
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unsigned CPUBitmask = 0, FPUBitmask = 0;
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int CPUTopSavedRegOff, FPUTopSavedRegOff;
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2007-08-28 05:06:17 +00:00
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2008-08-06 06:14:43 +00:00
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// Set the CPU and FPU Bitmasks
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2010-01-28 06:22:43 +00:00
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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2007-08-28 05:06:17 +00:00
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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2011-05-23 20:34:30 +00:00
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// size of stack area to which FP callee-saved regs are saved.
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2012-04-20 07:30:17 +00:00
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unsigned CPURegSize = Mips::CPURegsRegClass.getSize();
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unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
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unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
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2011-05-23 20:34:30 +00:00
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bool HasAFGR64Reg = false;
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unsigned CSFPRegsSize = 0;
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unsigned i, e = CSI.size();
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// Set FPU Bitmask.
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for (i = 0; i != e; ++i) {
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2010-06-02 20:02:30 +00:00
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unsigned Reg = CSI[i].getReg();
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2012-04-20 07:30:17 +00:00
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if (Mips::CPURegsRegClass.contains(Reg))
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2011-05-23 20:34:30 +00:00
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break;
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2011-12-30 21:09:41 +00:00
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unsigned RegNum = getMipsRegisterNumbering(Reg);
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2012-04-20 07:30:17 +00:00
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if (Mips::AFGR64RegClass.contains(Reg)) {
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2011-05-23 20:34:30 +00:00
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FPUBitmask |= (3 << RegNum);
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CSFPRegsSize += AFGR64RegSize;
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HasAFGR64Reg = true;
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continue;
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}
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FPUBitmask |= (1 << RegNum);
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CSFPRegsSize += FGR32RegSize;
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}
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// Set CPU Bitmask.
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for (; i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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2011-12-30 21:09:41 +00:00
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unsigned RegNum = getMipsRegisterNumbering(Reg);
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2011-05-23 20:34:30 +00:00
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CPUBitmask |= (1 << RegNum);
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2008-08-06 06:14:43 +00:00
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}
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2007-08-28 05:06:17 +00:00
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2011-05-23 20:34:30 +00:00
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// FP Regs are saved right below where the virtual frame pointer points to.
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FPUTopSavedRegOff = FPUBitmask ?
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(HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
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2010-11-18 21:19:35 +00:00
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2011-05-23 20:34:30 +00:00
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// CPU Regs are saved below FP Regs.
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CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
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2007-08-28 05:06:17 +00:00
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2008-08-06 06:14:43 +00:00
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// Print CPUBitmask
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2010-04-04 04:47:45 +00:00
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O << "\t.mask \t"; printHex32(CPUBitmask, O);
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2011-05-23 20:34:30 +00:00
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O << ',' << CPUTopSavedRegOff << '\n';
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2008-08-06 06:14:43 +00:00
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// Print FPUBitmask
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2011-05-23 20:34:30 +00:00
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O << "\t.fmask\t"; printHex32(FPUBitmask, O);
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O << "," << FPUTopSavedRegOff << '\n';
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2007-08-28 05:06:17 +00:00
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}
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// Print a 32 bit hex number with all numbers.
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2010-04-04 04:47:45 +00:00
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void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
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2008-08-21 00:14:44 +00:00
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O << "0x";
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2011-03-04 17:51:39 +00:00
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for (int i = 7; i >= 0; i--)
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2011-11-06 20:37:06 +00:00
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O.write_hex((Value & (0xF << (i*4))) >> (i*4));
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2007-07-11 23:24:41 +00:00
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}
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2008-07-14 14:42:54 +00:00
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// Frame and Set directives
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2008-07-14 14:42:54 +00:00
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/// Frame Directive
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2010-04-04 07:05:53 +00:00
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void MipsAsmPrinter::emitFrameDirective() {
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2008-07-14 14:42:54 +00:00
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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2010-01-28 06:22:43 +00:00
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unsigned stackReg = RI.getFrameRegister(*MF);
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2008-07-14 14:42:54 +00:00
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unsigned returnReg = RI.getRARegister();
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2010-01-28 06:22:43 +00:00
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unsigned stackSize = MF->getFrameInfo()->getStackSize();
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2008-07-14 14:42:54 +00:00
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2012-02-28 07:46:26 +00:00
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if (OutStreamer.hasRawTextSupport())
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2011-11-08 22:26:47 +00:00
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OutStreamer.EmitRawText("\t.frame\t$" +
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2011-11-06 20:37:06 +00:00
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StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
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2011-07-07 23:56:50 +00:00
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"," + Twine(stackSize) + ",$" +
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2011-11-06 20:37:06 +00:00
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StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
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2008-07-14 14:42:54 +00:00
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}
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/// Emit Set directives.
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2011-03-04 17:51:39 +00:00
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const char *MipsAsmPrinter::getCurrentABIString() const {
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2010-04-04 07:05:53 +00:00
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switch (Subtarget->getTargetABI()) {
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2011-03-04 17:51:39 +00:00
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case MipsSubtarget::O32: return "abi32";
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2010-04-04 07:05:53 +00:00
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case MipsSubtarget::N32: return "abiN32";
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case MipsSubtarget::N64: return "abi64";
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case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
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2012-09-10 21:26:47 +00:00
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default: llvm_unreachable("Unknown Mips ABI");
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2008-07-14 14:42:54 +00:00
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}
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2011-03-04 17:51:39 +00:00
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}
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2008-07-14 14:42:54 +00:00
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2010-01-27 23:23:58 +00:00
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void MipsAsmPrinter::EmitFunctionEntryLabel() {
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2012-05-24 18:37:43 +00:00
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if (OutStreamer.hasRawTextSupport()) {
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if (Subtarget->inMips16Mode())
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OutStreamer.EmitRawText(StringRef("\t.set\tmips16"));
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else
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OutStreamer.EmitRawText(StringRef("\t.set\tnomips16"));
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2012-06-13 02:41:14 +00:00
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// leave out until FSF available gas has micromips changes
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// OutStreamer.EmitRawText(StringRef("\t.set\tnomicromips"));
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2011-11-08 22:26:47 +00:00
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OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
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2012-05-24 18:37:43 +00:00
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}
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2010-01-27 23:23:58 +00:00
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OutStreamer.EmitLabel(CurrentFnSym);
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}
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2010-01-28 06:22:43 +00:00
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/// EmitFunctionBodyStart - Targets can override this to emit stuff before
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/// the first basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyStart() {
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2012-03-28 00:22:50 +00:00
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MCInstLowering.Initialize(Mang, &MF->getContext());
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2010-04-04 07:05:53 +00:00
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emitFrameDirective();
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2011-03-04 17:51:39 +00:00
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2011-11-08 22:26:47 +00:00
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if (OutStreamer.hasRawTextSupport()) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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printSavedRegsBitmask(OS);
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OutStreamer.EmitRawText(OS.str());
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2012-03-28 00:22:50 +00:00
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OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
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OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
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2012-11-02 20:56:25 +00:00
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OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
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2012-05-12 00:48:43 +00:00
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}
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2010-01-28 06:22:43 +00:00
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}
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2007-06-06 07:42:06 +00:00
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2010-01-28 06:22:43 +00:00
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/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
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/// the last basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyEnd() {
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2010-01-28 01:48:52 +00:00
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// There are instruction for this macros, but they must
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|
|
// always be at the function end, and we can't emit and
|
2011-03-04 17:51:39 +00:00
|
|
|
// break with BB logic.
|
2011-11-08 22:26:47 +00:00
|
|
|
if (OutStreamer.hasRawTextSupport()) {
|
2012-11-02 20:56:25 +00:00
|
|
|
OutStreamer.EmitRawText(StringRef("\t.set\tat"));
|
2011-11-08 22:26:47 +00:00
|
|
|
OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
|
|
|
|
OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
|
|
|
|
OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
|
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2010-07-20 08:37:04 +00:00
|
|
|
/// isBlockOnlyReachableByFallthough - Return true if the basic block has
|
|
|
|
/// exactly one predecessor and the control transfer mechanism between
|
|
|
|
/// the predecessor and this block is a fall-through.
|
2011-04-15 21:51:11 +00:00
|
|
|
bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
|
|
|
|
MBB) const {
|
2010-07-20 08:37:04 +00:00
|
|
|
// The predecessor has to be immediately before this block.
|
|
|
|
const MachineBasicBlock *Pred = *MBB->pred_begin();
|
|
|
|
|
|
|
|
// If the predecessor is a switch statement, assume a jump table
|
|
|
|
// implementation, so it is not a fall through.
|
|
|
|
if (const BasicBlock *bb = Pred->getBasicBlock())
|
|
|
|
if (isa<SwitchInst>(bb->getTerminator()))
|
|
|
|
return false;
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 18:57:38 +00:00
|
|
|
// If this is a landing pad, it isn't a fall through. If it has no preds,
|
|
|
|
// then nothing falls through to it.
|
|
|
|
if (MBB->isLandingPad() || MBB->pred_empty())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If there isn't exactly one predecessor, it can't be a fall through.
|
|
|
|
MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
|
|
|
|
++PI2;
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-04-01 18:57:38 +00:00
|
|
|
if (PI2 != MBB->pred_end())
|
2012-02-28 07:46:26 +00:00
|
|
|
return false;
|
2011-04-01 18:57:38 +00:00
|
|
|
|
|
|
|
// The predecessor has to be immediately before this block.
|
|
|
|
if (!Pred->isLayoutSuccessor(MBB))
|
|
|
|
return false;
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-04-01 18:57:38 +00:00
|
|
|
// If the block is completely empty, then it definitely does fall through.
|
|
|
|
if (Pred->empty())
|
|
|
|
return true;
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-04-01 18:57:38 +00:00
|
|
|
// Otherwise, check the last instruction.
|
|
|
|
// Check if the last terminator is an unconditional branch.
|
|
|
|
MachineBasicBlock::const_iterator I = Pred->end();
|
2011-12-07 07:15:52 +00:00
|
|
|
while (I != Pred->begin() && !(--I)->isTerminator()) ;
|
2011-04-01 18:57:38 +00:00
|
|
|
|
2011-12-07 07:15:52 +00:00
|
|
|
return !I->isBarrier();
|
2010-07-20 08:37:04 +00:00
|
|
|
}
|
|
|
|
|
2008-08-02 19:42:36 +00:00
|
|
|
// Print out an operand for an inline asm expression.
|
2012-05-10 21:48:22 +00:00
|
|
|
bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
2010-04-04 05:29:35 +00:00
|
|
|
unsigned AsmVariant,const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
2008-08-02 19:42:36 +00:00
|
|
|
// Does this asm operand have a single letter operand modifier?
|
2012-05-10 21:48:22 +00:00
|
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
|
|
|
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
switch (ExtraCode[0]) {
|
2012-05-19 00:51:56 +00:00
|
|
|
default:
|
2012-06-21 17:14:46 +00:00
|
|
|
// See if this is a generic print operand
|
|
|
|
return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
|
2012-05-19 00:51:56 +00:00
|
|
|
case 'X': // hex const int
|
|
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
|
|
|
|
return false;
|
|
|
|
case 'x': // hex const int (low 16 bits)
|
|
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
|
|
|
|
return false;
|
|
|
|
case 'd': // decimal const int
|
|
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
O << MO.getImm();
|
|
|
|
return false;
|
2012-05-30 19:05:19 +00:00
|
|
|
case 'm': // decimal const int minus 1
|
|
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
O << MO.getImm() - 1;
|
|
|
|
return false;
|
2012-06-28 20:46:26 +00:00
|
|
|
case 'z': {
|
|
|
|
// $0 if zero, regular printing otherwise
|
2012-06-28 01:33:40 +00:00
|
|
|
if (MO.getType() != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
int64_t Val = MO.getImm();
|
|
|
|
if (Val)
|
|
|
|
O << Val;
|
|
|
|
else
|
|
|
|
O << "$0";
|
|
|
|
return false;
|
|
|
|
}
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
case 'D': // Second part of a double word register operand
|
|
|
|
case 'L': // Low order register of a double word register operand
|
2012-07-18 06:41:36 +00:00
|
|
|
case 'M': // High order register of a double word register operand
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
{
|
2012-07-05 23:58:21 +00:00
|
|
|
if (OpNum == 0)
|
|
|
|
return true;
|
|
|
|
const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
|
|
|
|
if (!FlagsOP.isImm())
|
|
|
|
return true;
|
|
|
|
unsigned Flags = FlagsOP.getImm();
|
|
|
|
unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
|
2012-07-06 02:44:22 +00:00
|
|
|
// Number of registers represented by this operand. We are looking
|
|
|
|
// for 2 for 32 bit mode and 1 for 64 bit mode.
|
2012-07-05 23:58:21 +00:00
|
|
|
if (NumVals != 2) {
|
2012-07-06 02:44:22 +00:00
|
|
|
if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
|
2012-07-05 23:58:21 +00:00
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
O << '$' << MipsInstPrinter::getRegisterName(Reg);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
2012-07-11 21:41:49 +00:00
|
|
|
|
|
|
|
unsigned RegOp = OpNum;
|
|
|
|
if (!Subtarget->isGP64bit()){
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
// Endianess reverses which register holds the high or low value
|
2012-07-18 06:41:36 +00:00
|
|
|
// between M and L.
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
switch(ExtraCode[0]) {
|
2012-07-18 06:41:36 +00:00
|
|
|
case 'M':
|
|
|
|
RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
break;
|
|
|
|
case 'L':
|
2012-07-18 06:41:36 +00:00
|
|
|
RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
|
|
|
|
break;
|
|
|
|
case 'D': // Always the second part
|
|
|
|
RegOp = OpNum + 1;
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
}
|
|
|
|
if (RegOp >= MI->getNumOperands())
|
|
|
|
return true;
|
|
|
|
const MachineOperand &MO = MI->getOperand(RegOp);
|
|
|
|
if (!MO.isReg())
|
|
|
|
return true;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
O << '$' << MipsInstPrinter::getRegisterName(Reg);
|
|
|
|
return false;
|
2012-07-05 23:58:21 +00:00
|
|
|
}
|
2012-05-10 21:48:22 +00:00
|
|
|
}
|
2012-07-06 02:44:22 +00:00
|
|
|
}
|
|
|
|
}
|
2008-08-02 19:42:36 +00:00
|
|
|
|
2012-05-10 21:48:22 +00:00
|
|
|
printOperand(MI, OpNum, O);
|
2008-08-02 19:42:36 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-06-21 00:40:49 +00:00
|
|
|
bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
|
|
|
unsigned OpNum, unsigned AsmVariant,
|
|
|
|
const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
|
|
|
if (ExtraCode && ExtraCode[0])
|
2012-06-28 01:33:40 +00:00
|
|
|
return true; // Unknown modifier.
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-06-21 00:40:49 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
assert(MO.isReg() && "unexpected inline asm memory operand");
|
2011-07-07 23:56:50 +00:00
|
|
|
O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
|
2012-06-28 01:33:40 +00:00
|
|
|
|
2011-06-21 00:40:49 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-04-04 04:47:45 +00:00
|
|
|
void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
|
|
|
|
raw_ostream &O) {
|
2007-06-06 07:42:06 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
2007-11-05 03:02:32 +00:00
|
|
|
bool closeP = false;
|
2009-09-01 17:27:58 +00:00
|
|
|
|
|
|
|
if (MO.getTargetFlags())
|
2009-08-27 19:57:56 +00:00
|
|
|
closeP = true;
|
2009-09-01 17:27:58 +00:00
|
|
|
|
|
|
|
switch(MO.getTargetFlags()) {
|
|
|
|
case MipsII::MO_GPREL: O << "%gp_rel("; break;
|
|
|
|
case MipsII::MO_GOT_CALL: O << "%call16("; break;
|
2011-04-01 21:41:06 +00:00
|
|
|
case MipsII::MO_GOT: O << "%got("; break;
|
|
|
|
case MipsII::MO_ABS_HI: O << "%hi("; break;
|
|
|
|
case MipsII::MO_ABS_LO: O << "%lo("; break;
|
2011-05-31 02:53:58 +00:00
|
|
|
case MipsII::MO_TLSGD: O << "%tlsgd("; break;
|
|
|
|
case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
|
|
|
|
case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
|
|
|
|
case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
|
2011-09-22 03:09:07 +00:00
|
|
|
case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
|
|
|
|
case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
|
|
|
|
case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
|
|
|
|
case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
|
|
|
|
case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2009-09-01 17:27:58 +00:00
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
switch (MO.getType()) {
|
2007-06-06 07:42:06 +00:00
|
|
|
case MachineOperand::MO_Register:
|
2011-07-07 23:56:50 +00:00
|
|
|
O << '$'
|
2011-11-06 20:37:06 +00:00
|
|
|
<< StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MachineOperand::MO_Immediate:
|
2011-05-24 21:22:21 +00:00
|
|
|
O << MO.getImm();
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
2010-03-13 21:04:28 +00:00
|
|
|
O << *MO.getMBB()->getSymbol();
|
2007-06-06 07:42:06 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
case MachineOperand::MO_GlobalAddress:
|
2010-03-12 21:19:23 +00:00
|
|
|
O << *Mang->getSymbol(MO.getGlobal());
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
|
|
|
|
2011-03-04 20:01:52 +00:00
|
|
|
case MachineOperand::MO_BlockAddress: {
|
2012-06-14 21:10:56 +00:00
|
|
|
MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
|
2011-03-04 20:01:52 +00:00
|
|
|
O << BA->getName();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
case MachineOperand::MO_ExternalSymbol:
|
2010-01-17 21:43:43 +00:00
|
|
|
O << *GetExternalSymbolSymbol(MO.getSymbolName());
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
|
|
|
|
2007-11-12 19:49:57 +00:00
|
|
|
case MachineOperand::MO_JumpTableIndex:
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
|
2010-01-16 00:21:18 +00:00
|
|
|
<< '_' << MO.getIndex();
|
2007-11-12 19:49:57 +00:00
|
|
|
break;
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix() << "CPI"
|
2007-12-30 23:10:15 +00:00
|
|
|
<< getFunctionNumber() << "_" << MO.getIndex();
|
2009-11-19 06:06:13 +00:00
|
|
|
if (MO.getOffset())
|
|
|
|
O << "+" << MO.getOffset();
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
default:
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("<unknown operand type>");
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (closeP) O << ")";
|
|
|
|
}
|
|
|
|
|
2010-04-04 04:47:45 +00:00
|
|
|
void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
|
|
|
|
raw_ostream &O) {
|
2008-08-13 07:13:40 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
2010-04-27 22:24:37 +00:00
|
|
|
if (MO.isImm())
|
2008-08-13 07:13:40 +00:00
|
|
|
O << (unsigned short int)MO.getImm();
|
2011-03-04 17:51:39 +00:00
|
|
|
else
|
2010-04-04 04:47:45 +00:00
|
|
|
printOperand(MI, opNum, O);
|
2008-08-13 07:13:40 +00:00
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
void MipsAsmPrinter::
|
2011-07-07 20:54:20 +00:00
|
|
|
printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
2011-03-04 17:51:39 +00:00
|
|
|
// Load/Store memory operands -- imm($reg)
|
|
|
|
// If PIC target the target is loaded as the
|
2007-11-05 03:02:32 +00:00
|
|
|
// pattern lw $25,%call16($28)
|
2010-04-04 04:47:45 +00:00
|
|
|
printOperand(MI, opNum+1, O);
|
2011-07-07 18:57:00 +00:00
|
|
|
O << "(";
|
|
|
|
printOperand(MI, opNum, O);
|
2007-06-06 07:42:06 +00:00
|
|
|
O << ")";
|
|
|
|
}
|
|
|
|
|
2011-07-07 20:54:20 +00:00
|
|
|
void MipsAsmPrinter::
|
|
|
|
printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
|
|
|
// when using stack locations for not load/store instructions
|
|
|
|
// print the same way as all normal 3 operand instructions.
|
|
|
|
printOperand(MI, opNum, O);
|
|
|
|
O << ", ";
|
|
|
|
printOperand(MI, opNum+1, O);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
void MipsAsmPrinter::
|
2010-04-04 04:47:45 +00:00
|
|
|
printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
|
|
|
|
const char *Modifier) {
|
2012-06-14 21:10:56 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
2011-03-04 17:51:39 +00:00
|
|
|
O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
2009-09-30 22:06:26 +00:00
|
|
|
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
|
2009-08-19 05:49:37 +00:00
|
|
|
// FIXME: Use SwitchSection.
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2008-07-14 14:42:54 +00:00
|
|
|
// Tell the assembler which ABI we are using
|
2011-11-08 22:26:47 +00:00
|
|
|
if (OutStreamer.hasRawTextSupport())
|
2011-12-19 19:52:25 +00:00
|
|
|
OutStreamer.EmitRawText("\t.section .mdebug." +
|
|
|
|
Twine(getCurrentABIString()));
|
2008-07-14 14:42:54 +00:00
|
|
|
|
|
|
|
// TODO: handle O64 ABI
|
2011-11-08 22:26:47 +00:00
|
|
|
if (OutStreamer.hasRawTextSupport()) {
|
|
|
|
if (Subtarget->isABI_EABI()) {
|
|
|
|
if (Subtarget->isGP32bit())
|
|
|
|
OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
|
|
|
|
else
|
|
|
|
OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
|
|
|
|
}
|
2010-04-05 10:17:15 +00:00
|
|
|
}
|
2008-07-14 14:42:54 +00:00
|
|
|
|
|
|
|
// return to previous section
|
2011-11-08 22:26:47 +00:00
|
|
|
if (OutStreamer.hasRawTextSupport())
|
|
|
|
OutStreamer.EmitRawText(StringRef("\t.previous"));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-07-01 01:04:43 +00:00
|
|
|
MachineLocation
|
|
|
|
MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
|
|
|
|
// Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
|
|
|
|
assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
|
|
|
|
assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
|
|
|
|
"Unexpected MachineOperand types");
|
|
|
|
return MachineLocation(MI->getOperand(0).getReg(),
|
|
|
|
MI->getOperand(1).getImm());
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
|
|
|
|
raw_ostream &OS) {
|
|
|
|
// TODO: implement
|
|
|
|
}
|
|
|
|
|
2009-06-23 23:59:40 +00:00
|
|
|
// Force static initialization.
|
2011-03-04 17:51:39 +00:00
|
|
|
extern "C" void LLVMInitializeMipsAsmPrinter() {
|
2009-07-25 06:49:55 +00:00
|
|
|
RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
|
|
|
|
RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
|
2011-09-21 03:00:58 +00:00
|
|
|
RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
|
|
|
|
RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
|
2009-07-15 20:24:03 +00:00
|
|
|
}
|