Commit Graph

4543 Commits

Author SHA1 Message Date
Rafael Espindola
b12380a76d Add a test for a recent regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240656 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 16:16:08 +00:00
Kit Barton
1ebbc68719 [PPC] Implement vmrgew and vmrgow instructions
This patch adds support for the vector merge even word and vector merge odd word
instructions introduced in POWER8.

Phabricator review: http://reviews.llvm.org/D10704


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240650 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 15:17:40 +00:00
Bruno Cardoso Lopes
39b2e22f00 [AsmPrinter] Fix crash in handleIndirectSymViaGOTPCRel
Check for symbols in MCValue before using them. Bail out early in case
they are null. This fixes PR23779.

Differential Revision: http://reviews.llvm.org/D10712

rdar://problem/21532830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240649 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 15:17:23 +00:00
Toma Tabacu
e39f000353 [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.
Summary:
In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser.
This means that we can only parse one level of inner parentheses.

In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions
(except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression().

Reviewers: dsanders, rafael

Reviewed By: dsanders, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9742

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240625 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 09:52:02 +00:00
Rafael Espindola
1e6b8f552c Don't get confused with sections whose section number is reserved.
It is perfectly possible for SHNDX to contain indexes that have the same value
as reserved st_shndx values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240544 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 14:48:54 +00:00
Zoran Jovanovic
41f28722ef [mips][microMIPS] Implement BREAK, EHB and EI instructions
http://reviews.llvm.org/D10090


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240531 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 10:32:16 +00:00
Toma Tabacu
115be6213d [mips] [IAS] Add partial support for the ULHU pseudo-instruction.
Summary:
This only adds support for ULHU of an immediate address with/without a source register.
It does not include support for ULHU of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240410 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 14:39:42 +00:00
Petar Jovanovic
7c5bf4d38a [mips64] Emit correct addend for some PC-relative relocations
So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch
fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation.

Patch by Vladimir Radosavljevic.

Differential Revision: http://reviews.llvm.org/D10565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240404 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 13:54:42 +00:00
Daniel Jasper
b7f5b8b4b2 Revert r240302 ("Bring r240130 back.").
This causes errors like:

  ld: error: blah.o: requires dynamic R_X86_64_PC32 reloc against '' which
  may overflow at runtime; recompile with -fPIC
  blah.cc:function f(): error: undefined reference to ''
  blah.o:g(): error: undefined reference to ''

I have not yet come up with an appropriate reproduction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240394 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 11:31:32 +00:00
Daniel Sanders
43fab48d42 [mips] llvm-readobj can parse .MIPS.abiflags. No need to check the bytes.
Summary:

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10538


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240392 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 10:11:36 +00:00
Elena Demikhovsky
d96e362b3f AVX-512: Added all forms of VPABS instruction
Added all intrinsics, tests for encoding, tests for intrinsics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240386 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 08:19:46 +00:00
Evgeniy Stepanov
845d1a6a17 Fix PR23914.
r226830 moved the declaration of Buf to a nested scope, resulting
in a dangling reference (in StringRef Name), and a use-after-free.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240357 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 23:36:03 +00:00
Pete Cooper
54d0bc35fe Change .thumb_set to have the same error checks as .set.
According to the documentation, .thumb_set is 'the equivalent of a .set directive'.

We didn't have equivalent behaviour in terms of all the errors we could throw, for
example, when a symbol is redefined.

This change refactors parseAssignment so that it can be used by .set and .thumb_set
and implements tests for .thumb_set for all the errors thrown by that method.

Reviewed by Rafael Espíndola.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240318 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 19:35:57 +00:00
Sanjoy Das
e0ef46e5e7 [FaultMaps] Add a parser for the __llvm__faultmaps section.
Summary:
The parser is exercised by llvm-objdump using -print-fault-maps.  As is
probably obvious, the code itself was "heavily inspired" by
http://reviews.llvm.org/D10434.

Reviewers: reames, atrick, JosephTremoulet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10491

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240304 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 18:03:02 +00:00
Rafael Espindola
afd779f72d Bring r240130 back.
Now that pr23900 is fixed, we can bring it back with no changes.

Original message:

Make all temporary symbols unnamed.

What this does is make all symbols that would otherwise start with a .L
(or L on MachO) unnamed.

Some of these symbols still show up in the symbol table, but we can just
make them unnamed.

In order to make sure we produce identical results when going thought assembly,
all .L (not just the compiler produced ones), are now unnamed.

Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to
205.57MB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 17:52:52 +00:00
Toma Tabacu
8204fb27ac [mips] [IAS] Add support for LAReg with identical source and destination register operands.
Summary: In this case, we're supposed to load the immediate in AT and then ADDu it with the source register and put it in the destination register.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9367

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240278 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 13:10:23 +00:00
Elena Demikhovsky
114489ab24 AVX-512: added VPSHUFB instruction - all SKX forms
Added intrinsics and encoding tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240277 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 13:00:42 +00:00
Toma Tabacu
d174678830 [mips] [IAS] Add support for LASym with identical source and destination register operands.
Summary:
In this case, we're supposed to load the address of the symbol in AT and then ADDu it with the source register and
put it in the destination register.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240273 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 12:08:39 +00:00
Elena Demikhovsky
4f1ddd396b AVX-512: All forms of VCOPMRESS VEXPAND instructions,
encoding tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240272 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 11:16:30 +00:00
Nico Weber
7081f6fc99 Revert 240130, it caused crashes (repro in PR23900).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240193 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-19 23:43:47 +00:00
Rafael Espindola
ec77d9ad83 Make all temporary symbols unnamed.
What this does is make all symbols that would otherwise start with a .L
(or L on MachO) unnamed.

Some of these symbols still show up in the symbol table, but we can just
make them unnamed.

In order to make sure we produce identical results when going thought assembly,
all .L (not just the compiler produced ones), are now unnamed.

Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to
205.57MB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240130 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-19 12:16:55 +00:00
Rafael Espindola
28b186f3cc Improve the --expand-relocs handling of MachO.
In a relocation target can take 3 basic forms

* A r_value in scattered relocations.
* A symbol in external relocations.
* A section is non-external relocations.

Have the dump reflect that. With this change we go from

CHECK-NEXT:       Extern: 0
CHECK-NEXT:       Type: X86_64_RELOC_SUBTRACTOR (5)
CHECK-NEXT:       Symbol: 0x2
CHECK-NEXT:       Scattered: 0

To just

// CHECK-NEXT:       Type: X86_64_RELOC_SUBTRACTOR (5)
// CHECK-NEXT:       Section: __data (2)

Since the relocation is with a section, we print the seciton name and don't
need to say that it is not scattered or external.

Someone motivated can add further special cases for things like
ARM64_RELOC_ADDEND and ARM_RELOC_PAIR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240073 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 22:38:20 +00:00
Rafael Espindola
50cef0052f Pass --expand-relocs to a few more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240069 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 22:12:47 +00:00
James Y Knight
d280420ee9 [SPARC] Repair GOT references to internal symbols.
They had been getting emitted as a section + offset reference, which
is bogus since the value needs to be the offset within the GOT, not
the actual address of the symbol's object.

Differential Revision: http://reviews.llvm.org/D10441

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240020 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 15:05:15 +00:00
Rafael Espindola
f314160e32 Convert a few tests to use llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240017 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 13:39:07 +00:00
Asaf Badouh
bc5667c7ac [AVX512]
add instructions: VPAVGB and VPAVGW


review
http://reviews.llvm.org/D10504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240012 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 12:30:53 +00:00
Elena Demikhovsky
6c24289bef AVX-512: (fixed) Added encoding of all forms of VPERMT2W/D/Q/PS/PD and VPERMI2W/D/Q/PS/PD.
Intrinsics and tests for them are comming in the next patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240003 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 08:56:19 +00:00
Elena Demikhovsky
f3d6e24ca4 reverted 239999 due to test failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240001 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 08:06:49 +00:00
Elena Demikhovsky
5686493ccc AVX-512: Added encoding of all forms of VPERMT2W/D/Q/PS/PD
and VPERMI2W/D/Q/PS/PD.
Intrinsics and tests for them are comming in the next patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239999 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 07:29:40 +00:00
Benjamin Kramer
4bf8188289 [MC/Dwarf] Encode DW_CFA_advance_loc in target endianess.
This matches GNU as output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239911 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 15:14:35 +00:00
Toma Tabacu
d510c1085a [mips] [IAS] Add support for expanding LASym with a source register operand.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9348

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239910 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 14:31:51 +00:00
Toma Tabacu
279a212ca2 [mips] [IAS] Add support for the B{L,G}{T,E}(U) branch pseudo-instructions.
Summary:
This does not include support for the immediate variants of these pseudo-instructions.
Fixes llvm.org/PR20968.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D8537

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239905 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 13:20:24 +00:00
Toma Tabacu
87f93f5387 [mips] [IAS] Fix LA with relative label operands.
Summary:
Call MCSymbolRefExpr::create() with a MCSymbol* argument, not with a StringRef
of the Symbol's name, in order to avoid creating invalid temporary symbols for
relative labels (e.g. {$,.L}tmp00, {$,.L}tmp10 etc.).

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10498

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239901 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 12:30:37 +00:00
Toma Tabacu
d3b8136e1d [mips] [IAS] Add test for SW with relative label operands. NFC.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10497

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239899 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 11:46:37 +00:00
Toma Tabacu
e7684db38f [mips] [IAS] Fix LW with relative label operands.
Summary:
Previously, MCSymbolRefExpr::create() was called with a StringRef of the symbol
name, which it would then search for in the Symbols StringMap (from MCContext).

However, relative labels (which are temporary symbols) are apparently not stored
in the Symbols StringMap, so we end up creating a new {$,.L}tmp symbol
({$,.L}tmp00, {$,.L}tmp10 etc.) each time we create an MCSymbolRefExpr by
passing in the symbol name as a StringRef.

Fortunately, there is a version of MCSymbolRefExpr::create() which takes an
MCSymbol* and we already have an MCSymbol* at that point, so we can just pass
that in instead of the StringRef.

I also removed the local StringRef calls to MCSymbolRefExpr::create() from
expandMemInst(), as those cases can be handled by evaluateRelocExpr() anyway.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9938

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239897 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 10:43:45 +00:00
Kit Barton
1b26bfbef1 Properly handle the mftb instruction.
The mftb instruction was incorrectly marked as deprecated in the PPC
Backend. Instead, it should not be treated as deprecated, but rather be
implemented using the mfspr instruction. A similar patch was put into GCC last
year. Details can be found at:

https://sourceware.org/ml/binutils/2014-11/msg00383.html.
This change will replace instances of the mftb instruction with the mfspr
instruction for all CPUs except 601 and pwr3. This will also be the default
behaviour.

Additional details can be found in:

https://llvm.org/bugs/show_bug.cgi?id=23680

Phabricator review: http://reviews.llvm.org/D10419


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239827 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 16:01:15 +00:00
Daniel Sanders
b17a563e9a [mips][ias] Expand on r238751 to cover as many relocs as possible.
Summary:
Relocs that can be converted from absolute to PC-relative now do so if IsPCRel
is true. Relocs that require PC-relative now call llvm_unreachable() if IsPCRel
is false and similarly those that require absolute assert that IsPCRel is false.

Note that while it looks like some relocs (e.g. R_MIPS_26) can be converted into
the MIPS32r6/MIPS64r6 relocs (R_MIPS_PC*_S2), it isn't actually valid to do so.

Placeholders have been left in the testcase for unsupported relocs and relocs
that cannot be generated at the moment.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits, rafael

Differential Revision: http://reviews.llvm.org/D10184

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 13:46:26 +00:00
Daniel Sanders
a8cc053519 [llvm-mc] The object form of the GNU triple should be the same as the string form.
Summary:
GetTarget() may modify TripleName without also updating TheTriple.
This can lead to situations where the MCObjectStreamer has a different triple
to the rest of LLVM.

This inconsistency caused sparc-little-endian.s to pass on Windows because most
of LLVM had sparcel-pc-win32 while MCObjectStreamer had "". I believe the same
kind of thing was also true of Darwin.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: llvm-commits, rengolin, rafael

Differential Revision: http://reviews.llvm.org/D10450

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239808 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 09:57:38 +00:00
Michael Kuperstein
3dd555171e Add support for parsing the XOR operator in Intel syntax inline assembly.
Differential Revision: http://reviews.llvm.org/D10385
Patch by marina.yatsina@intel.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 12:59:45 +00:00
Igor Breger
6ea3ad7e6e AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D10430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239694 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 12:44:55 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00
Tom Stellard
f28da43112 R600/SI: Add assembler support for FLAT instructions
- Add glc, slc, and tfe operands to flat instructions
- Add missing flat instructions
- Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 20:47:06 +00:00
Toma Tabacu
f24e4e46cd Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
Apparently, Arcanist didn't include some of my local changes in my previous
commit attempt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239523 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 10:36:10 +00:00
Zoran Jovanovic
9d115effdf [mips][microMIPS] Implement ERET and ERETNC instructions
http://reviews.llvm.org/D10091


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239522 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 10:22:46 +00:00
Zoran Jovanovic
d09e8beec3 [mips] Change existing uimm10 operand to restrict the accepted immediates
http://reviews.llvm.org/D10312


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 09:51:58 +00:00
Zoran Jovanovic
938cba6ae3 [mips][microMIPSr6] Change disassembler tests to one line format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239519 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 09:42:10 +00:00
Nemanja Ivanovic
f7d6501d1d LLVM support for vector quad bit permute and gather instructions through builtins
This patch corresponds to review:
http://reviews.llvm.org/D10096

This is the back end portion of the patch related to D10095.
The patch adds the instructions and back end intrinsics for:
vbpermq
vgbbd


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239505 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 06:21:25 +00:00
Colin LeMahieu
c196bfecd6 [Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239477 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 16:52:32 +00:00
Toma Tabacu
c154887856 Recommit "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).
Specified the llvm namespace for the 2 calls to make_unique() which caused
compilation errors in Visual Studio 2013.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239405 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-09 13:33:26 +00:00
Elena Demikhovsky
22debdcab6 X86-MPX: Implemented encoding for MPX instructions.
Added encoding tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239403 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-09 13:02:10 +00:00
Toma Tabacu
695a997ef2 Revert "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
It was breaking buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239397 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-09 10:43:49 +00:00
Toma Tabacu
dc2af2605f [mips] [IAS] Add support for BNE and BEQ with an immediate operand.
Summary:
For some branches, GAS accepts an immediate instead of the 2nd register operand.
We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D9666

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239396 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-09 10:34:31 +00:00
Ranjeet Singh
1666977cd0 [AArch64] AsmParser should be case insensitive about accepting vector register names.
Differential Revision: http://reviews.llvm.org/D10320


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239353 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-08 21:32:16 +00:00
Rafael Espindola
279ef837e8 Fix a regression in .pop_section.
It was calling ChangeSection with the wrong current section, eventually leading
to a crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239335 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-08 20:08:55 +00:00
Javed Absar
d48ce2c34f ARM]: Add support for MMFR4_EL1 in assembler
This patch adds support for system register MMFR4_EL1 (memory model feature register) in the assembler.
This register provides information about the implemented memory model and memory management support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-08 15:01:11 +00:00
Igor Breger
17e24879cb AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL
Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.

Differential Revision: http://reviews.llvm.org/D10310

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239300 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-08 14:03:17 +00:00
Colin LeMahieu
8cc8dbc062 [objdump] Moving PrintImmHex out of MachODump and in to llvm-objdump and setting instprinter appropriately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239265 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-07 21:07:17 +00:00
Colin LeMahieu
4514db2bfb Teaching llvm-mc how to understand the defsym command line option. This allows integer-constant symbols to be defined on the command line and used during assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239240 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-07 01:46:24 +00:00
Colin LeMahieu
2ca8f0f5d6 [MC] Common symbols weren't being checked for redeclaration which allowed an assembly file to generate an assertion in setCommon(): !isCommon(). This change allows redeclaration as long as the size and alignment match exactly, otherwise report a fatal error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239227 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-06 20:12:40 +00:00
Rafael Espindola
dcb11d3206 Handle 16 bit PC relative relocations.
Fixes pr23771.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239214 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-06 02:29:56 +00:00
Colin LeMahieu
750b351b76 [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239161 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-05 16:00:11 +00:00
John Brawn
272d7fdf42 [ARM] Add support for -sp- FPUs and FPU none to TargetParser
These are added mainly for the benefit of clang, but this also means that they
are now allowed in .fpu directives and we emit the correct .fpu directive when
single-precision-only is used.

Differential Revision: http://reviews.llvm.org/D10238


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239151 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-05 13:31:19 +00:00
Toma Tabacu
dbaee6dadd Revert "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).
This is breaking the Windows buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239145 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-05 12:19:27 +00:00
Toma Tabacu
b349e0f1f1 [mips] [IAS] Restore STI.FeatureBits in .set pop.
Summary:
Only restoring AvailableFeatures is not enough and will lead to buggy behaviour.
For example, if we have a feature enabled and we ".set pop", the next time we try
to ".set" that feature nothing will happen because the "!(STI.getFeatureBits()[Feature])"
check will be false, because we didn't restore STI.FeatureBits.

In order to fix this, we need to make MipsAssemblerOptions remember the STI.FeatureBits
instead of the AvailableFeatures and then regenerate AvailableFeatures each time we ".set pop".
This is because, AFAIK, there is no way to convert from AvailableFeatures back to STI.FeatureBits,
but the reverse is possible by using ComputeAvailableFeatures(STI.FeatureBits).

I also moved the updating of AssemblerOptions inside the "if" statement in
setFeatureBits() and clearFeatureBits(), as there is no reason to update if
nothing changes.

Reviewers: dsanders, mkuper

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239144 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-05 11:48:54 +00:00
Jim Grosbach
aa48bf4e1c MC: Remove obsolete MachO UseAggressiveSymbolFolding.
Fix the FIXME and remove this old as(1) compat option. It was useful for
bringup of the integrated assembler to diff object files, but now it's
just causing more relocations than strictly necessary to be generated.

rdar://21201804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239084 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 20:27:42 +00:00
Rafael Espindola
9f299abc05 Omit unused section symbols from the symbol table.
Section symbols exist as an optimization: instead of having multiple relocations
point to different symbols, many of them can point to a single section symbol.

When that optimization is unused, a section symbol is also unused and adds no
extra information to the object file.

This saves a bit of space on the object files and makes the output of
llvm-objdump -t easier to read and consequently some tests get quite a bit
simpler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239045 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 15:33:30 +00:00
Rafael Espindola
0f898d59f8 No need to check the raw relocation bytes if checking the parsed dump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239042 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 15:21:17 +00:00
Rafael Espindola
523b2cdb29 llvm-readobj can parse relocations, no need to check the raw bytes.x
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239041 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 15:15:12 +00:00
Igor Breger
7c290adeb4 Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239019 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 07:23:38 +00:00
Elena Demikhovsky
1bbb64b206 AVX-512: added all SKX forms of VPERMW/D/Q instructions.
Added all forms of VPERMPS/PD instrcuctions.
Added encoding tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239016 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 07:07:13 +00:00
Rafael Espindola
79fa3fc84a Add testcase that would crash before the previous revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239011 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 05:51:13 +00:00
Asaf Badouh
ce375dc63a re-apply 238809
AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
CR:
http://reviews.llvm.org/D9991


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238923 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 13:41:48 +00:00
Elena Demikhovsky
23dc4bbf1d AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions for SKX and KNL.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238917 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 10:56:40 +00:00
Rafael Espindola
201a551929 Fix the interpretation of a 0 st_name.
The ELF spec is very clear:

-----------------------------------------------------------------------------
If the value is non-zero, it represents a string table index that gives the
symbol name. Otherwise, the symbol table entry has no name.
--------------------------------------------------------------------------

In particular, a st_name of 0 most certainly doesn't mean that the symbol has
the same name as the section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238899 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 05:14:22 +00:00
Tim Northover
33d75a269c AArch64: fix typo in SMIN far atomics and add tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238858 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 18:37:20 +00:00
Elena Demikhovsky
6628cb50bd AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238834 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 14:12:54 +00:00
Vladimir Sukharev
1e7e9b1881 [AArch64] Add v8.1a atomic instructions
Patch by: Tom Coxon

Reviewers: t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8501


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238818 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:58:41 +00:00
Toma Tabacu
01cf1d3ef3 [mips] [IAS] Reformat mips-expansions.s. NFC.
Summary:
Make mips-expansions.s more readable by grouping the instructions with their respective CHECK's.
This test is going to get a lot bigger soon and it will become essentially unreadable if the current formatting is kept.

I've also made the comments more useful and accurate, and I've restricted the RUN lines to under 80 columns.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10089

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:34:10 +00:00
Daniel Sanders
fa82cb6244 [mips] Test both %dtprel_hi and %dtprel_lo instead of testing %dtprel_hi twice.
The second %dtprel_hi is used on an addiu so it looks like a copy/paste error.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238815 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:09:08 +00:00
Daniel Sanders
ad601b6b90 [mips] Expand tabs in test/MC/Mips/mips-relocations.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238814 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:02:00 +00:00
Toma Tabacu
a5f14070fa [mips] [IAS] Add support for the .set softfloat/hardfloat directives.
Summary: These directives are used to set the current value of the SoftFloat feature.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D9074

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 09:48:04 +00:00
Elena Demikhovsky
d929045eb5 AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL
Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238811 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 08:28:57 +00:00
Asaf Badouh
aa9e1c528b revert 238809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238810 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 07:45:19 +00:00
Asaf Badouh
82fa06895e AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238809 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 07:18:14 +00:00
Rafael Espindola
872808e946 Fix relocation selection for foo-. on mips.
This handles only the 32 bit case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238751 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 15:10:51 +00:00
Asaf Badouh
b06d15c70f First commit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238745 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 13:56:00 +00:00
Elena Demikhovsky
af0e519127 AVX-512: Implemented VRANGEPD and VRANGEPD instructions for SKX.
Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238738 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 11:05:34 +00:00
Elena Demikhovsky
8e12b59b13 AVX-512: added all forms of VPSHUFD and VPSHUFHW, VPSHUFLW
including encodings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238729 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 07:17:23 +00:00
Elena Demikhovsky
9029910d9f AVX-512: Implemented VFIXUPIMMPD and VFIXUPIMMPS instructions for KNL and SKX
Implemented DAG lowering for all these forms.
Added tests for encoding.

by Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238728 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 06:50:49 +00:00
Nemanja Ivanovic
8493722975 Add support for VSX FMA single-precision instructions to the PPC back end
This patch corresponds to review:
http://reviews.llvm.org/D9941

It adds the various FMA instructions introduced in the version 2.07 of
the ISA along with the testing for them. These are operations on single
precision scalar values in VSX registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238578 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29 17:13:25 +00:00
Colin LeMahieu
0ace3c01f7 [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238556 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29 14:44:13 +00:00
Ahmed Bougacha
d4b59dcdba [TableGen][AsmMatcherEmitter] Only parse isolated tokens as registers.
Fixes PR23455, where, when TableGen generates the matcher from the
AsmString, it splits "cmp${cc}ss" into tokens, and the "ss" suffix
is recognized as the SS register.

I can't think of a situation where that's a feature, not a bug, hence:
when a token is "isolated", i.e., it is followed and preceded by
separators, it shouldn't be parsed as a register.

Differential Revision: http://reviews.llvm.org/D9844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238536 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29 01:03:37 +00:00
Rafael Espindola
fb48de619e Don't special case undefined symbol when deciding the symbol order.
ELF has no restrictions on where undefined symbols go relative to other defined
symbols. In fact, gas just sorts them together. Do the same.

This was there since r111174 probably just because the MachO writer has it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238513 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-28 21:59:34 +00:00
Andy Ayers
588f5f0cbb Revise test to run llc and llvm-mc separately.
Differential Revision: http://reviews.llvm.org/D10066

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238508 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-28 21:49:50 +00:00
Kai Nacke
95fa1db8f5 [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.
Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor.
E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to introduce a new deconding namespace to avoid a decoding conflict.

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D10083


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238439 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-28 16:23:16 +00:00
Rafael Espindola
c4e38f605e Don't create an unused _GLOBAL_OFFSET_TABLE_.
This was a bug for bug compatibility with gas that is completely unnecessary.
If a _GLOBAL_OFFSET_TABLE_ symbol is used, it will already be created by
the time we get to the ELF writer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238432 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-28 15:20:00 +00:00
Renato Golin
a052a77187 ARMTargetParser: Normalising build attributes
Now that most of the methods in Clang and LLVM that were parsing arch/cpu/fpu
strings are using ARMTargetParser, it's time to make it a bit more conforming
with what the ABI says.

This commit adds some clarification on what build attributes are accepted and
which are "non-standard". It also makes clear that the "defaultCPU" and
"defaultArch" methods were really just build attribute getters.

It also diverges from GCC's behaviour to say that armv2/armv3 are really an
ARMv4 in the build attributes, when the ABI has a clear state for that: Pre-v4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238344 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 18:15:37 +00:00
Zoran Jovanovic
dbab00a2d4 [mips][microMIPSr6] Implement SEB and SEH instructions
Differential Revision: http://reviews.llvm.org/D9739


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238333 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 15:39:47 +00:00
Jozef Kolek
b8124ac882 [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D10031


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238325 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 14:19:22 +00:00
Elena Demikhovsky
078088b790 AVX-512: Implemented all forms of sign-extend and zero-extend instructions for KNL and SKX
Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238301 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 08:15:19 +00:00