6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-02 02:55:35 +00:00
Code Issues Projects Releases Wiki Activity
18,928 Commits 39 Branches 0 Tags 277 MiB
00812e2095
Commit Graph

3843 Commits

Author SHA1 Message Date
Chris Lattner
0bdc6f1fd4 Turn PPC64 and VMX into classes that can be added to instructions instead of 
bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:32:54 +00:00
Nate Begeman
1cbf3abbb8 Next round of PPC CR optimizations. For the following code: 
int %bar(float %a, float %b, float %c, float %d) {
entry:
    %tmp.1 = setlt float %a, %d
    %tmp.2 = setlt float %b, %d
    %or = or bool %tmp.1, %tmp.2
    %tmp.3 = setgt float %c, %d
    %tmp.4 = or bool %or, %tmp.3
    %tmp.5 = and bool %tmp.4, true
    %retval = cast bool %tmp.5 to int
    ret int %retval
}

We now emit:

_bar:
.LBB_bar_0:     ; entry
        fcmpu cr0, f1, f4
        fcmpu cr1, f2, f4
        cror 0, 0, 4
        fcmpu cr1, f3, f4
        cror 28, 0, 5
        mfcr r2
        rlwinm r3, r2, 29, 31, 31
        blr

Instead of:

_bar:
.LBB_bar_0:     ; entry
        fcmpu cr7, f1, f4
        mfcr r2
        rlwinm r2, r2, 29, 31, 31
        fcmpu cr7, f2, f4
        mfcr r3
        rlwinm r3, r3, 29, 31, 31
        or r2, r2, r3
        fcmpu cr7, f3, f4
        mfcr r3
        rlwinm r3, r3, 30, 31, 31
        or r3, r2, r3
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21321 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-18 07:48:09 +00:00
Nate Begeman
16ac709c63 Change codegen for setcc to read the bit directly out of the condition 
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-18 02:43:24 +00:00
Chris Lattner
477d1de9b2 Handle ExternalSymbol operands in the PPC JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21312 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-18 00:46:10 +00:00
Nate Begeman
f8b02949e3 Make pattern isel default for ppc 
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-15 22:12:16 +00:00
Andrew Lenharth
1e0d9bda62 fix calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21303 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 17:34:20 +00:00
Andrew Lenharth
3ae1829fe5 a 21264 fix, and fix the operator precidence on an and -> zap check (should fix hundreds of test cases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21302 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 16:24:00 +00:00
Duraid Madina
1ce0c015ad print negative 64 bit immediates as negative numbers, makes things a little 
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21300 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 10:08:01 +00:00
Duraid Madina
3eb7150c3e oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21299 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 10:06:35 +00:00
Nate Begeman
7bfba7d5e3 Implement multi-way branches through logical ops on condition registers. 
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21298 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 09:45:08 +00:00
Duraid Madina
c4ccc2db6b we have zextloads, not sextloads! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21296 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 08:37:32 +00:00
Nate Begeman
ef7288c824 Add the necessary support to codegen condition register logical ops with 
register allocated condition registers.  Make sure that the printed
  output is gas compatible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 03:20:38 +00:00
Nate Begeman
1b7f7fbf95 Start allocating condition registers. Almost all explicit uses of CR0 are 
now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21294 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 23:15:44 +00:00
Nate Begeman
3664ceffdd Implement the fold shift X, zext(Y) -> shift X, Y at the target level, 
where it is safe to do so.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21293 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 22:14:14 +00:00
Nate Begeman
eea805e74c Disbale the broken fold of shift + sz[ext] for now 
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21291 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 21:23:31 +00:00
Andrew Lenharth
c24b537399 WOW, function calls still seem to work after this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21286 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 17:17:28 +00:00
Andrew Lenharth
556c44e116 prepare for func call optimization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21285 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 16:19:50 +00:00
Duraid Madina
ed09502a0b * add the shladd instruction 
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21282 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 06:12:04 +00:00
Andrew Lenharth
4f7cba5af8 add matches for SxADDL and company, as well as simplify the SxADDQ code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21281 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 05:19:55 +00:00
Duraid Madina
c02780eed1 * if ANDing with a constant of the form: 
0x00000..00FFF..FF
      ^      ^
      ^      ^
    any number of
    0's followed by
    some number of
    1's

    then we use dep.z to just paste zeros over the input. For the special
    cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
    because we're all about readability!!!
    that's what it's about!! readability!

  *twitch* ;D


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21279 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 04:50:54 +00:00
Andrew Lenharth
483f22d817 added all flavors of zap for anding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21276 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 03:47:03 +00:00
Chris Lattner
5bf2686a1b Fix some mysteriously missing {}'s which cause the miscompilation of 
Olden/mst, Ptrdist/bc, Obsequi, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21274 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 03:29:53 +00:00
Chris Lattner
519f40ba4e remove one more occurance of this that snuck in 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21271 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 02:46:17 +00:00
Chris Lattner
2942e9c301 Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff 
like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21270 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 02:43:40 +00:00
Chris Lattner
6ac614a4f2 Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing 
things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21269 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 02:41:52 +00:00
Chris Lattner
c951d87fe9 Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit 
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21268 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 02:40:26 +00:00
Chris Lattner
91302a10ae Z_E_I is gone 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21267 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 02:39:05 +00:00
Nate Begeman
b882752bd0 Fold shift by size larger than type size to undef 
Make llvm undef values generate ISD::UNDEF nodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21261 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 23:12:17 +00:00
Nate Begeman
9765c25eb7 Implement setcc op, -1 sequences 
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21260 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 21:22:28 +00:00
Duraid Madina
e8fd25f5c5 * OK, after changing to use liveIn/liveOut instead of IDEFs, 
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21252 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 18:42:59 +00:00
Andrew Lenharth
0b04b5d562 Get rid of idefs for arguments (oops) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21251 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 17:47:57 +00:00
Andrew Lenharth
e1c5a00e8b Get rid of idefs for arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21250 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 17:35:16 +00:00
Chris Lattner
9c24ba642e Put out* into the allocation order, allowing the register allocator to 
coallesce moves into outgoing args.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21249 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 15:12:51 +00:00
Chris Lattner
ea6f770fb0 Make sure to realize that calls use their argument regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21248 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 15:12:19 +00:00
Duraid Madina
ca494fddcd stop emitting IDEFs for args - change to using liveIn/liveOut 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21247 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 14:54:44 +00:00
Nate Begeman
7af0248af4 Initial support for allocation condition registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 07:04:16 +00:00
Nate Begeman
9f833d3085 Implement bitfield clears 
Implement divide by negative power of two


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21240 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 00:10:02 +00:00
Nate Begeman
ef9531efed Update PPC readme. Remove things that are done or aren't ppc specific 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21232 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 20:48:57 +00:00
Chris Lattner
30e82431b3 IA64 supports this operation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21228 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 18:55:36 +00:00
Chris Lattner
5eef9f3bc9 ORo sets CR0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21227 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:03:48 +00:00
Chris Lattner
6b4ea2cfa2 Revert the previous patch, which I didn't mean to check in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:03:41 +00:00
Chris Lattner
26d4fdb968 Fix a minor bug (ORo didn't mark that it set CR0). 
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:01:39 +00:00
Duraid Madina
21478e55db hmm, should probably change addImm() to take 64-bit arguments one day anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21224 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 07:16:39 +00:00
Nate Begeman
c7bd4827cd Add recording variants of ISD::AND and ISD::OR. This kills almost 1000 
(1.5%) instructions in 186.crafty


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21222 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 06:34:10 +00:00
Duraid Madina
5ef2ec9929 assorted fixes: 
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21221 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 05:55:56 +00:00
Nate Begeman
709c806a1e Fix another fixme: factor out the constant fp generation code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21207 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-10 06:06:10 +00:00
Nate Begeman
c5b1cd22b5 Fix 64 bit argument loading that straddles the args in regs / args on stack 
boundary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21206 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-10 05:53:14 +00:00
Nate Begeman
340f290783 Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not 
have to inform the register allocator it might be stepped on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21202 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-10 03:59:42 +00:00
Nate Begeman
27499e3f1b Make sure that BRCOND branches can be converted into long branches too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21198 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-10 01:48:29 +00:00
Nate Begeman
a0e3e9474f Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21197 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-10 01:14:13 +00:00
Chris Lattner
51d2ed976f rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more 
correct.  Remove the EmitComparison retvalue, as it is always the first arg.

Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty.  Crafty now works!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21195 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-10 01:03:31 +00:00
Nate Begeman
706471e291 fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21193 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 23:35:05 +00:00
Chris Lattner
9184bfbbf4 Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap. 
This caused the "use before a def" assertion on some programs.

With this patch, 254.gap now passes with the PPC backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21191 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 22:05:17 +00:00
Chris Lattner
91277ea45c do not set the root to null if an argument is dead 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21188 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 21:23:24 +00:00
Nate Begeman
cd08e4cb7e Add rlwnm instruction for variable rotate 
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21187 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 20:09:12 +00:00
Chris Lattner
27ee3a332d Fix a crash on 173.applu by asking for a constant bigger than 32-bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21185 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 19:47:21 +00:00
Chris Lattner
f429a3e0f6 Switch this instruction selector over to using liveins and liveouts, eliminating 
implicit defs on entry to the function.  yaay :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21184 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 16:32:30 +00:00
Chris Lattner
4c52f0ec8c Use live out sets for return values instead of imp_defs, which is cleaner and faster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21181 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 15:23:56 +00:00
Duraid Madina
e00e5ded51 ok, the "ia64 has a boatload of registers" joke stopped being funny today ;) 
* fix overallocation of integer (stacked) registers: we can't allocate
  registers for local use if they are required as output registers

this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21178 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 11:53:00 +00:00
Nate Begeman
af4ab1b103 Optimize FSEL a bit for fneg arguments. This fixes the recently added test 
case so that we emit

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fsel f1, f1, f3, f2
        blr

instead of:

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fneg f0, f1
        fneg f0, f0
        fsel f1, f0, f3, f2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21177 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 09:33:07 +00:00
Chris Lattner
67ac5f459e Fix CodeGen/SparcV9/2005-05-09-GEP-Crash.ll a crash on some specfp program 
lets hope this doesn't break other programs with induced entropy


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21174 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 06:27:14 +00:00
Chris Lattner
da4d4694a8 This target does not support/want ISD::BRCONDTWOWAY 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21164 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 03:22:37 +00:00
Chris Lattner
644db4ec5f This target does not yet support ISD::BRCONDTWOWAY 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21163 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 03:22:30 +00:00
Nate Begeman
e88aa5b4d1 64b: Expand S/UREM 
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
     Pattern match fsub a, mul(b, c) as fnmsub
     Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21161 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 03:05:51 +00:00
Nate Begeman
a9532d5dde Fix 64b shifts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21159 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-08 23:45:01 +00:00
Nate Begeman
f3f2d6d378 Match Mac OS X 64 bit calling conventions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21157 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-08 21:26:05 +00:00
Andrew Lenharth
a32b9e31c6 collect a few statistics, factor constants (constant loading and mult), fix logic operation pattern matchs, supress FP div when int dividing by a constant 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21156 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-08 17:28:49 +00:00
Duraid Madina
6dcceb5ecb fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn) 
fix hack in division (clean up frcpa instruction)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21153 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-08 10:01:48 +00:00
Nate Begeman
7e7fadd2ea Optimized code sequences for setcc reg, 0 
Optimized code sequence for (a < 0) ? b : 0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21150 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 20:30:01 +00:00
Andrew Lenharth
d3355e22a7 Alpha zero extends setcc results 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21149 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 20:11:32 +00:00
Chris Lattner
cbd06fc3d7 PowerPC zero extends setcc results 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21147 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 19:41:49 +00:00
Chris Lattner
6659bd7592 X86 zero extends setcc results 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21146 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 19:41:46 +00:00
Andrew Lenharth
2966e84a8d fix a small optimization opertunity and make gcc happy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21143 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 18:15:28 +00:00
Andrew Lenharth
320174f009 fixup magic constant making code. tested by thousands of random divisions.... by 10000. ok, so random divisors would be good too, but this at least fixes some things 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21140 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 17:19:16 +00:00
Andrew Lenharth
9bf59d7ed2 lowercase instructions, makes diff happier 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21139 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 17:17:48 +00:00
Andrew Lenharth
273a1f956f It wasn't happy about this either 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21133 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 14:18:13 +00:00
Andrew Lenharth
706be918ca Yea, it wasn't happy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21132 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 13:55:53 +00:00
Duraid Madina
e6a0b6cbda teach asmprinter to print s8/s14 operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21131 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 12:34:36 +00:00
Duraid Madina
f55e403ef9 codegen immediate forms of add/sub/shift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21130 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 12:33:38 +00:00
Duraid Madina
18c0c6bcc4 add immediate forms of add, sub, shift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21129 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-07 12:32:24 +00:00
Nate Begeman
7ddecb4186 Pattern match bitfield insert, which helps shift long by immediate, among 
other things.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21127 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 23:51:40 +00:00
Nate Begeman
020ef42c19 Fix some shift bugs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21126 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 22:42:08 +00:00
Alkis Evlogimenos
aeca558788 Make these 64 bit constants so that this compiles on x86-32 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21125 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 22:09:40 +00:00
Andrew Lenharth
a565c275b5 added sdiv by 2^k and works for neg divisors also 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21124 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 22:03:13 +00:00
Andrew Lenharth
f77f395043 fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21121 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 20:59:59 +00:00
Chris Lattner
6d027f2e6f Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not 
properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21120 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 20:59:35 +00:00
Andrew Lenharth
4b8ac1559a Added Nate's div by constant stuff, also scaled operations! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21116 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 20:25:34 +00:00
Chris Lattner
ce91ec9ae6 Fix a namespace issue, reported by Vladimir Merzliakov! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21115 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 19:45:39 +00:00
Duraid Madina
4826a0786d steal sampo's div-by-constant-power-of-2 stuff 
thanks sampo!!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21113 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 09:55:17 +00:00
Duraid Madina
b366a02ff2 add fms instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21112 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 09:54:09 +00:00
Nate Begeman
27b4c23b80 Fixed version of optimized integer divide is now fixed. Calculate the 
quotient, not the remainder.  Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21111 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 06:44:57 +00:00
Duraid Madina
b70c2f3ef7 lie a bit and say that r1/r12 (GP/SP) _aren't_ callee-save, as we take 
care of this ourselves


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21110 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 06:18:36 +00:00
Duraid Madina
4ee131ffa8 make sure 'special' registers don't get allocated 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21109 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 06:17:54 +00:00
Chris Lattner
8db0af1c8d Add (untested) support for MULHS and MULHU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21107 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 04:21:07 +00:00
Chris Lattner
1e6a71524e add signed versions of the extra precision multiplies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21106 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 04:19:22 +00:00
Nate Begeman
8f52980f03 Turn off the div -> mul optimization until it works correctly 100% of the 
time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21105 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 03:36:33 +00:00
Nate Begeman
815d6dac1e Add support for MULHS and MULHU nodes 
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21104 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 00:25:27 +00:00
Andrew Lenharth
2513ddc239 added lowerargs support for varargs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21101 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 20:51:46 +00:00
Nate Begeman
ad5f65c74b Behold, rlwinm with certain immediate arguments is printed as the much more 
readable slwi or srwi (shift left/right word immediate).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21099 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 18:19:50 +00:00
Nate Begeman
a3829d5580 Fix cut & paste errors (32->64), and codegen float->int more optimally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21098 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 17:32:30 +00:00
Tanya Lattner
ac6e2dbf52 Updated to use dep analyzer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21097 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 16:36:44 +00:00
Nate Begeman
d3e6b94020 Remove 64 bit simple ISel, it never worked correctly 
Add initial (buggy) implementation of 64 bit pattern ISel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21096 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 08:51:15 +00:00
Nate Begeman
c8c5c8f0fa Back out the previous change to SelectBranchCC, since there are cases it 
could miscompile.  A correct solution will be found in the near future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21095 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 04:32:16 +00:00
Nate Begeman
439b444cad Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better 
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
  can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21094 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 04:22:58 +00:00
Nate Begeman
80196b1331 Implement SDIV by power of 2 as srawi/addze rather than load imm, divw 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21091 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 00:15:08 +00:00
Nate Begeman
93075ec0a5 Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21090 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 23:40:36 +00:00
Nate Begeman
178bb34ee5 Add support for multiply-add, multiply-sub, and their negated versions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21089 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 23:01:51 +00:00
Nate Begeman
d860aa62ac Make sure that arg regs used by the call instruction are marked as such, so 
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21086 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 22:17:48 +00:00
Nate Begeman
04ec80173b Remove unnecessary register copy now that regalloc is fixed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21085 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 21:48:13 +00:00
Nate Begeman
c3e2db407e i1 loads should also be from the low byte of the argument word. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21077 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 09:09:00 +00:00
Nate Begeman
e584668f04 Fix i64 return, fix CopyFromReg 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21076 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 06:52:38 +00:00
Duraid Madina
6e02e6842a fix SREM/UREM, which gave incorrect results for x%y if x was zero. This is 
an ugly hack, but it seems to work. I should fix this properly and add a test
as well.

fixes multisource/obsequi (maybe others)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21075 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 05:05:52 +00:00
Duraid Madina
09c61b9c19 add implicit use op 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21074 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 04:50:57 +00:00
Nate Begeman
6644d4c933 Full varargs support. All of UnitTests now passes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21070 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-03 23:11:17 +00:00
Nate Begeman
4ec0cbdf15 Pass the correct value for the chain to the store 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21066 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-03 22:22:56 +00:00
Nate Begeman
fa55470e39 Fix SHL_PARTS 
Start implementation of integer varargs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21065 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-03 22:13:27 +00:00
Andrew Lenharth
63b720ac7c is this simpler? I think it is simpler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21064 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-03 20:35:21 +00:00
Andrew Lenharth
500d025bd9 fix 101 regressions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21063 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-03 18:24:50 +00:00
Duraid Madina
162a837f63 .bss is no problem here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21061 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-03 14:52:01 +00:00
Nate Begeman
aa73a9f16f Keeping up with the Joneses. 
Implement not, nor, nand, and eqv


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21060 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-03 11:20:20 +00:00
Andrew Lenharth
10c085b525 Select optimization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21051 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 22:32:39 +00:00
Andrew Lenharth
0eaf6ce2ef Try several things. 1) drop /i from FP ops 2) factor out FP to Int moves and provide 21264 support for those 3) match not 4) match ornot andnot xornot 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21046 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 21:06:51 +00:00
Andrew Lenharth
7332f3e05d FNEG/FABS/UNDEF 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21029 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 19:11:07 +00:00
Andrew Lenharth
30b46d41bc FNEG/FABS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21028 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 19:04:58 +00:00
Duraid Madina
32c46f33b7 ia64 asmprinter fixes: 
- turn off assembler's autoalignment
  - set FunctionAddrPrefix/Suffix so that .data8 entries pointing to
    functions have their value wrapped in @fptr(), so that a function
    descriptor will be materialized for that function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21025 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 12:30:47 +00:00
Duraid Madina
75c9fcbdcc support IDEF, fnegabs (thanks sampo) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21023 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 10:33:53 +00:00
Duraid Madina
5c156b7473 add fnegabs op 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21022 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 10:06:27 +00:00
Nate Begeman
27eeb00a1a Set shift amount to Extend 
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21018 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 05:59:34 +00:00
Chris Lattner
b7edaa1d08 add support for FABS and FNEG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21015 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 05:30:17 +00:00
Duraid Madina
a7ee8b8f04 add support FNEG and FABS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21012 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 05:18:38 +00:00
Chris Lattner
43fdea070c This target doesn't support fabs/fneg yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 05:03:24 +00:00
Chris Lattner
b1f26fb921 add an fabs instr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21006 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 04:31:56 +00:00
Chris Lattner
b38a7495da Add support for 64-bit shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21005 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 04:01:14 +00:00
Nate Begeman
27523a1c92 Fix i64 returns 
Generate PowerPC 'subfic' instruction when appropriate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20995 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 00:42:16 +00:00
Chris Lattner
7ce7eff54c Add support for ISD::UNDEF to the X86 be 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20990 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 22:46:45 +00:00
Nate Begeman
fc1b1dad88 Add ISD::UNDEF node 
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
  arguments, but not shadowing their value.  This allows us to do the right
  thing with both fixed and vararg floating point arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20988 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 22:34:39 +00:00
Chris Lattner
e6fea166c3 Fix another PATypeHolder error, contributed by Bill Wendling! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20983 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 15:41:30 +00:00
Duraid Madina
69c8e20aa1 repair mindless SELECT waste. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20982 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 10:35:00 +00:00
Nate Begeman
6cb2e1b124 Fix Olden/bh, CR0 was being set in the wrong order 
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20981 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 08:57:43 +00:00
Nate Begeman
31318e4b6c Also apply Chris's fix to FP select and SETCC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20979 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 07:21:30 +00:00
Chris Lattner
3071019026 Move the selection of the arms of the select operation up to the conditional 
part to make sure we get the side effects and to avoid confusing the CFG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20977 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 07:10:02 +00:00
Nate Begeman
a7e11a4bb5 Fix stores to global addresses 
Fix calls with no arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20975 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 05:57:17 +00:00
Nate Begeman
04730361b5 Support indexed loads and stores. This drops Shootout/matrix time from 
18.8 to 14.8 seconds.  The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20973 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 04:45:11 +00:00
Nate Begeman
6b55997df5 Implement FP_TO_SINT and FP_TO_UINT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20972 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 02:59:27 +00:00
Nate Begeman
6d369ccae0 Add support for adding 0.0 and -0.0 to the constant pool, since we lie and 
say that we support them, for the purposes of generating fsel instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20970 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 01:08:07 +00:00
Nate Begeman
dffcfccc13 Factor out common code, support FP comparison in folded SetCC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20969 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-01 00:32:34 +00:00
Nate Begeman
3e89716ad7 fsel generation for f32 and f64 select 
generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select

Code generation quality for Shootout is now on par with the Simple ISel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20968 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-31 23:55:40 +00:00
Andrew Lenharth
5e99dd9c2b make fp div trick dependend on flag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20967 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-31 22:02:25 +00:00
Andrew Lenharth
95762124a1 PCMarker support for DAG and Alpha 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20965 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-31 21:24:06 +00:00
Duraid Madina
beeaab28a5 Assorted fixes: 
* Stop being pessimistic about output register allocation
  * Start to handle function descriptors: compute target GPs and so on
  when doing indirect calls etc. Not there yet, though. For the moment,
  we try to use _indirect_ branches wherever possible, to stress test
  function descriptors.
  * FP divide-by-zero should work now
  * add varargs (it doesn't work, though)

At this point, all of SingleSource passes (modulo C++ tests that are due
to issues with the CFE, see note in the README.) Much of MultiSource also
passes although there's still a ton of bugs around. Something for me to
work on tomorrow, then. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20960 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-31 12:31:11 +00:00