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04b091a782
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3937 Commits

Author SHA1 Message Date
Chris Lattner
04b091a782 handle equality memcmp of 8 bytes on x86-64 with two unaligned loads and a 
compare.  On other targets we end up with a call to memcmp because we don't
want 16 individual byte loads.  We should be able to use movups as well, but
we're failing to select the generated icmp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92107 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-24 01:07:17 +00:00
Chris Lattner
8047d9a6be move an optimization for memcmp out of simplifylibcalls and into 
SDISel.  This optimization was causing simplifylibcalls to 
introduce type-unsafe nastiness.  This is the first step, I'll be 
expanding the memcmp optimizations shortly, covering things that
we really really wouldn't want simplifylibcalls to do.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92098 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-24 00:37:38 +00:00
Nuno Lopes
ec9d8b0047 move a few more symbols to .rodata 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 17:48:10 +00:00
Dale Johannesen
9949933d6e Use more sensible type for flags in asms. PR 5570. 
Patch by Sylve`re Teissier (sorry, ASCII only).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91988 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 07:32:51 +00:00
Eric Christopher
d060b2576a Update objectsize intrinsic and associated dependencies. Fix 
lowering code and update testcases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 02:51:48 +00:00
Bill Wendling
0d58013c3f Remove superfluous SDNode ordering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91971 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:28:19 +00:00
Bill Wendling
fc67bbe7bc Remove node ordering from inline asm nodes. It's not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91961 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 00:47:20 +00:00
Bill Wendling
c1d3c944ab Remove node ordering from VA nodes. It's not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91958 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 00:44:51 +00:00
Bill Wendling
775db97a50 Revert r91949 r91942 and r91936. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91953 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 00:28:23 +00:00
Bill Wendling
122d06de74 Finish up node ordering in ExpandNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91949 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 00:05:09 +00:00
Bill Wendling
3dbcb55b40 Assign ordering to nodes created in ExpandNode. Only roughly 1/2 of the function 
is finished.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91942 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 23:44:56 +00:00
Bill Wendling
167bea71a4 Assign ordering to SDNodes in PromoteNode. Also fixing a subtle bug where BSWAP 
was using "Tmp1" in the first getNode call instead of Node->getOperand(0).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91936 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 22:53:39 +00:00
Bill Wendling
3ea58b6d7a Allow 0 as an order number. Don't assign an order to formal arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 21:35:02 +00:00
Bob Wilson
e261b0c90b Report an error for bad inline assembly, where the value passed for an 
"indirect" operand is not a pointer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91913 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 18:34:19 +00:00
Bill Wendling
3ea3c24619 Add more plumbing. This time in the LowerArguments and "get" functions which 
return partial registers. This affected the back-end lowering code some.

Also patch up some places I missed before in the "get" functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 02:10:19 +00:00
Bill Wendling
651ad13d3c Add SDNode ordering to inlined asm and VA functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91876 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 01:25:10 +00:00
Bill Wendling
ec72e32fb0 Adding more assignment of ordering to SDNodes. This time in the "call" and 
generic copy functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91872 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 01:11:43 +00:00
Bill Wendling
e80ae836f2 Add ordering of SDNodes to LowerCallTo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91866 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 00:50:32 +00:00
Bill Wendling
d0283fa69f Now add ordering to SDNodes created by the massive intrinsic lowering function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91863 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 00:40:51 +00:00
Bill Wendling
856ff41079 To make things interesting, I added MORE code to set the ordering of 
SDNodes. This time in the load/store and limited-precision code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91860 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 00:12:37 +00:00
Bill Wendling
87710f04e5 Add more plumbing to assign ordering to SDNodes. Have the "getValue" method 
assign the ordering when called. Combine some of the ordering assignments to
keep things simple.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91857 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 23:47:40 +00:00
Bill Wendling
e1a9042041 More ordering plumbing. This time for GEP. I need to remember to assign 
orderings to values returned by getValue().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 23:10:19 +00:00
Bill Wendling
b85b6e8882 Another incremental check-in for assigning ordering to SDNodes. This time for 
shuffle and insert vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91847 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 22:42:14 +00:00
Bill Wendling
49fcff8a5d Assign ordering to more instructions. Incremental check-in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91846 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 22:30:11 +00:00
Bill Wendling
0777e92721 - Add a bit more plumbing assigning an order to SDNodes. 
- Modify the "dump" method to emit the order of an SDNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91845 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 21:59:52 +00:00
Bill Wendling
3b7a41ce90 First wave of plumbing for assigning an ordering to SDNodes. This takes care of 
a lot of the branching instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91838 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 19:59:38 +00:00
Bill Wendling
e36025ec18 Place SDNodeOrdering.h in the directory it's used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91834 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 19:34:59 +00:00
Anton Korobeynikov
cc62c3c928 Use 4-arg getVTList) variant instead of generic one, when possible 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91744 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-19 02:04:00 +00:00
Bill Wendling
b4e6a5df5d Changes from review: 
- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
  doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.

This isn't used yet, so there should be no functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91727 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 23:32:53 +00:00
Evan Cheng
9ab2b98ba5 Increase opportunities to optimize (brcond (srl (and c1), c2)). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91717 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 21:31:31 +00:00
Bob Wilson
5afffaed5c Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 01:03:29 +00:00
Ken Dyck
bceddbdc91 Introduce EVT::getHalfSizedIntegerVT() for use in ExpandUnalignedStore() in 
LegalizeDAG.cpp. Unlike the code it replaces, which simply decrements the simple
type by one, getHalfSizedIntegerVT() searches for the smallest simple integer
type that is at least half the size of the type it is called on. This approach
has the advantage that it will continue working if a new value type (such as
i24) is added to MVT.

Also, in preparation for new value types, remove the assertions that
non-power-of-2 8-bit-mutiple types are Extended when legalizing extload and
truncstore operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91614 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 20:09:43 +00:00
Bob Wilson
266d945fff Fix a comment grammaro. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91584 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 05:07:36 +00:00
Evan Cheng
4c2b001f13 Revert this dag combine change: 
Fold (zext (and x, cst)) -> (and (zext x), cst)

DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91574 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 00:40:05 +00:00
Daniel Dunbar
819309efec Reapply r91392, it was only unmasking the bug, and since TOT is still broken having it reverted does no good. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91560 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 20:10:05 +00:00
Daniel Dunbar
222518d0bb Revert "Initial work on disabling the scheduler. This is a work in progress, and 
this", this broke llvm-gcc bootstrap for release builds on
x86_64-apple-darwin10.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91533 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 10:56:02 +00:00
Evan Cheng
9818c043d2 Make 91378 more conservative. 
1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91399 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 03:00:32 +00:00
Bill Wendling
614407a9d2 Initial work on disabling the scheduler. This is a work in progress, and this 
stuff isn't used just yet.

We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothesis is that the people who use these flags know what they are
doing, and have hand-optimized the C code to reduce latencies and other
conflicts.

The idea behind our scheme to turn off scheduling is to create a map "on the
side" during DAG generation. It will order the nodes by how they appeared in the
code. This map is then used during scheduling to get the ordering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91392 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 01:54:51 +00:00
Evan Cheng
8acb3100de Fold (zext (and x, cst)) -> (and (zext x), cst). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91380 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:52:11 +00:00
Evan Cheng
99b653c36f Propagate zest through logical shift. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91378 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:41:36 +00:00
Dan Gohman
2e141d744e Fix integer cast code to handle vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 23:40:38 +00:00
Dan Gohman
688fb80334 Fix this to properly clear the FastISel debug location. Thanks to 
Bill for spotting this!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91355 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 23:08:09 +00:00
Anton Korobeynikov
60283f9bc9 Fix weird typo which leads to unallocated memory access for nodes with 4 results. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91233 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-13 01:00:59 +00:00
Dan Gohman
a0474a83bf Delete an unnecessary line. The VTSDNode on a SIGN_EXTEND_REG is never 
a vector type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91181 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 23:26:08 +00:00
Dan Gohman
87862e77bb Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 21:31:27 +00:00
Dan Gohman
a4f9cc4e55 Fix the result type of SELECT nodes lowered from Select instructions with 
aggregate return values. This fixes PR5754.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91145 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 19:50:50 +00:00
Evan Cheng
7bd6478cd6 Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 01:53:58 +00:00
Evan Cheng
64fa4a9584 Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90922 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 01:36:00 +00:00
Evan Cheng
de2ace1758 Infer alignment for non-fixed stack object. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 01:17:24 +00:00
Evan Cheng
7ced2e0b30 Add const qualifier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 01:10:37 +00:00