Commit Graph

4327 Commits

Author SHA1 Message Date
Rafael Espindola
9924357175 Use CIE version 4 for dwarf4.
According to http://www.dwarfstd.org/doc/DWARF4.pdf appendix F the CIE
version for dwarf 4 is 4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235988 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 13:55:31 +00:00
Ahmed Bougacha
e1f835ab59 [MC] Use LShr for constant evaluation of ">>" on ELF/arm64--darwin.
This matches other assemblers and is less unexpected (e.g. PR23227).
On ELF, I tried binutils gas v2.24 and nasm 2.10.09, and they both
agree on LShr.  On COFF, I couldn't get my hands on an assembler yet,
so don't change the behavior.  For now, don't change it on non-AArch64
Darwin either, as the other assembler is gas v1.38, which does an AShr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235963 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 01:37:11 +00:00
Rafael Espindola
b8def5a8d1 Use CIE version 1 for .eh_frame.
According to

http://www.linuxbase.org/betaspecs/lsb/LSB-Core-generic/LSB-Core-generic/ehframechpt.html

we should always use 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235923 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 22:04:24 +00:00
Toma Tabacu
af3ec2cfd4 [mips] [IAS] Improve warning for using AT with .set noat.
Summary:
Changed the warning message to show the current value of $at, similar to what clang does for typedef's, and renamed warnIfAssemblerTemporary to a more descriptive name.

I also changed the type of variables which store registers from int to unsigned, updated the relevant test and tried to make the related comments clearer.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235881 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 14:05:04 +00:00
Toma Tabacu
0b5a15b779 [MC] [IAS] Add support for the \@ .macro pseudo-variable.
Summary:
When used, it is substituted with the number of .macro instantiations we've done up to that point in time.
So if this is the 1st time we've instantiated a .macro (any .macro, regardless of name), \@ will instantiate to 0, if it's the 2nd .macro instantiation, it will instantiate to 1 etc.

It can only be used inside a .macro definition, an .irp definition or an .irpc definition (those last 2 uses are undocumented).

Reviewers: echristo, rafael

Reviewed By: rafael

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D9197

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235862 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 10:50:29 +00:00
Hal Finkel
100eab89f5 [PowerPC] Support register name prefixes for vector registers
Match binutils by supporting the optional register name prefix for new vector
registers ("vs" for VSX registers and "q" for QPX registers).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235665 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:16:22 +00:00
Hal Finkel
ba03f542ac [PowerPC] Use sync inst alias when printing
So long as the choice between printing msync and sync is not ambiguous, we can
print 'sync 0' and just 'sync'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235663 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:05:08 +00:00
Hal Finkel
79f43b2736 [PowerPC] Add asm/disasm support for dcbt with hint
Add assembler/disassembler support for dcbt/dcbtst (and aliases) with the hint
field specified (non-zero). Unforunately, the syntax for this instruction is
special in that it differs for server vs. embedded cores:
   dcbt ra, rb, th [server]
   dcbt th, ra, rb [embedded]
where th can be omitted when it is 0. dcbtst is the same. Thus we need to play
games in the parser and the printer to flip the operands around on the embedded
cores. We'll use the server syntax as the default (binutils currently uses the
embedded form by default, but IBM is changing that).

We also stop marking dcbtst as having unmodeled side effects (this is not
necessary, it is just a hint like dcbt -- noticed by inspection, so no separate
test case).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 22:47:57 +00:00
Peter Collingbourne
f86c29ea2c ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.
This makes it more likely that we can use the 16-bit push and pop instructions
on Thumb-2, saving around 4 bytes per function.

Differential Revision: http://reviews.llvm.org/D9165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:31:26 +00:00
Peter Collingbourne
b28abbf98b ARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools.
This appears to have been introduced back in r76698 as part of an unrelated
change. I can find no official ARM documentation stating that Thumb-2 functions
require 4-byte alignment; in fact, ARM documentation appears to contradict
this (see, e.g., ARM Architecture Reference Manual Thumb-2 Supplement,
section 2.6.1: "Thumb-2 enforces 16-bit alignment on all instructions.").

Also remove code that sets alignment for ARM functions, which is redundant
with code in the MachineFunction constructor, and remove the hidden
-arm-align-constant-islands flag, which has been enabled by default since
r146739 (Dec 2011) and has probably received sufficient testing by now.

Differential Revision: http://reviews.llvm.org/D9138

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235636 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:31:22 +00:00
Tom Stellard
e32631cecd R600/SI: Add missing -mcpu=SI to assembler test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235630 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 19:33:55 +00:00
Tom Stellard
59edae9b85 R600/SI: Add assembler support for all CI and VI VOP1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235629 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 19:33:54 +00:00
Tom Stellard
95081f5241 R600/SI: Improve AsmParser support for forced e64 encoding
We can now force e64 encoding even when the operands would be legal
for e32 encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235626 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 19:33:48 +00:00
Hal Finkel
184f8f7c10 [PowerPC] Enable printing instructions using aliases
TableGen had been nicely generating code to print a number of instructions using
shorter aliases (and PowerPC has plenty of short mnemonics), but we were not
calling it. For some of the aliases we support in the parser, TableGen can't
infer the "inverse" alias relationship, so there is still more to do.

Thus, after some hours of updating test cases...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 18:30:38 +00:00
Hans Wennborg
defaf830f9 Re-commit r235560: Switch lowering: extract jump tables and bit tests before building binary tree (PR22262)
Third time's the charm. The previous commit was reverted as a
reverse for-loop in SelectionDAGBuilder::lowerWorkItem did 'I--'
on an iterator at the beginning of a vector, causing asserts
when using debugging iterators. This commit fixes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235608 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 16:45:24 +00:00
Aaron Ballman
5d538f71c2 Revert r235560; this commit was causing several failed assertions in Debug builds using MSVC's STL. The iterator is being used outside of its valid range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235597 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 13:41:59 +00:00
Hans Wennborg
395f4f4b2a Switch lowering: extract jump tables and bit tests before building binary tree (PR22262)
This is a re-commit of r235101, which also fixes the problems with the previous patch:

- Switches with only a default case and non-fallthrough were handled incorrectly

- The previous patch tickled a bug in PowerPC Early-Return Creation which is fixed here.

> This is a major rewrite of the SelectionDAG switch lowering. The previous code
> would lower switches as a binary tre, discovering clusters of cases
> suitable for lowering by jump tables or bit tests as it went along. To increase
> the likelihood of finding jump tables, the binary tree pivot was selected to
> maximize case density on both sides of the pivot.
>
> By not selecting the pivot in the middle, the binary trees would not always
> be balanced, leading to performance problems in the generated code.
>
> This patch rewrites the lowering to search for clusters of cases
> suitable for jump tables or bit tests first, and then builds the binary
> tree around those clusters. This way, the binary tree will always be balanced.
>
> This has the added benefit of decoupling the different aspects of the lowering:
> tree building and jump table or bit tests finding are now easier to tweak
> separately.
>
> For example, this will enable us to balance the tree based on profile info
> in the future.
>
> The algorithm for finding jump tables is quadratic, whereas the previous algorithm
> was O(n log n) for common cases, and quadratic only in the worst-case. This
> doesn't seem to be major problem in practice, e.g. compiling a file consisting
> of a 10k-case switch was only 30% slower, and such large switches should be rare
> in practice. Compiling e.g. gcc.c showed no compile-time difference.  If this
> does turn out to be a problem, we could limit the search space of the algorithm.
>
> This commit also disables all optimizations during switch lowering in -O0.
>
> Differential Revision: http://reviews.llvm.org/D8649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235560 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-22 23:14:56 +00:00
Elena Demikhovsky
bf704ed348 AVX-512: Added VPMOVx2M instructions for SKX,
fixed encoding of VPMOVM2x.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235385 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 14:38:31 +00:00
Elena Demikhovsky
695922de3d AVX-512: Added VPTESTM and VPTESTNM instructions for SKX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235383 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 13:13:46 +00:00
Toma Tabacu
203a9224ff [mips] [IAS] Implement the .asciiz directive.
Summary:
This directive is exactly the same as .asciz, except it's only used by MIPS.
It is used to store null terminated strings in object files.

Reviewers: rafael, dsanders, echristo

Reviewed By: dsanders, echristo

Subscribers: echristo, llvm-commits

Differential Revision: http://reviews.llvm.org/D7530

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235382 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 11:50:52 +00:00
Jozef Kolek
c589d1b3bc [mips][microMIPSr6] Implement CACHE and PREF instructions
Implement CACHE and PREF instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8893


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235379 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 11:17:25 +00:00
Elena Demikhovsky
a1fa0de258 AVX-512: Added logical and arithmetic instructions for SKX
by Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235375 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 10:27:40 +00:00
Derek Schuff
9b56994421 Tighten bundling section alignment test.
Leftover comment from http://reviews.llvm.org/D9131

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235366 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 00:17:59 +00:00
Derek Schuff
a49508cb92 [MC] When using bundle aligment, align sections to bundle size
Summary:
Bundle aligment requires that the functions always start at an aligned address.
Usually this is ensured by the compiler, but assembly code does not always
begin with a .align directive.

This change ensures that sections get the correct alignment if they contain
any instructions and bundling is enabled. (It also makes LLVM match the
behavior of GNU as).

Differential Revision: http://reviews.llvm.org/D9131

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235365 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 00:14:25 +00:00
Jozef Kolek
382bee5224 [mips][microMIPSr6] Implement BITSWAP instruction
Implement BITSWAP instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8857


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235321 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 18:14:59 +00:00
Vladimir Sukharev
d1e387b9e6 [AArch64] LORID_EL1 register must be treated as read-only
Patch by: John Brawn

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9105


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235314 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 16:54:37 +00:00
Jozef Kolek
fc4915076f [mips][microMIPSr6] Implement disassembler support
Implement disassembler support for microMIPS32r6.

Differential Revision: http://reviews.llvm.org/D8490


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235307 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 14:40:38 +00:00
Jozef Kolek
dbef0175c3 [mips][microMIPSr6] Implement BALC and BC instructions
This patch implements BALC and BC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8388


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 13:04:14 +00:00
Rafael Espindola
ca3837369f Look past locals in comdats.
We have to avoid converting a reference to a global into a reference to a local,
but it is fine to look past a local.

Patch by Vasileios Kalintiris.

I just moved the comment and added thet test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235300 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 12:44:06 +00:00
Rafael Espindola
fb118bd226 Compute A-B when A or B is weak.
Similar to r235222, but for the weak symbol case.

In an "ideal" assembler/object format an expression would always refer to the
final value and A-B would only be computed from a section in the same
comdat as A and B with A and B strong.

Unfortunately that is not the case with debug info on ELF, so we need an
heuristic.  Since we need an heuristic, we may as well use the same one as
gas:

* call weak_sym : produces a relocation, even if in the same section.
* A - weak_sym and weak_sym -A: don't produce a relocation if we can
  compute it.

This fixes pr23272 and changes the fix of pr22815 to match what gas does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235227 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-17 21:15:17 +00:00
Rafael Espindola
560d73a4cc Compute A-B if both A and B are in the same comdat section.
Part of pr23272.

A small annoyance with the assembly syntax we implement is that given an
expression there is no way to know if what is desired is the value of that
expression for the symbols in this file or for the final values of those
symbols in a link.

The first case is useful for use in sections that get discarded or ignored
if the section they are describing is discarded.

For axample, consider A-B where A and B are in the same comdat section.

We can compute the value of the difference in the section that is present in
the current .o and if that section survives to the final DSO the value will
still will be correct.

But the section is in a comdat. Another section from another object file
might be used istead. We know that that section will define A and B, but
we have no idea what the value of A-B might be.

In practice we have to assume that the intention is to compute the value
in the current section since otherwise the is no way to create something like
the debug aranges section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235222 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-17 20:05:17 +00:00
Rafael Espindola
c59decb902 Add a proper fix for pr23025.
Instead of avoiding looking past every global symbol, only do so
if the symbol is in a comdat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235181 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-17 11:27:13 +00:00
Rafael Espindola
e95f704ed9 Add a reduced testcase from pr23025.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235168 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-17 09:05:25 +00:00
Rafael Espindola
2298ce3d6a Don't walk aliases from global to local symbols in comdats.
This fixes pr23196.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235167 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-17 08:46:11 +00:00
Rafael Espindola
b4b0b34181 Write relocation sections contiguously.
Linkers normally read all the relocations upfront to compute the references
between sections. Putting them together is a bit more cache friendly.

I benchmarked linking a Release+Asserts clang with gold on a vm. I tried all
4 combinations of --gc-sections/no --gc-section hot and cold cache.

I cleared the cache with

echo 3 > /proc/sys/vm/drop_caches

and warmed it up by running the link once before timing the subsequent ones.

With cold cache and --gc-sections the time goes from

1.86130781665 +- 0.01713126697463843 seconds
to
1.82370735105 +- 0.014127522318814516 seconds

With cold cache and no --gc-sections the time goes from

1.6087245435500002 +- 0.012999066825178644 seconds
to
1.5687122041500001 +- 0.013145850126026619 seconds

With hot cache and no --gc-sections the time goes from

0.926200939 ( +-  0.33% ) seconds
to
0.907200079 ( +-  0.31% ) seconds

With hot cache and gc sections the time goes from

1.183038049 ( +-  0.34% ) seconds
to
1.147355862 ( +-  0.39% ) seconds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-17 08:11:38 +00:00
David Blaikie
32b845d223 [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction
See r230786 and r230794 for similar changes to gep and load
respectively.

Call is a bit different because it often doesn't have a single explicit
type - usually the type is deduced from the arguments, and just the
return type is explicit. In those cases there's no need to change the
IR.

When that's not the case, the IR usually contains the pointer type of
the first operand - but since typed pointers are going away, that
representation is insufficient so I'm just stripping the "pointerness"
of the explicit type away.

This does make the IR a bit weird - it /sort of/ reads like the type of
the first operand: "call void () %x(" but %x is actually of type "void
()*" and will eventually be just of type "ptr". But this seems not too
bad and I don't think it would benefit from repeating the type
("void (), void () * %x(" and then eventually "void (), ptr %x(") as has
been done with gep and load.

This also has a side benefit: since the explicit type is no longer a
pointer, there's no ambiguity between an explicit type and a function
that returns a function pointer. Previously this case needed an explicit
type (eg: a function returning a void() function was written as
"call void () () * @x(" rather than "call void () * @x(" because of the
ambiguity between a function returning a pointer to a void() function
and a function returning void).

No ambiguity means even function pointer return types can just be
written alone, without writing the whole function's type.

This leaves /only/ the varargs case where the explicit type is required.

Given the special type syntax in call instructions, the regex-fu used
for migration was a bit more involved in its own unique way (as every
one of these is) so here it is. Use it in conjunction with the apply.sh
script and associated find/xargs commands I've provided in rr230786 to
migrate your out of tree tests. Do let me know if any of this doesn't
cover your cases & we can iterate on a more general script/regexes to
help others with out of tree tests.

About 9 test cases couldn't be automatically migrated - half of those
were functions returning function pointers, where I just had to manually
delete the function argument types now that we didn't need an explicit
function type there. The other half were typedefs of function types used
in calls - just had to manually drop the * from those.

import fileinput
import sys
import re

pat = re.compile(r'((?:=|:|^|\s)call\s(?:[^@]*?))(\s*$|\s*(?:(?:\[\[[a-zA-Z0-9_]+\]\]|[@%](?:(")?[\\\?@a-zA-Z0-9_.]*?(?(3)"|)|{{.*}}))(?:\(|$)|undef|inttoptr|bitcast|null|asm).*$)')
addrspace_end = re.compile(r"addrspace\(\d+\)\s*\*$")
func_end = re.compile("(?:void.*|\)\s*)\*$")

def conv(match, line):
  if not match or re.search(addrspace_end, match.group(1)) or not re.search(func_end, match.group(1)):
    return line
  return line[:match.start()] + match.group(1)[:match.group(1).rfind('*')].rstrip() + match.group(2) + line[match.end():]

for line in sys.stdin:
  sys.stdout.write(conv(re.search(pat, line), line))

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235145 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 23:24:18 +00:00
Hans Wennborg
e2711530de Revert the switch lowering change (r235101, r235103, r235106)
Looks like it broke the sanitizer-ppc64-linux1 build. Reverting for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235108 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 15:43:26 +00:00
Vladimir Sukharev
cf9593b050 [AArch64] Add v8.1a "Virtualization Host Extensions"
Reviewers: t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8500

Patch by: Tom Coxon


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235107 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 15:38:58 +00:00
Vladimir Sukharev
39c4ba63f2 [AArch64] Add v8.1a "Limited Ordering Regions" extension
Reviewers: 	t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8499

Patch by: Tom Coxon


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235105 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 15:30:43 +00:00
Vladimir Sukharev
798efb5b3a [AArch64] Add v8.1a "Privileged Access Never" extension
Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8498


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235104 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 15:20:51 +00:00
Hans Wennborg
cc987d98bb Switch lowering: extract jump tables and bit tests before building binary tree (PR22262)
This is a major rewrite of the SelectionDAG switch lowering. The previous code
would lower switches as a binary tre, discovering clusters of cases
suitable for lowering by jump tables or bit tests as it went along. To increase
the likelihood of finding jump tables, the binary tree pivot was selected to
maximize case density on both sides of the pivot.

By not selecting the pivot in the middle, the binary trees would not always
be balanced, leading to performance problems in the generated code.

This patch rewrites the lowering to search for clusters of cases
suitable for jump tables or bit tests first, and then builds the binary
tree around those clusters. This way, the binary tree will always be balanced.

This has the added benefit of decoupling the different aspects of the lowering:
tree building and jump table or bit tests finding are now easier to tweak
separately.

For example, this will enable us to balance the tree based on profile info
in the future.

The algorithm for finding jump tables is O(n^2), whereas the previous algorithm
was O(n log n) for common cases, and quadratic only in the worst-case. This
doesn't seem to be major problem in practice, e.g. compiling a file consisting
of a 10k-case switch was only 30% slower, and such large switches should be rare
in practice. Compiling e.g. gcc.c showed no compile-time difference.  If this
does turn out to be a problem, we could limit the search space of the algorithm.

This commit also disables all optimizations during switch lowering in -O0.

Differential Revision: http://reviews.llvm.org/D8649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235101 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 14:49:23 +00:00
Toma Tabacu
9f8549a4a0 [mips] [IAS] Preserve microMIPS label marking for objects when assigning.
Summary: Previously, this was only happening for functions, but because of .insn, objects can also be marked now.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8007

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235095 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 13:37:32 +00:00
Rafael Espindola
05da50f87b Don't depend on the order relocations are written to a .o file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235092 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 12:59:30 +00:00
Vladimir Sukharev
5ade5fcee4 [ARM] Add v8.1a "Privileged Access Never" extension
Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8504


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235087 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 11:34:25 +00:00
Toma Tabacu
e7d84301cc [mips] [IAS] Add support for the .insn directive.
Summary:
This assembler directive marks the current label as an instruction label in microMIPS and MIPS16.

This initial implementation works only for microMIPS.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8006

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235084 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 09:53:47 +00:00
Charlie Turner
fdb3720f58 Fix BXJ is undefined in AArch32.
BXJ was incorrectly said to be unsupported in ARMv8-A. It is not
supported in the A64 instruction set, but it is supported in the T32
and A32 instruction sets, because it's listed as an instruction in the
ARM ARM section F7.1.28.

Using SP as an operand to BXJ changed from UNPREDICTABLE to
PREDICTABLE in v8-A. This patch reflects that update as well.

This was found by MCHammer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235024 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-15 17:28:23 +00:00
Rafael Espindola
11df480f67 Make it explicit which sections these relocations are in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235022 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-15 17:24:06 +00:00
Rafael Espindola
70a987303a Make it clear in which sections these relocations are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235020 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-15 16:59:47 +00:00
Rafael Espindola
6d9fd9bc70 Make it clear where the relocations we are CHECKING are from.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235018 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-15 16:45:03 +00:00
Rafael Espindola
f194367792 Update tests to not be as dependent on section numbers.
Many of these predate llvm-readobj. With elf-dump we had to match
a relocation to symbol number and symbol number to symbol name or
section number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235015 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-15 15:59:37 +00:00