Commit Graph

81454 Commits

Author SHA1 Message Date
Rafael Espindola
168b1bebf0 Add support deterministic output in llvm-ar and make it the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242061 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 20:38:09 +00:00
Matt Arsenault
bae3cf3a1b AMDGPU: Minor cleanups to always inline pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242053 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 19:08:36 +00:00
David Majnemer
8a2d65cf4a [MC] Correctly escape .safeseh's symbol
This fixes PR24107.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242050 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 18:51:15 +00:00
Mark Heffernan
9be1720729 Enable partial and runtime loop unrolling for NVPTX.
Enable partial and runtime loop unrolling for NVPTX backend via
TTI::UnrollingPreferences with a small threshold. This partially unrolls
small loops which are often unrolled by the PTX to SASS compiler
and unrolling earlier can be beneficial.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242049 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 18:33:21 +00:00
Mark Heffernan
8a9e01d606 Enable runtime unrolling with unroll pragma metadata
Enable runtime unrolling for loops with unroll count metadata ("#pragma unroll N")
and a runtime trip count. Also, do not unroll loops with unroll full metadata if the
loop has a runtime loop count. Previously, such loops would be unrolled with a
very large threshold (pragma-unroll-threshold) if runtime unrolled happened to be
enabled resulting in a very large (and likely unwise) unroll factor.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242047 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 18:26:27 +00:00
Adrian Prantl
8f5464d3ab Service the doxygen comments in DwarfUnit and DwarfDebug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242046 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 18:25:29 +00:00
Alex Lorenz
ad7556d177 MIR Serialization: Serialize the fixed stack objects.
This commit serializes the fixed stack objects, including fixed spill slots.
The fixed stack objects are serialized using a YAML sequence of YAML inline
mappings. Each mapping has the object's ID, type, size, offset, and alignment.
The objects that aren't spill slots also serialize the isImmutable and isAliased
flags.

The fixed stack objects are a part of the machine function's YAML mapping.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242045 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 18:07:26 +00:00
Reid Kleckner
c6d1cc7e16 [WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name
Add another C++ 32-bit EH table test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242044 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 17:55:14 +00:00
Benjamin Kramer
0ed5091742 Remove macro guards for extern template instantiations.
This is a C++11 feature that both GCC and MSVC have supported as ane extension
long before C++11 was approved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242042 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 17:21:31 +00:00
Benjamin Kramer
ed5546e50b Avoid using Loop::getSubLoopsVector.
Passes should never modify it, just use the const version. While there
reduce copying in LoopInterchange. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242041 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 17:21:14 +00:00
James Y Knight
af8cf90e2f Fix handling of the 'n' asm constraint with invalid operands.
It had accidently accepted a symbol+offset value (and emitted
incorrect code for it, keeping only the offset part) instead of
properly reporting the constraint as invalid.

Differential Revision: http://reviews.llvm.org/D11039

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242040 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 16:36:22 +00:00
Tom Stellard
f5be357d37 AMDGPU/SI: Select mad patterns to v_mac_f32
The two-address instruction pass will convert these back to v_mad_f32
if necessary.

Differential Revision: http://reviews.llvm.org/D11060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242038 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 15:47:57 +00:00
Logan Chien
af3e4a2f2f ARM: Fix cttz expansion on vector types.
The 64/128-bit vector types are legal if NEON instructions are
available.  However, there was no matching patterns for @llvm.cttz.*()
intrinsics and result in fatal error.

This commit fixes the problem by lowering cttz to:
a. ctpop((x & -x) - 1)
b. width - ctlz(x & -x) - 1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242037 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 15:37:30 +00:00
Scott Douglass
f8560e5a5b [ARM] Handle commutativity when converting to tADDhirr in Thumb2
Also, run thumb_rewrite.s tests in Thumb2 now that they pass.

Differential Revision: http://reviews.llvm.org/D11132

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242036 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 15:31:48 +00:00
Scott Douglass
ffc51593c8 [ARM] Add Thumb2 ADD with SP narrowing from 3 operand to 2
Differential Revision: http://reviews.llvm.org/D11131

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242035 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 15:31:40 +00:00
Scott Douglass
f716895679 [ARM] Small refactor of tryConvertingToTwoOperandForm (nfc)
Also, add more Thumb2 ADD tests requested during review of
http://reviews.llvm.org/D11053.

Differential Revision: http://reviews.llvm.org/D11130

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242034 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 15:31:33 +00:00
Silviu Baranga
5b50110192 Cleanup after r241809 - remove uncessary call to std::sort
Summary:
The iteration order within a member of DepCands is deterministic
and therefore we don't have to sort the accesses within a member.
We also don't have to copy the indices of the pointers into a
vector, since we can iterate over the members of the class.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11145

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242033 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 14:48:24 +00:00
Rafael Espindola
46db875af8 Remove unused variable.
Sorry I missed it in the previous commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242032 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 14:43:33 +00:00
Rafael Espindola
0b2f27eb8d Aliases don't have available_externally linkage.
Allowing that is probably a good idea, but currently we don't, so
this is dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242031 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 14:39:02 +00:00
Rafael Espindola
94162a044b Don't change the visibility when converting a definition to a declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242030 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 14:18:22 +00:00
Aaron Ballman
b3e72a7c9d Removing several -Wunused-but-set-variable warnings; NFC intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242028 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 14:04:30 +00:00
Rafael Espindola
5572685621 Print the visibility of available_externally functions.
We were already printing it for declarations, but not available_externally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242027 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 13:55:18 +00:00
Manuel Klimek
c376473bb4 Revert r241981 "Revert "Revert r236894 "[BasicAA] Fix zext & sext handling"""
The repros from PR23626 still fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242025 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 13:50:55 +00:00
Elena Demikhovsky
a0a51734cd AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types.
In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch.
I temporary removed the old intrinsics test (just to split this patch).
Half types are not covered here.

Differential Revision: http://reviews.llvm.org/D11134



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242023 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 13:26:20 +00:00
Jingyue Wu
8e7e3650af [LSR] don't attempt to promote ephemeral values to indvars
Summary:
This at least saves compile time. I also encountered a case where
ephemeral values affect whether other variables are promoted, causing
performance issues. It may be a bug in LSR, but I didn't manage to
reduce it yet. Anyhow, I believe it's in general not worth considering
ephemeral values in LSR.

Reviewers: atrick, hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11115

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242011 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 03:28:53 +00:00
David Majnemer
46b13dd880 [InstSimplify] Teach InstSimplify how to simplify extractelement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242008 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 01:15:53 +00:00
David Majnemer
5501985a58 [InstSimplify] Teach InstSimplify how to simplify extractvalue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242007 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 01:15:46 +00:00
Renato Golin
4173058d07 [ARM] Add support for nest attribute using r12
Register r12 ('ip') is used by GCC for this purpose
and hence is used here. As discussed on the GCC mailing
list, the register choice is an ABI issue and so
choosing the same register as GCC means
__builtin_call_with_static_chain is compatible.

A similar patch has just gone in the AArch64 backend,
so this is just the ARM counterpart, following the same
discussion.

Patch by Stephen Cross.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241996 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-12 18:16:40 +00:00
Simon Pilgrim
9c64d9cc04 [X86][SSE] (V)PMINSB is commutable.
(V)PMINSB is no different to the other (V)PMIN/(V)PMAX B/D/W instructions - it is fully commutable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241994 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-12 16:44:11 +00:00
Simon Pilgrim
b3a04b5806 Trim trailing whitespaces. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241990 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-12 11:17:33 +00:00
Simon Pilgrim
f9df477221 [X86][SSE] Vectorized v4i32 non-uniform shifts.
While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized.

This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together.

Differential Revision: http://reviews.llvm.org/D11063

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241989 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-12 11:15:19 +00:00
David Majnemer
a1b821fac9 [LICM] Don't try to sink values out of loops without any exits
There is no suitable basic block to sink instructions in loops without
exits.  The only way an instruction in a loop without exits can be used
is as an incoming value to a PHI.  In such cases, the incoming block for
the corresponding value is unreachable.

This fixes PR24013.

Differential Revision: http://reviews.llvm.org/D10903

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241987 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-12 03:53:05 +00:00
Hal Finkel
866cf31c07 [PowerPC] Make use of the TargetRecip system
r238842 added the TargetRecip system for controlling use of reciprocal
estimates for sqrt and division using a set of parameters that can be set by
the frontend. Clang now supports a sophisticated -mrecip option, and this will
allow that option to effectively control the relevant code-generation
functionality of the PPC backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241985 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-12 02:33:57 +00:00
Hal Finkel
d14325bee9 [PowerPC] Support the nest parameter attribute
This adds support for the 'nest' attribute, which allows the static chain
register to be set for functions calls under non-Darwin PPC/PPC64 targets. r11
is the chain register (which the PPC64 ELF ABI calls the "environment
pointer"). For indirect calls under PPC64 ELFv1, this would normally be loaded
from the function descriptor, but providing an explicit 'nest' parameter will
override that process and use the value provided.

This allows __builtin_call_with_static_chain to work as expected on PowerPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241984 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-12 00:37:44 +00:00
Hal Finkel
1e3fa768c0 Revert "Revert r236894 "[BasicAA] Fix zext & sext handling""
r236894 caused PR23626 (Clang miscompiles webkit's base64 decoder), and was
reverted in r237984. This reapplies the patch with an additional test case for
PR23626 and the associated fix (both scales and offsets in the
BasicAliasAnalysis::constantOffsetHeuristic should initially be zero).

Patch by Nick White, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241981 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-11 11:04:54 +00:00
Hal Finkel
4e947d8111 Move getStrideFromPointer and friends from LoopVectorize to VectorUtils
The following functions are moved from the LoopVectorizer to VectorUtils:

  - getGEPInductionOperand
  - stripGetElementPtr
  - getUniqueCastUse
  - getStrideFromPointer

These used to be static functions in LoopVectorize, but will also be used by
the upcoming loop versioning LICM transformation.

Patch by Ashutosh Nema!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241980 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-11 10:52:42 +00:00
Igor Laevsky
6690dbffe0 Add argmemonly attribute.
This change adds new attribute called "argmemonly". Function marked with this attribute can only access memory through it's argument pointers. This attribute directly corresponds to the "OnlyAccessesArgumentPointees" ModRef behaviour in alias analysis.

Differential Revision: http://reviews.llvm.org/D10398



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241979 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-11 10:30:36 +00:00
Chandler Carruth
c51f300513 [PM/AA] Completely remove the AliasAnalysis::copyValue interface.
No in-tree alias analysis used this facility, and it was not called in
any particularly rigorous way, so it seems unlikely to be correct.

Note that one of the only stateful AA implementations in-tree,
GlobalsModRef is completely broken currently (and any AA passes like it
are equally broken) because Module AA passes are not effectively
invalidated when a function pass that fails to update the AA stack runs.

Ultimately, it doesn't seem like we know how we want to build stateful
AA, and until then trying to support and maintain correctness for an
untested API is essentially impossible. To that end, I'm planning to rip
out all of the update API. It can return if and when we need it and know
how to build it on top of the new pass manager and as part of *tested*
stateful AA implementations in the tree.

Differential Revision: http://reviews.llvm.org/D10889

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241975 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-11 04:39:00 +00:00
Tyler Nowicki
057d6c2904 Renamed some uses of unroll to interleave in the vectorizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241971 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-11 00:31:11 +00:00
Adrian Prantl
aefc592dd3 Cleanup a couple of comments in DIBuilder.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241966 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 23:26:02 +00:00
Duncan P. N. Exon Smith
c9978bab4b MC: Only allow changing feature bits in MCSubtargetInfo
Disallow all mutation of `MCSubtargetInfo` expect the feature bits.

Besides deleting the assignment operators -- which were dead "code" --
this restricts `InitMCProcessorInfo()` to subclass initialization
sequences, and exposes a new more limited function called
`setDefaultFeatures()` for use by the ARMAsmParser `.cpu` directive.

There's a small functional change here: ARMAsmParser used to adjust
`MCSubtargetInfo::CPUSchedModel` as a side effect of calling
`InitMCProcessorInfo()`, but I've removed that suspicious behaviour.
Since the AsmParser shouldn't be doing any scheduling, there shouldn't
be any observable change...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241961 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:52:15 +00:00
Matt Arsenault
ce43851064 AMDGPU: Fix chains for memory ops dependent on argument loads
Most loads and stores are derived from pointers derived from
a kernel argument load inserted during argument lowering.
This was just using the EntryToken chain for the argument loads,
and any users of these loads were also on the EntryToken chain.

Return the chain of the lowered argument load so that dependent loads
end up on the correct chain.

No test since I'm not aware of any case where this actually
broke.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241960 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:51:36 +00:00
Alex Lorenz
1cca87a981 MIR Serialization: Serialize the virtual register operands.
Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D11005


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241959 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:51:20 +00:00
David Majnemer
c3b47b30ab [IR] Switch static const to an enum to silence MSVC linker warnings
Integral class statics are handled oddly in MSVC, we don't need them
in this case, use an enum instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241958 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:46:02 +00:00
Duncan P. N. Exon Smith
16859aa242 MC: Remove MCSubtargetInfo() default constructor
Force all creators of `MCSubtargetInfo` to immediately initialize it,
merging the default constructor and the initializer into an initializing
constructor.  Besides cleaning up the code a little, this makes it clear
that the initializer is never called again later.

Out-of-tree backends need a trivial change: instead of calling:

    auto *X = new MCSubtargetInfo();
    InitXYZMCSubtargetInfo(X, ...);
    return X;

they should call:

    return createXYZMCSubtargetInfoImpl(...);

There's no real functionality change here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241957 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:43:42 +00:00
Duncan P. N. Exon Smith
5733fd14d4 MC: Remove MCSubtargetInfo::InitCPUSched()
Remove all calls to `MCSubtargetInfo::InitCPUSched()` and merge its body
into the only relevant caller, `MCSubtargetInfo::InitMCProcessorInfo()`.
We were only calling the former after explicitly calling the latter with
the same CPU; it's confusing to have both methods exposed.

Besides a minor (surely unmeasurable) speedup in ARM and X86 from
avoiding running the logic twice, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241956 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:33:01 +00:00
Bjorn Steinbrink
ca7473f5d0 [InstCombine] Actually combine AA metadata when replacing one load with another
Fixes PR24083

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241955 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:30:17 +00:00
Matt Arsenault
bd884766bf AMDGPU: Use requested chain when lowering arguments
No test since I'm not aware of any case where this will
end up being a different chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241954 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:28:41 +00:00
Matthias Braun
eada3a8b97 ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241951 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:23:57 +00:00
Reid Kleckner
09450da653 [SEH] Push reloads of the SEH code past phi nodes
This in turn would sometimes introduce new cleanupblocks that didn't
previously exist. The uses were being introduced by SSA value demotion.
We actually want to *promote* uses of EH pointers and selectors, so I
added some spcecial casing to avoid demoting such instructions.  This is
getting overly complicated, but hopefully we'll come along and delete it
in the new representation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241950 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:21:54 +00:00
Duncan P. N. Exon Smith
34b9a7dcb1 Add <type_traits> for is_pod, fixing r241947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241949 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:17:49 +00:00
Matt Arsenault
ee6d5d1c9e DAGCombiner: Assume invariant load cannot alias a store
The motivation is to allow GatherAllAliases / FindBetterChain
to not give up on dependent loads of a pointer from constant memory.

This is important for AMDGPU, because most loads are pointers
derived from a load of a kernel argument from constant memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241948 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:17:40 +00:00
Duncan P. N. Exon Smith
d819fac294 MC: Remove the copy of MCSchedModel in MCSubtargetInfo
`MCSchedModel` is large.  Make `MCSchedModel::GetDefaultSchedModel()`
return by-reference instead of by-value, so we can store a pointer in
`MCSubtargetInfo::CPUSchedModel` instead of a copy.

Note: since `MCSchedModel` is POD, this doesn't create a static
constructor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241947 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:13:43 +00:00
Quentin Colombet
722aa9573b [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks.
Although this is not incorrect to insert such code, it is useless
and it hurts the binary size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241946 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:09:55 +00:00
David Majnemer
7ebb7ed7d0 [MC] Switch static const to an enum to silence MSVC linker warnings
Integral class statics are handled oddly in MSVC, we don't need them in
this case, use an enum instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241945 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 21:50:04 +00:00
Evgeniy Stepanov
61b8d4a9df Fix AArch64 prologue for empty frame with dynamic allocas.
Fixes PR23804: assertion failure in emitPrologue in the case of a
function with an empty frame and a dynamic alloca that needs stack
realignment. This is a typical case for AddressSanitizer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241943 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 21:24:07 +00:00
Jingyue Wu
020938f3ee [TTI] BasicTTIImpl assumes no vector registers
Summary:
Following the discussion on r241884, it's more reasonable to assume that a
target has no vector registers by default instead of letting every such
target overrides getNumberOfRegisters.

Therefore, this patch modifies BasicTTIImpl::getNumberOfRegisters to
return 0 when Vector is true, and partially reverts r241884 which
modifies NVPTXTTIImpl::getNumberOfRegisters.

It also fixes a performance bug in LoopVectorizer. Even if a target has
no vector registers, vectorization may still help ILP. So, we need both
checks to be false before disabling loop vectorization all together.

Reviewers: hfinkel

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11108

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241942 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 21:14:54 +00:00
Adam Nemet
31a4111f50 [LoopDist/LoopVer] Move LoopVersioning to a new module, NFC
Summary:
The class will obviously need improvement down the road.  For one, there
is no reason that addPHINodes would have to be exposed like that.  I
will make this and other improvements in follow-up patches.

The main goal is to be able to share this functionality.  The
LoopLoadElimination pass I am working on needs it too.  Later we can
move other clients as well (LV and Ashutosh's LICMVer).

Reviewers: hfinkel, ashutosh.nema

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10577

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241932 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:55:13 +00:00
Adam Nemet
8c3eef8b7c [LoopDist] Move loop-versioning helper functions to Cloning, NFC
Summary:
This makes them available to the LoopVersioning class as that is moved
to its own module in the next patch.

Reviewers: ashutosh.nema, hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10576

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241931 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:55:09 +00:00
Matthias Braun
74c23af006 ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code
This commit factors out common code from MergeBaseUpdateLoadStore() and
MergeBaseUpdateLSMultiple() and introduces a new function
MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a
strd/ldrd instruction into an strd/ldrd instruction with writeback where
possible.

Differential Revision: http://reviews.llvm.org/D10676

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241928 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:37:33 +00:00
Fiona Glaser
b0a2d8c5a5 ComputeKnownBits: be a bit smarter about ADDs
If our two inputs have known top-zero bit counts M and N, we trivially
know that the output cannot have any bits set in the top (min(M, N)-1)
bits, since nothing could carry past that point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241927 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:29:02 +00:00
Matthias Braun
02e89ace70 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2
Differential Revision: http://reviews.llvm.org/D10623

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241926 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:28:49 +00:00
JF Bastien
7bfd515593 WebAssembly: basic instructions todo, and basic register info.
Summary:
This code is based on AArch64 for modern backend good practice, and NVPTX for
virtual ISA concerns.

Reviewers: sunfish

Subscribers: aemerson, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11070

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241923 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:23:10 +00:00
Alex Lorenz
b83896903b MIR Serialization: Initial serialization of stack objects.
This commit implements the initial serialization of stack objects from the
MachineFrameInfo class. It can only serialize the ordinary stack objects
(including ordinary spill slots), but it doesn't serialize variable sized or
fixed stack objects yet.

The stack objects are serialized using a YAML sequence of YAML inline mappings.
Each mapping has the object's ID, type, size, offset and alignment. The stack
objects are a part of machine function's YAML mapping.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241922 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:13:57 +00:00
JF Bastien
99cb989593 Target RegisterInfo: devirtualize TargetFrameLowering
Summary:
The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can.

This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here.

Subscribers: sunfish, ted, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241921 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:13:17 +00:00
Matthias Braun
892af54a91 ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.
This improves the logic in several ways and is a preparation for
followup patches:
- First perform an analysis and create a list of merge candidates, then
  transform. This simplifies the code in that you have don't have to
  care to much anymore that you may be holding iterators to
  MachineInstrs that get removed.
- Analyze/Transform basic blocks in reverse order. This allows to use
  LivePhysRegs to find free registers instead of the RegisterScavenger.
  The RegisterScavenger will become less precise in the future as it
  relies on the deprecated kill-flags.
- Return the newly created node in MergeOps so there's no need to look
  around in the schedule to find it.
- Rename some MBBI iterators to InsertBefore to make their role clear.
- General code cleanup.

Differential Revision: http://reviews.llvm.org/D10140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241920 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:08:49 +00:00
Eli Bendersky
98da4704dd Actually support volatile memcpys in NVPTX lowering
Differential Revision: http://reviews.llvm.org/D11091



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241914 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 15:40:33 +00:00
Nemanja Ivanovic
46c36cfa0f NFC. Added a blank line for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241913 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 14:25:17 +00:00
Benjamin Kramer
b0927bee8e [InstSimplify] Fold away ord/uno fcmps when nnan is present.
This is important to fold away the slow case of complex multiplies
emitted by clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241911 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 14:02:02 +00:00
James Molloy
ee0d992b07 Add support for fast-math flags to the FCmp instruction.
FCmp behaves a lot like a floating-point binary operator in many ways,
and can benefit from fast-math information. Flags such as nsz and nnan
can affect if this fcmp (in combination with a select) can be treated
as a fminnum/fmaxnum operation.

This adds backwards-compatible bitcode support, IR parsing and writing,
LangRef changes and IRBuilder changes. I'll need to audit InstSimplify
and InstCombine in a followup to find places where flags should be
copied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241901 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 12:52:00 +00:00
Nemanja Ivanovic
e57b60a7f9 Add missing builtins to the PPC back end for ABI compliance (vol. 3)
This patch corresponds to review:
http://reviews.llvm.org/D10973

Back end portion of the third round of additions to altivec.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 12:38:08 +00:00
Alexey Bataev
f7dc9d0f5e Disable loop re-rotation for -Oz (patch by Andrey Turetsky)
After changes in rL231820 loop re-rotation is performed even in -Oz mode. Since loop rotation is disabled for -Oz, it seems loop re-rotation should be disabled too.
Differential Revision: http://reviews.llvm.org/D10961


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241897 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 10:37:09 +00:00
David Majnemer
eddf9e2057 Revert the new EH instructions
This reverts commits r241888-r241891, I didn't mean to commit them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241893 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:15:17 +00:00
David Majnemer
ec83dbdc5e Tighten the verifier check for catchblock.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:01:07 +00:00
David Majnemer
2431442e67 Address Joseph's review comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241890 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:01:03 +00:00
David Majnemer
a5d05b7711 Address Reid's review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241889 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:00:58 +00:00
David Majnemer
751c4be705 New EH representation for MSVC compatibility
Summary:
This introduces new instructions neccessary to implement MSVC-compatible
exception handling support.  Most of the middle-end and none of the
back-end haven't been audited or updated to take them into account.

Reviewers: rnk, JosephTremoulet, reames, nlewycky, rjmccall

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11041

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241888 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:00:44 +00:00
Bjorn Steinbrink
86ef198476 [InstCombine] Employ AliasAnalysis in FindAvailableLoadedValue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241887 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 06:55:49 +00:00
Bjorn Steinbrink
ad4d73941a [InstCombine] Properly combine metadata when replacing a load with another
Not doing this can lead to misoptimizations down the line, e.g. because
of range metadata on the replacing load excluding values that are valid
for the load that is being replaced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241886 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 06:55:44 +00:00
Jingyue Wu
dde12814c7 [NVPTX] declare no vector registers
Summary:
Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll)
produces code with complex control flow which hurts later optimizations. Since
NVPTX doesn't have vector registers in LLVM's sense
(NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector
registers to effectively disable loop vectorization.

Reviewers: jholewinski

Subscribers: jingyue, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11089

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241884 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 04:31:56 +00:00
Reid Kleckner
b4eeb6bca5 [WinEH] Make sure LSDA tables are 4 byte aligned
Apparently this is important, otherwise _except_handler3 assumes that
the registration node is corrupted and ignores it.

Also fix a bug in WinEHPrepare where we would insert code after a
terminator instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241877 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 00:08:49 +00:00
Eli Bendersky
89a5e2532d Replace index-loops by range-based loops
NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241875 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 23:06:03 +00:00
Sanjay Patel
c68ccc1a70 [x86] enable machine combiner reassociations for scalar double-precision multiplies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241873 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:58:39 +00:00
Sanjay Patel
39f09b5150 [x86] enable machine combiner reassociations for scalar double-precision adds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241871 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:48:54 +00:00
Alex Lorenz
ad6702ec23 MIR Serialization: Serialize the virtual register definitions.
The virtual registers are serialized using a YAML sequence of YAML inline
mappings. Each mapping has the id of the virtual register and the register
class.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:23:13 +00:00
Adam Nemet
81e7e2dfab [LAA] Fix grammar in debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241867 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:17:41 +00:00
Adam Nemet
1c25d370c1 [LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFC
Currently canCheckPtrAtRT returns two flags NeedRTCheck and CanDoRT.
NeedRTCheck says whether we need checks and CanDoRT whether we can
generate the checks.  The idea is to encode three states with these:

     Need/Can:
(1) false/dont-care: no checks are needed
(2) true/false: we need checks but can't generate them
(3) true/true: we need checks and we can generate them

This is pretty unnecessary since the caller (analyzeLoop) is only
interested in whether we can generate the checks if we actually need
them (i.e. 1 or 3).

So this change cleans up to return just that (CanDoRTIfNeeded) and pulls
all the underlying logic into canCheckPtrAtRT.

By doing all this, we simplify analyzeLoop which is the complex function
in LAA.

There is further room for improvement here by using RtCheck.Need
directly rather than a new local variable NeedRTCheck but that's for a
later patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241866 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:17:38 +00:00
Reid Kleckner
5cf6c0b070 [WinEH] Give up on using CSRs across 32-bit invokes for now
The runtime does not restore CSRs when transferring control back to the
function handling the exception. According to the experts on IRC, LLVM's
register allocator has no way to model register clobbers that only
happen on one edge of the CFG. For now, don't worry about trying to use
the meager three CSRs available on 32-bit X86 and just say that such
invokes preserve nothing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241865 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:09:41 +00:00
Reid Kleckner
827f211e95 Expose sjlj preparation through opt for my own debugging purposes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241864 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:48:40 +00:00
Alex Lorenz
ccba68af82 MIR Parser: Report an error when parsing machine function with an empty body.
This commit adds a new error which is reported when the MIR Parser encounters
a machine function without any machine basic blocks. The machine verifier
expects that the machine functions have at least one MBB, and this error will
prevent machine functions without MBBs from reaching the machine verifier and
crashing with an assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241862 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:21:33 +00:00
Tom Stellard
847c023a2e AMDGPU: Add helper function for implicit parameter offsets.
Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241861 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:20:37 +00:00
JF Bastien
b5ebaf3ae5 Unbreak WebAssembly build
Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed.

Reviewers: sunfish, joker.eph, echristo

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241859 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:00:09 +00:00
Sanjoy Das
efec6ccae3 [ImplicitNullChecks] Fix a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241851 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:13:31 +00:00
Sanjoy Das
a5a3e2d58a [ImplicitNullChecks] Be smarter in picking the memory op.
Summary:
Before this change ImplicitNullChecks would only pick loads of the form:

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   movl 32(Reg), Reg2
```

but not (say)

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   inc Reg3
   movl 32(Reg), Reg2
```

This change teaches ImplicitNullChecks to look through "unrelated"
instructions like `inc Reg3` when searching for a load instruction
to convert to a trapping load.

Reviewers: atrick, JosephTremoulet, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:13:25 +00:00
Alex Lorenz
7c6ad33126 MIR Serialization: Serialize the simple MachineFrameInfo attributes.
This commit serializes the 13 scalar boolean and integer attributes from the
MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap,
HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack,
HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and
HasMustTailInVarArgFunc. These attributes are serialized as part
of the frameInfo YAML mapping, which itself is a part of the machine function's
YAML mapping.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241844 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 19:55:27 +00:00
Rafael Espindola
7255090cd3 llvm-ar: Pad the symbol table to 4 bytes.
It looks like ld64 requires it. With this we seem to be able to bootstrap using
llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 19:48:06 +00:00
Matt Arsenault
0685a5c5ed AMDGPU/R600: Return correct chain when lowering loads
The other LowerLOAD should be returning the correct chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:47:03 +00:00
Sanjoy Das
4db527032a [IndVars] Try to use existing values in RewriteLoopExitValues.
Summary:
In RewriteLoopExitValues, before expanding out an SCEV expression using
SCEVExpander, try to see if an existing LLVM IR expression already
computes the value we're interested in.  If so use that existing
expression.

Apart from reducing IndVars' reliance on the rest of the compilation
pipeline, this also prevents IndVars from concluding some expressions as
"high cost" when they're not.  For instance,
`InductiveRangeCheckElimination` often emits code of the following form:

```
len = umin(len_A, len_B)

loop:
  ...
  if (i++ < len)
    goto loop

outside_loop:
    use(i)
```

`SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`,
since it thinks the value of `i` on loop exit, `len`, is a high cost
expansion since it contains an `umax` in it.  With this change,
`IndVars` can see that it can re-use `len` instead of creating a new
expression to compute `umin(len_A, len_B)`.

I considered putting this cleverness in `SCEVExpander`, but I was
worried that it may then have a deterimental effect on other passes
that use it.  So I decided it was better to just do this in the one
place where it seems like an obviously good idea, with the intent of
generalizing later if needed.

Reviewers: atrick, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10782

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241838 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:46:12 +00:00
Reid Kleckner
5574399e37 Remove dead code from old 64-bit SEH lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:46:39 +00:00
Pat Gavlin
db5a82b861 Allow {e,r}bp as the target of {read,write}_register.
This patch allows the read_register and write_register intrinsics to
read/write the RBP/EBP registers on X86 iff the targeted register is
the frame pointer for the containing function.

Differential Revision: http://reviews.llvm.org/D10977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241827 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:40:29 +00:00
Sanjay Patel
dc219dddde fix an invisible bug when combining repeated FP divisors
This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG:
r237046 ( http://reviews.llvm.org/rL237046 ):

1. When replacing a division node, it's not enough to RAUW.
   We should call CombineTo() to delete dead nodes and combine again.
2. Because we are changing the DAG, we can't return an empty SDValue
   after the transform. As the code comments say:

    Visitation implementation - Implement dag node combining for different node types.
    The semantics are as follows: Return Value:
      SDValue.getNode() == 0 - No change was made
      SDValue.getNode() == N - N was replaced, is dead and has been handled.
      otherwise - N should be replaced by the returned Operand.

The new test case shows no difference with or without this patch, but it will crash if
we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt.

Differential Revision: http://reviews.llvm.org/D9893



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2015-07-09 17:28:37 +00:00
Juergen Ributzka
c014920a89 [StackMap] Use lambdas to specify the sort and erase conditions. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241823 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:15 +00:00
Juergen Ributzka
fd5ef9d20c [StackMap] Rename variables to be more consistent. NFC.
Rename a few variables and use auto for long iterator names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241822 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:11 +00:00
Juergen Ributzka
9ba87b84ab [StackMaps] Use emplace_back when possible. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241821 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:08 +00:00
Tom Stellard
2b2d86178c AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use
This is convered by existing testcases and will be exposed by a future
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:36 +00:00
Tom Stellard
e05910e677 AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()
No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:27 +00:00
Rafael Espindola
a55816b3fc Basic support for BSD symbol tables in archives.
This could be optimized and for now we only produce __.SYMDEF
and not "__.SYMDEF SORTED".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241814 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:56:23 +00:00
Krzysztof Parzyszek
8e78dfcf23 [Hexagon] Add missing preamble to a source file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:40:25 +00:00
Rafael Espindola
f336caf392 Remove redundant variable. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241810 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:24:39 +00:00
Silviu Baranga
f283cd9acf Don't rely on the DepCands iteration order when constructing checking pointer groups
Summary:
The checking pointer group construction algorithm relied on the iteration on DepCands.
We would need the same leaders across runs and the same iteration order over the underlying std::set for determinism.

This changes the algorithm to process the pointers in the order in which they were added to the runtime check, which is deterministic.
We need to update the tests, since the order in which pointers appear has changed.

No new tests were added, since it is impossible to test for non-determinism.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11064

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241809 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:18:25 +00:00
Rafael Espindola
3696927846 Add a helper to printing BE of LE depending on the format.
The gnu ar format uses BE numbers. The BSD one uses LE. Add a helper for one or the
other. NFC for now, just removes some noise from the following patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241808 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:13:41 +00:00
Mehdi Amini
cdc323b2b7 Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT user
A documentation for this function would be nice by the way.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241807 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:12:23 +00:00
Pawel Bylica
dbbfabaf01 Reapply fixed r241790: Fix shift legalization and lowering for big constants.
Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.

Reviewers: nadav, majnemer, sanjoy, RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241806 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:58:04 +00:00
Rafael Espindola
56240eaf73 Extract printBSDMemberHeader.
It will get another use in the following patch. Also rename the other helper to
printGNUSmallMemberHeader for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241805 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:54:12 +00:00
Krzysztof Parzyszek
b13f72aa2d [Hexagon] Add support for atomic RMW operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241804 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:51:21 +00:00
Arnaud A. de Grandmaison
86d3dfce62 [AArch64] Select SBFIZ or UBFIZ instead of left + right shifts
And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241803 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:33:38 +00:00
Scott Douglass
0e714c7efa [ARM] Thumb1 3 to 2 operand convertion for commutative operations
Differential Revision: http://reviews.llvm.org/D11057

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241802 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:55 +00:00
Scott Douglass
7b8defda79 [ARM] Don't be overzealous converting Thumb1 3 to 2 operands
Differential Revision: http://reviews.llvm.org/D11056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241801 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:48 +00:00
Scott Douglass
3ca1884ba8 [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2
Differential Revision: http://reviews.llvm.org/D11055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241800 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:41 +00:00
Scott Douglass
ab17c04abe [ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc)
Also adds some test cases.

Differential Revision: http://reviews.llvm.org/D11054

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241799 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:34 +00:00
Renato Golin
86b4ed2fc4 Add support for nest attribute to AArch64 backend
The nest attribute is currently supported on the x86 (32-bit) and x86-64
backends, but not on ARM (32-bit) or AArch64. This patch adds support for
nest to the AArch64 backend.

Register x18 is used by GCC for this purpose and hence is used here.
As discussed on the GCC mailing list the register choice is an ABI issue
and so choosing the same register as GCC means __builtin_call_with_static_chain
is compatible.

Patch by Stephen Cross.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 10:18:02 +00:00
Tamas Berghammer
6055ca7bf4 Add getSizeInBits function to the APFloat class
The newly added function returns the size of the specified floating
point semantics in bits.

Differential revision: http://reviews.llvm.org/D8413

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2015-07-09 10:13:39 +00:00
Pawel Bylica
b0205f5937 Revert r241790: Fix shift legalization and lowering for big constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241792 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 09:50:54 +00:00
Pawel Bylica
71386b0e04 Fix shift legalization and lowering for big constants.
Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.

Reviewers: nadav, majnemer, sanjoy, RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241790 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 08:01:36 +00:00
Elena Demikhovsky
43afab3bdb Extended syntax of vector version of getelementptr instruction.
The justification of this change is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/082989.html

According to the current GEP syntax, vector GEP requires that each index must be a vector with the same number of elements.

%A = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets

In this implementation I let each index be or vector or scalar. All vector indices must have the same number of elements. The scalar value will mean the splat vector value.

(1) %A = getelementptr i8, i8* %ptr, <4 x i64> %offsets
or
(2) %A = getelementptr i8, <4 x i8*> %ptrs, i64 %offset

In all cases the %A type is <4 x i8*>

In the case (2) we add the same offset to all pointers.

The case (1) covers C[B[i]] case, when we have the same base C and different offsets B[i].

The documentation is updated.

http://reviews.llvm.org/D10496




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2015-07-09 07:42:48 +00:00
Adam Nemet
f959df643a [LAA] Fix line break in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241785 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 06:47:21 +00:00
Adam Nemet
ecb6a37111 [LAA] Rename IsRTNeeded to IsRTCheckAnalysisNeeded
The original name was too close to NeedRTCheck which is what the actual
memcheck analysis returns.  This flag, as the new name suggests, is only
used to whether to initiate that analysis.

Also a comment is added to answer one question I had about this code for
a long time.  Namely, how does this flag differ from
isDependencyCheckNeeded since they are seemingly set at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241784 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 06:47:18 +00:00
Mehdi Amini
dc4dccabf3 Remove getDataLayout() from TargetSelectionDAGInfo (had no users)
Summary:
Remove empty subclass in the process.

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren, ted

Differential Revision: http://reviews.llvm.org/D11045

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241780 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:10:08 +00:00
Mehdi Amini
691b2ff11e Remove getDataLayout() from TargetLowering
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11042

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241779 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:52 +00:00
Mehdi Amini
0e496c884c Make isLegalAddressingMode() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11040

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:40 +00:00
Mehdi Amini
027a9f4561 Make getByValTypeAlignment() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11038

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241777 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:28 +00:00
Mehdi Amini
29a2d864d4 Make TargetLowering::getShiftAmountTy() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11037

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241776 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:20 +00:00
Mehdi Amini
f29cc18dcb Make TargetLowering::getPointerTy() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11028

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241775 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:04 +00:00
Mehdi Amini
966e6ca1ac Make TargetTransformInfo keeping a reference to the Module DataLayout
DataLayout is no longer optional. It was initialized with or without
a DataLayout, and the DataLayout when supplied could have been the
one from the TargetMachine.

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11021

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241774 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:08:42 +00:00
Mehdi Amini
103bdfccee Redirect DataLayout from TargetMachine to Module in ComputeValueVTs()
Summary:
Avoid using the TargetMachine owned DataLayout and use the Module owned
one instead. This requires passing the DataLayout up the stack to
ComputeValueVTs().

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11019

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241773 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 01:57:34 +00:00
David Majnemer
b1d6ad18ba [CodeView] Add support for emitting column information
Column information is present in CodeView when the line table subsection
has bit 0 set to 1 in it's flags field.  The column information is
represented as a pair of 16-bit quantities: a starting and ending
column.  This information is present at the end of the chunk, after all
the line-PC pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241764 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 00:19:51 +00:00
Adam Nemet
f7f4697e3c [LAA] Fix misleading use of word 'consecutive'
Fix some places where the word consecutive is used but the code really
means constant-stride (i.e. not just unit stride).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241763 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 00:03:22 +00:00
Alex Lorenz
5faf25b798 MIR Serialization: Serialize the 'undef' register machine operand flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241762 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 23:58:31 +00:00
Sanjay Patel
c1c43c15cc [SLPVectorizer] Try different vectorization factors for store chains
...and set max vector register size based on target 

This patch is based on discussion on the llvmdev mailing list:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-July/087405.html

and also solves:
https://llvm.org/bugs/show_bug.cgi?id=17170

Several FIXME/TODO items are noted in comments as potential improvements.

Differential Revision: http://reviews.llvm.org/D10950



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241760 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 23:40:55 +00:00
Matthias Braun
6e999b0a30 RegisterPressure: Add PressureDiff::dump()
Also display the pressure diff in the case of a
getMaxUpwardPressureDelta() verify failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241759 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 23:40:27 +00:00
Adam Nemet
7a6f54545f [LAA] Revert a small part of r239295
This commit ([LAA] Fix estimation of number of memchecks) regressed the
logic a bit.  We shouldn't quit the analysis if we encounter a pointer
without known bounds *unless* we actually need to emit a memcheck for
it.

The original code was using NumComparisons which is now computed
differently.  Instead I compute NeedRTCheck from NumReadPtrChecks and
NumWritePtrChecks.

As side note, I find the separation of NeedRTCheck and CanDoRT
confusing, so I will try to merge them in a follow-up patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241756 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:58:48 +00:00
Juergen Ributzka
9a39681fd9 Run clang-format before making changes to StackMaps. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241754 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:42:09 +00:00
Sanjay Patel
f769239c19 [x86] enable machine combiner reassociations for scalar single-precision multiplies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241752 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:35:20 +00:00
Rafael Espindola
a04933edc1 Don't reject an archive with just a symbol table.
It is pretty unambiguous how to interpret it and gnu ar accepts it too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241750 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:27:54 +00:00
Rafael Espindola
bf4296f2c0 Disallow Archive::child_iterator that don't point to an archive.
NFC, just less error prone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241747 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:15:07 +00:00
Michael Zolotukhin
5ebb47fa90 [LoopVectorizer] Rename BypassBlock to VectorPH, and CheckBlock to NewVectorPH. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241742 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:48:03 +00:00
Michael Zolotukhin
c196e8f18b [LoopVectorizer] Restructurize code for emitting RT checks. NFCI.
Place all code corresponding to a run-time check in one place.
Previously we generated some code, then proceeded to a next check, then
finished the code for the first check (like splitting blocks and
generating branches). Now the code for generating a check is
self-contained.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241741 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:47:59 +00:00
Michael Zolotukhin
f26da26d05 [LoopVectorizer] Remove redundant variables PastOverflowCheck and OverflowCheckAnchor. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241740 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:47:56 +00:00
Michael Zolotukhin
ca6e363f1d [LoopVectorizer] Move some code around to ease further refactoring. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241739 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:47:53 +00:00
Michael Zolotukhin
a8e8640a65 [LoopVectorizer] Remove redundant variable LastBypassBlock. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241738 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:47:47 +00:00
Alex Lorenz
f67f2c25fe MIR Parser: Remove redundant TODO comment. NFC.
This TODO comment has been redundant since r240474.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241737 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:30:21 +00:00
Alex Lorenz
03dcd3c6ef MIR Serialization: Serialize the 'killed' register machine operand flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241734 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:23:34 +00:00
Diego Novillo
afab5f8c17 Add missing dependency to Hexagon target.
A recent patch added calls to isInstructionTriviallyDead without the
corresponding dependency on TransformUtils.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241731 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:13:37 +00:00
Rafael Espindola
576604b51b Use a raw_svector_ostream and simplify a loop. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241727 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:07:18 +00:00
Reid Kleckner
f8d3677531 [Win64] Only treat some functions as having the Win64 convention
All the usual X86 target-specific conventions are collapsed to the
normal Win64 convention, but the custom conventions like GHC and webkit
should not be.

Previously we would assume that the caller allocated 32 bytes of shadow
space for us, which is not how webkit_jscc or other custom conventions
are supposed to work.

Based on a patch by peavo@outlook.com.

Fixes PR24051.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241725 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:03:47 +00:00
Rafael Espindola
b13e877e27 Start adding support for writing archives in BSD format.
No support for the symbol table yet (but will hopefully add it today).
We always use the long filename format so that we can align the member,
which is an advantage of the BSD format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241721 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 20:47:32 +00:00
Alex Lorenz
31512fe6ce MIR Parser: Use source locations for MBB naming errors.
This commit changes the type of the field 'Name' in the struct
'yaml::MachineBasicBlock' from 'std::string' to 'yaml::StringValue'. This change
allows the MIR parser to report errors related to the MBB name with the proper
source locations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241718 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 20:22:20 +00:00
Sanjay Patel
ea64a51108 early exits -> less indenting; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241716 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 19:32:39 +00:00
Krzysztof Parzyszek
a307401165 [Hexagon] Implement commoning of GetElementPtr instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241714 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 19:22:28 +00:00
Peter Collingbourne
c783eb28f7 LibDriver: Fix output path inference.
The inferred output file name is based on the first input file, not the
first one with extension .obj. The output file was also being written to
the wrong directory; it needs to be written to whichever directory on the
libpath it was found in. This change fixes both issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241710 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 19:00:46 +00:00
Adam Nemet
b089d62c9a [LAA] Add missing debug output after r239285
r239285 ([LoopAccessAnalysis] Teach LAA to check the memory dependence
between strided accesses.) introduced a new case under
MemoryDepChecker::isDependent.  We normally have debug output for each
case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241707 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 18:47:38 +00:00
Reid Kleckner
f0999f3b02 [SEH] Ensure that empty __except blocks have their own BB
The 32-bit lowering assumed that WinEHPrepare had this invariant.
WinEHPrepare did it for C++, but not SEH. The result was that we would
insert calls to llvm.x86.seh.restoreframe in normal basic blocks, which
corrupted the frame pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241699 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 18:08:52 +00:00
Duncan P. N. Exon Smith
dfcac4b07a MC: Constify MCSubtargetInfo in getDeprecationInfo(), NFC
There's no reason to be able to mutate `MCSubtargetInfo` in
`getDeprecationInfo()`.  Constify the reference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241693 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 17:30:55 +00:00
Rafael Espindola
4ea795b15a Inline function into only use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241692 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 17:26:24 +00:00
Rafael Espindola
9ff2cd5417 Add a helper function to reduce a bit of code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241691 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 17:08:26 +00:00
Eli Bendersky
e933e5bd08 Cosmetic cleanups - NFC
Remove commented lines, trailing whitespace, etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241687 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 16:33:21 +00:00
James Y Knight
8eb1aaac9c [SPARC] Cleanup handling of the Y/ASR registers.
- Implement copying ASR to/from GPR regs.
- Mark ASRs as non-allocatable, so it won't try to arbitrarily use
  them inappropriately.
- Instead of inserting explicit WRASR/RDASR nodes in the MUL/DIV
  routines, just do normal register copies.
- Also...mark div as using Y, not just writing it.

Added a test case with some code which previously died with an
assertion failure (with -O0), or produced wrong code (otherwise).

(Third time's the charm?)

Differential Revision: http://reviews.llvm.org/D10401

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241686 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 16:25:12 +00:00
Rafael Espindola
cf8f6a296f Use a range loop. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241685 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 16:16:15 +00:00
Krzysztof Parzyszek
e7f45f66a7 [Hexagon] Generate "insert" instructions more aggressively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:47:34 +00:00
Krzysztof Parzyszek
5d447e9c2a Revert 241681: causes Windows builds to fail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241682 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:34:13 +00:00
Krzysztof Parzyszek
ea2273d00c [Hexagon] Generate "insert" instructions more aggressively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241681 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:22:27 +00:00
Silviu Baranga
8bde857088 [LAA] Merge memchecks for accesses separated by a constant offset
Summary:
Often filter-like loops will do memory accesses that are
separated by constant offsets. In these cases it is
common that we will exceed the threshold for the
allowable number of checks.

However, it should be possible to merge such checks,
sice a check of any interval againt two other intervals separated
by a constant offset (a,b), (a+c, b+c) will be equivalent with
a check againt (a, b+c), as long as (a,b) and (a+c, b+c) overlap.
Assuming the loop will be executed for a sufficient number of
iterations, this will be true. If not true, checking against
(a, b+c) is still safe (although not equivalent).

As long as there are no dependencies between two accesses,
we can merge their checks into a single one. We use this
technique to construct groups of accesses, and then check
the intervals associated with the groups instead of
checking the accesses directly.

Reviewers: anemet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10386

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241673 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 09:16:33 +00:00
Simon Pilgrim
796a06d4eb [X86][SSE] Added (V)ROUNDSD + (V)ROUNDSS stack folding support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241671 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 08:07:57 +00:00
Karthik Bhat
d9dffa6b3c Allow constfolding of llvm.sin.* and llvm.cos.* intrinsics
This patch const folds llvm.sin.* and llvm.cos.* intrinsics whenever feasible.

Differential Revision: http://reviews.llvm.org/D10836



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241665 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 03:55:47 +00:00
Mehdi Amini
7bcdaa6978 Remove IsLittleEndian from TargetLowering and redirect to DataLayout
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11017

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241655 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 01:00:38 +00:00
Mehdi Amini
564bfad782 Redirect DataLayout from TargetMachine to Module in SjLjEHPrepare
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11009

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241654 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 01:00:31 +00:00
Reid Kleckner
39ee70ca76 [WinEH] Make llvm.x86.seh.restoreframe work for stack realignment prologues
The incoming EBP value points to the end of a local stack allocation, so
we can use that to restore ESI, the base pointer. Once we do that, we
can use local stack allocations. If we know we need stack realignment,
spill the original frame pointer in the prologue and reload it after
restoring ESI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241648 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:45:58 +00:00
Mehdi Amini
c845b4d7be Redirect DataLayout from TargetMachine to Module in StackProtector
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11010

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241646 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:38:49 +00:00
Alex Lorenz
aa0d6db1e7 MIR Printer: Use a module slot tracker to print global address operands. NFC.
This commit adopts the 'ModuleSlotTracker' class, which was surfaced in r240842,
to print the global address operands. This change ensures that the slot tracker
won't have to be recreated every time a global address operand is printed,
making the MIR printing more efficient.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241645 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:27:53 +00:00
Reid Kleckner
4fe74caa61 [WinEH] Add localaddress intrinsic instead of using frameaddress
Clang uses this for SEH finally. The new intrinsic will produce the
right value when stack realignment is required.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241643 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:23:03 +00:00
Arnold Schwaighofer
39fe55270a Add more nvcasts
Tim Northover has told me that they can occur when the compiler cleverly
constructs constants - as demonstrated in the test case.

rdar://21703486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241641 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:13:18 +00:00
Dan Gohman
8ef6f1e24b [WebAssembly] Set the scheduling preference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 22:38:06 +00:00
Reid Kleckner
8f32e5f0d6 Rename llvm.frameescape and llvm.framerecover to localescape and localrecover
Summary:
Initially, these intrinsics seemed like part of a family of "frame"
related intrinsics, but now I think that's more confusing than helpful.
Initially, the LangRef specified that this would create a new kind of
allocation that would be allocated at a fixed offset from the frame
pointer (EBP/RBP). We ended up dropping that design, and leaving the
stack frame layout alone.

These intrinsics are really about sharing local stack allocations, not
frame pointers. I intend to go further and add an `llvm.localaddress()`
intrinsic that returns whatever register (EBP, ESI, ESP, RBX) is being
used to address locals, which should not be confused with the frame
pointer.

Naming suggestions at this point are welcome, I'm happy to re-run sed.

Reviewers: majnemer, nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11011

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241633 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 22:25:32 +00:00
Sanjay Patel
dd5fd545b1 fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241629 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 21:31:54 +00:00
Alex Lorenz
78bc2545c9 MIR Serialization: Serialize the 'dead' register machine operand flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241624 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 20:34:53 +00:00
Mehdi Amini
298a718c94 Redirect DataLayout from TargetMachine to Module in SelectionDAG
Summary:
SelectionDAG itself is not invoking directly the DataLayout in the
TargetMachine, but the "TargetLowering" class is still using it. I'll
address it in a following commit.

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11000

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241618 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 19:07:19 +00:00
David Majnemer
0148a4c854 Revert "Revert r241570, it caused PR24053"
This reverts commit r241602.  We had a latent bug in SCCP where we would
make a basic block empty and then proceed to ask questions about it's
terminator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241616 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:49:41 +00:00
Mehdi Amini
a77796487b Redirect DataLayout from TargetMachine to Module in GlobalMerge
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10987

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241615 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:49:25 +00:00
Mehdi Amini
d888ac430d Redirect DataLayout from TargetMachine to Module in CodeGen Prepare
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10986

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241614 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:45:17 +00:00
Mehdi Amini
26a2a4b4ed Redirect DataLayout from TargetMachine to Module in FastISel
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10985

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241613 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:39:02 +00:00
Arnold Schwaighofer
f869ca86f1 Add a pattern for a nvcast from v2f64 -> v4f32
Since the NvCast is generated by the selection process the concerns about
endianess and bit reversal don't apply.

rdar://21703486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:31:55 +00:00
Mehdi Amini
33c4d685e3 Redirect DataLayout from TargetMachine to Module in MachineFunction
Summary:
This change is part of a series of commits dedicated to have a
single DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10984

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241610 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:20:57 +00:00
Reid Kleckner
d0c71cfdf6 Use default member initializers to deduplicate code in X86MachineFunctionInfo, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241609 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:12:06 +00:00
Rafael Espindola
51652580f4 Fix the -DBUILD_SHARED_LIBS=ON build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241608 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 17:48:00 +00:00
Alex Lorenz
ddc6f0a433 MIR Parser: wrap 'MBBSlots' from the MI parsing functions in a struct. NFC.
This commit modifies the interface for the machine instruction parsing
functions by wrapping the parameter 'MBBSlots' in a new structure called
'PerFunctionMIParsingState'. This change is useful as in the future I will be
able to pass new parameters to the machine instruction parser just by modifying
the 'PerFunctionMIParsingState' structure instead of adding a new parameter to
each function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241607 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 17:46:43 +00:00
Rafael Espindola
7b7c81cd35 Delete UnknownAddress. It is a perfectly valid symbol value.
getSymbolValue now returns a value that in convenient for most callers:
* 0 for undefined
* symbol size for common symbols
* offset/address for symbols the rest

Code that needs something more specific can check getSymbolFlags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241605 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 17:12:59 +00:00
Rafael Espindola
9327084f92 Simplify by passing in the section of the symbol. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241603 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 16:45:55 +00:00
Nico Weber
1a2abd4a90 Revert r241570, it caused PR24053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241602 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 16:42:50 +00:00
Krzysztof Parzyszek
70bb40bd17 [Hexagon] Fix unused variable warnings in NDEBUG build caused by r241595
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241600 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 16:02:11 +00:00
Reid Kleckner
db38d7657a [WinEH] Add a report_fatal_error for 32-bit stack realignment
This type of prologue isn't supported yet. Implementing it should be a
matter of copying the adjusted incoming EBP into ESI (the base pointer)
instead of EBP.  The original EBP can be saved and restored from other
memory afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241597 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 15:47:29 +00:00