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294 Commits

Author SHA1 Message Date
Vladimir Medic
dadd1fba32 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:53:21 +00:00
Daniel Sanders
2fd3e67dc6 [mips][msa] Added load/store intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 12:04:29 +00:00
Akira Hatanaka
a796d90c0e [mips] Use ptr_rc to simplify definitions of base+index load/store instructions. 
Also, fix predicates.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 00:55:15 +00:00
Akira Hatanaka
bf19dba2d4 [mips] Clean up definitions of move word from/to coprocessor instructions. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189431 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 00:42:50 +00:00
Daniel Sanders
c9617b9a9d [mips][msa] Added bitconverts for vector types for big and little-endian 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189330 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-27 09:40:30 +00:00
Vladimir Medic
e4bf77a128 This patch implements trap instructions for mips. The test cases are added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 10:02:40 +00:00
Akira Hatanaka
a98a486ad1 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of 
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 21:08:22 +00:00
Akira Hatanaka
93877b3cbc [mips] Guard micromips instructions with predicate InMicroMips. Also, fix 
assembler predicate HasStdEnd so that it is false when the target is micromips.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 20:46:51 +00:00
Vladimir Medic
6f297afb7e This patch implements wait instruction for mips. Examples are added in test files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188537 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 10:17:03 +00:00
Jack Carter
e2a9376b1b [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) 
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-15 12:24:57 +00:00
Akira Hatanaka
cbaf6d0cc3 [mips] Rename HIRegs and LORegs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 00:47:08 +00:00
Jack Carter
3f70e908c3 [Mips][msa] Added initial MSA support. 
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-13 20:54:07 +00:00
Jack Carter
da0860f78e [Mips] Support for unaligned load/store microMips instructions 
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-13 20:19:16 +00:00
Vladimir Medic
809313970f This patch implements ei and di instructions for mips. Test cases are added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188176 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-12 13:07:23 +00:00
Akira Hatanaka
491d04969d [mips] Rename accumulator register classes and FP register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-08 21:54:26 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:08:38 +00:00
Akira Hatanaka
014096e4d5 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias' 
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 22:35:29 +00:00
Akira Hatanaka
a1fe9ef62e [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 22:20:40 +00:00
Akira Hatanaka
ddbdeefa28 [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also, 
remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 23:14:16 +00:00
Akira Hatanaka
52b7321a48 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 00:55:34 +00:00
Akira Hatanaka
8838da6587 [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that 
turns "bal" into "bgezal".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-30 20:24:24 +00:00
Akira Hatanaka
9758562aa7 [mips] Implement llvm.trap intrinsic. 
Patch by Sasa Stankovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187244 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 20:58:55 +00:00
Akira Hatanaka
0b92642767 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete 
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-22 18:52:22 +00:00
Vladimir Medic
16f385f90f Implement eret and deret(return from exception) instructions for Mips. Test examples are given. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186507 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-17 14:05:19 +00:00
Akira Hatanaka
ae24f7d3c6 [mips] Add instruction itinerary classes for mult, seb and slt instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186222 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-12 22:43:20 +00:00
Vladimir Medic
dd51a0c1e0 Add support for Mips break and syscall insructions. The corresponding test cases are added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186151 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-12 09:25:35 +00:00
Vladimir Medic
296c1534b4 Reverting commit r185999 due to buildboot failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186000 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-10 12:26:26 +00:00
Vladimir Medic
2ec5933eae Add support for Mips break and syscall insructions. The corresponding test cases are added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185999 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-10 10:18:10 +00:00
Akira Hatanaka
a66aacf6d7 [mips] Add new InstrItinClasses for move from/to coprocessor instructions and 
floating point loads and stores.

No changes in functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-02 00:00:02 +00:00
Akira Hatanaka
5112243aec [mips] Reverse the order of source operands of shift and rotate instructions that 
have three register operands.

No intended functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-01 20:39:53 +00:00
Akira Hatanaka
8270e68c56 [mips] brcond + setgt/setugt instruction selection patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 19:49:55 +00:00
Akira Hatanaka
1d4d32398d [mips] Add instruction selection patterns for blez and bgez. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 17:13:47 +00:00
Akira Hatanaka
1aeb13bd9c [mips] Add (setne $lhs, 0) instruction selection pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 18:18:07 +00:00
Akira Hatanaka
f894199a14 [mips] Trap on integer division by zero. 
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 18:07:43 +00:00
Jack Carter
e351865b65 Mips assembler: Add TwoOperandConstraint definitions 
This patch removes alias definition for addiu $rs,$imm 
and instead uses the TwoOperandAliasConstraint field in 
the ArithLogicI instruction class. 

This way all instructions that inherit ArithLogicI class 
have the same macro defined. 

The usage examples are added to test files.

Patch by Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182048 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 20:24:27 +00:00
Jack Carter
d761004bfd Mips td file formatting: white space and long lines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182047 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 20:08:49 +00:00
Jack Carter
3209baefd4 Mips assembler: Add branch macro definitions 
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm

The corresponding test cases are added.

Patch by Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 19:40:19 +00:00
Jack Carter
f4a1377322 Mips assembler: Assembler macro ADDIU $rs,imm 
This patch adds alias for addiu instruction which enables following syntax:

    addiu $rs,imm

The macro is translated as:

    addiu $rs,$rs,imm


Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-13 20:26:46 +00:00
Akira Hatanaka
b637b9f89e [mips] Add instruction selection pattern for (seteq $LHS, 0). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181459 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-08 19:38:04 +00:00
Akira Hatanaka
c147c1b994 [mips] Fix handling of instructions which copy to/from accumulator registers. 
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 23:22:09 +00:00
Akira Hatanaka
089741479b [mips] Add definitions of micromips load and store instructions. 
Patch by Zoran Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180241 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-25 01:21:25 +00:00
Akira Hatanaka
385de77303 [mips] Add definitions of micromips shift instructions. 
Patch by Zoran Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-25 01:11:15 +00:00
Akira Hatanaka
f530aff9de [mips] First patch which adds support for micromips. 
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 19:03:11 +00:00
Akira Hatanaka
8d99ec5748 [mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change 
operand type to uimm16.

Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 18:47:40 +00:00
Akira Hatanaka
3d60241c3e [mips] Reapply r179420 and r179421. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-13 00:55:41 +00:00
Akira Hatanaka
d35d5bdfc4 Revert r179420 and r179421. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 22:40:07 +00:00
Akira Hatanaka
6d224459f4 [mips] Instruction selection patterns for carry-setting and using add 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 22:24:52 +00:00
Akira Hatanaka
fd2cd0db97 [mips] Add patterns for DSP indexed load instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-30 02:14:45 +00:00
Akira Hatanaka
175f0fd99a [mips] Define reg+imm load/store pattern templates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-30 02:01:48 +00:00
Akira Hatanaka
f5926fd844 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions. 
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-30 01:36:35 +00:00