Eli Friedman
ca072a3977
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 02:07:20 +00:00
Chad Rosier
a860b189e4
Add support for lowering fneg when AVX is enabled.
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rdar://10566486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 01:02:25 +00:00
Pete Cooper
4e5a1ab10b
Added InstCombine for "select cond, ~cond, x" type patterns
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These can be reduced to "~cond & x" or "~cond | x"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 00:56:45 +00:00
Eli Friedman
7d1ff37118
Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 00:50:34 +00:00
Dan Gohman
f042660197
Move Instruction::isSafeToSpeculativelyExecute out of VMCore and
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into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146610 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:49:11 +00:00
Jim Grosbach
9b1b390288
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:25:46 +00:00
Devang Patel
5211134fbd
Do not sink instruction, if it is not profitable.
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On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.
Radar 10266272.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146604 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:20:38 +00:00
Kevin Enderby
c3fc3136a1
Improve the implementation of .incbin directive by replacing a loop by using
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getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 22:34:45 +00:00
Andrew Trick
19154f4576
LSR: Fold redundant bitcasts on-the-fly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 22:07:19 +00:00
Jim Grosbach
ec04a3f8db
ARM NEON fix alignment encoding for VST2 w/ writeback.
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Add tests for w/ writeback instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:49:24 +00:00
Kevin Enderby
c55accaddb
Add the .incbin directive which takes the binary data from a file and emits
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it to the streamer. rdar://10383898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:47:48 +00:00
Jim Grosbach
e90ac9bce9
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
Stepan Dyatkovskiy
ac12ef4ad2
Fix for bug #11429 : Wrong behaviour for switches. Small improvement for code size heuristics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:19:17 +00:00
Dan Gohman
f9096e450b
It turns out that clang does use pointer-to-function types to
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point to ARC-managed pointers sometimes. This fixes rdar://10551239.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:10:53 +00:00
Akira Hatanaka
3faac0a78c
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
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emission is not supported yet, but a patch that adds the support should follow
soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 18:26:41 +00:00
Jim Grosbach
8d11c6349f
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
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When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:30:24 +00:00
Jim Grosbach
a39cda7aff
ARM assembler support for the target-specific .req directive.
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rdar://10549683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:16:11 +00:00
Evan Cheng
ddfd1377d2
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
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to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:11:42 +00:00
Chad Rosier
8f644259dc
Add newline at EOF.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146538 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 01:34:39 +00:00
Jim Grosbach
863d2af947
Thumb2 assembler aliases for "mov(shifted register)"
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rdar://10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1
ARM LDM/STM system instruction variants.
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rdar://10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:48:29 +00:00
Jim Grosbach
0da6e867cf
Test for 146516
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:06:59 +00:00
Jim Grosbach
55b02f28c1
ARM thumb2 parsing of "rsb rd, rn, #0 ".
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rdar://10549741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:50:38 +00:00
Jim Grosbach
0f293de207
ARM NEON two-operand aliases for VQDMULH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:40:37 +00:00
Jim Grosbach
e91e7bcadc
ARM pre-UAL NEG mnemonic for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:23:22 +00:00
Chad Rosier
8a9bce978f
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
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load and then move the result from a GPR to a FPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 19:22:14 +00:00
Akira Hatanaka
d1472e8657
Add test/MC/Mips/dg.exp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 04:12:49 +00:00
Akira Hatanaka
692be5491a
Move direct object emitter test to directory test/MC/Mips. Rename it to
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elf-relsym.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 03:50:34 +00:00
Akira Hatanaka
f3315cf65f
Relocation against a symbol, instead of against section. We had some extreme
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test cases where there were a lot of relocations applied relative to a large
rodata section. Gas would create a symbol for each of these whereas we would
be relative to the beginning of the rodata section. This change mimics what
gas does.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 02:27:40 +00:00
Nick Lewycky
5a3d4c9830
Don't rely on a particular version string for llvm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 00:34:14 +00:00
Tony Linthicum
781907b2b8
Temporarily disable Hexagon tests. They are failing on OS X
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 00:33:45 +00:00
Akira Hatanaka
dcfc2eaf62
Test case for r146432 by Jack Carter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 22:41:39 +00:00
Bob Wilson
9cd2b9562d
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
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These modifiers simply select either the low or high D subregister of a Neon
Q register. I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146417 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 21:45:15 +00:00
Tony Linthicum
b4b54153ad
Hexagon backend support
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 21:14:40 +00:00
Joerg Sonnenberger
127a669d09
Only replace fwrite with fputc, if the return value is unused.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 20:18:31 +00:00
Jan Sjödin
37e7ecf52b
XOP instructions and encoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:37:49 +00:00
Roman Divacky
a0c17a495b
Add support for gnu_indirect_function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 17:34:04 +00:00
Chandler Carruth
ddbc274169
Manually upgrade the test suite to specify the flag to cttz and ctlz.
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I followed three heuristics for deciding whether to set 'true' or
'false':
- Everything target independent got 'true' as that is the expected
common output of the GCC builtins.
- If the target arch only has one way of implementing this operation,
set the flag in the way that exercises the most of codegen. For most
architectures this is also the likely path from a GCC builtin, with
'true' being set. It will (eventually) require lowering away that
difference, and then lowering to the architecture's operation.
- Otherwise, set the flag differently dependending on which target
operation should be tested.
Let me know if anyone has any issue with this pattern or would like
specific tests of another form. This should allow the x86 codegen to
just iteratively improve as I teach the backend how to differentiate
between the two forms, and everything else should remain exactly the
same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 11:59:10 +00:00
Chandler Carruth
2106badea3
Add an explicit test of the auto-upgrade functionality for the new
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intrinsic syntax.
Now that this is explicitly covered, I plan to upgrade the existing test
suite to use an explicit immediate. Note that I plan to specify 'true'
in most places rather than the auto-upgraded value as that is the far
more common value to end up here as that is the value coming from GCC's
builtins. The only place I'm likely to put a 'false' in is when testing
x86 which actually has different instructions for the two variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146369 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 11:23:11 +00:00
Chandler Carruth
c4eab904c9
Teach the verifier to reject all non-constant arguments to the second
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argument of the cttz and ctlz intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 04:36:02 +00:00
Stepan Dyatkovskiy
3e0dc0606a
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11 14:35:48 +00:00
Chandler Carruth
59164b731b
Don't assume things about the exact details of the LLVM version number,
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such as what VCS information is attached.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 21:40:31 +00:00
Chad Rosier
2baabf0374
Revert associate SelectInsertValue test as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 21:34:28 +00:00
Chad Rosier
d440f678fb
Revert r146322 to appease buildbots. Original commit message:
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Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 19:55:03 +00:00
Stepan Dyatkovskiy
8c0b807e8f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 08:42:24 +00:00
Hal Finkel
fed4d19edd
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 04:50:53 +00:00
Rafael Espindola
f3aefb56de
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
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does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 02:28:43 +00:00
Eli Friedman
effab8fa24
Splats can contain undef's; make sure to handle them correctly. PR11526.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 23:54:42 +00:00
Jim Grosbach
840bf7eda7
ARM assembly aliases for BIC<-->AND (immediate).
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When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:02:17 +00:00
Evan Cheng
b3e6c70c84
Update test to something more sensible.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146282 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:54:10 +00:00
Jim Grosbach
a4e3c7fc4b
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:28:25 +00:00
Chad Rosier
cd462d055f
[fast-isel] Add support for selecting insertvalue.
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rdar://10530851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 20:09:54 +00:00
Rafael Espindola
3c68acd202
Handle reloc_signed_4byte in here. Not doing so was a regression from my
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previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:57:29 +00:00
Kevin Enderby
94c2e85bea
The second part of support for generating dwarf for assembly source files. This
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generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146262 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:09:40 +00:00
Benjamin Kramer
b653397dcd
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 15:44:03 +00:00
Andrew Trick
5d73448bb7
Add -unroll-runtime for unrolling loops with run-time trip counts.
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Patch by Brendon Cahoon!
This extends the existing LoopUnroll and LoopUnrollPass. Brendon
measured no regressions in the llvm test suite with -unroll-runtime
enabled. This implementation works by using the existing loop
unrolling code to unroll the loop by a power-of-two (default 8). It
generates an if-then-else sequence of code prior to the loop to
execute the extra iterations before entering the unrolled loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 06:19:40 +00:00
Evan Cheng
9c181a92d8
Forgot setting -march.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 06:15:00 +00:00
Rafael Espindola
1d5969d839
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
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symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 03:03:58 +00:00
Akira Hatanaka
0dca9456c5
jalr should use t9 ($25) for indirect calls regardless of the relocation model
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specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:45:12 +00:00
Eli Friedman
2dd0353fec
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146219 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:16:26 +00:00
Nick Lewycky
c9b98ad7a7
Fix infinite loop in DSE when deleting a free in a reachable loop that's also
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trivially infinite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:36:35 +00:00
Evan Cheng
e955726a0e
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146196 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:30:45 +00:00
Jim Grosbach
8759c3f548
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:19:04 +00:00
Jim Grosbach
6b044c2609
ARM VSHR implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:06:06 +00:00
Evan Cheng
13d2ba34f2
Add various missing AVX patterns which was causing crashes. Sadly, the generated
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code looks pretty bad compared to SSE.
rdar://10538793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:05:28 +00:00
Jim Grosbach
318df74104
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:04:40 +00:00
Jim Grosbach
120313435d
ARM VSUB implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:56:26 +00:00
Jim Grosbach
beef39ab63
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:53:19 +00:00
Jim Grosbach
9e7b42a40e
ARM VQADD implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389
ARM a few more VMUL implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:42:35 +00:00
Owen Anderson
4a4fdf3476
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:32:14 +00:00
Evan Cheng
e9c1e07c5f
Add test for r146163.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:21:39 +00:00
Daniel Dunbar
3b0887e291
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
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sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 17:32:18 +00:00
NAKAMURA Takumi
e4472726b5
test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 15:24:09 +00:00
Nadav Rotem
44bac7cd65
Fix a bug in the integer-promotion of bitcast operations on vector types.
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We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 13:10:01 +00:00
Stepan Dyatkovskiy
72590c9738
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 07:55:03 +00:00
Jim Grosbach
730fe6c1b6
ARM NEON two-operand aliases for VSHL(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:30:04 +00:00
Jim Grosbach
ff4cbb4c9a
ARM NEON two-operand aliases for VSHL(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:12:35 +00:00
Jim Grosbach
a44f2c4a28
ARM optional destination operand variants for VEXT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:43:47 +00:00
Jim Grosbach
71a0a2ec0b
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:41:54 +00:00
Jim Grosbach
3bc8a3d3af
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
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For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:40:58 +00:00
Akira Hatanaka
0a18cdc372
32 to 64-bit zext pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:14:41 +00:00
Jim Grosbach
9fa0a743e6
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f
ARM two-operand aliases for VADDW instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13
ARM two-operand aliases for VADD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:52:54 +00:00
Akira Hatanaka
2c78be01f6
64-bit WrapperPICPat patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:11:43 +00:00
Akira Hatanaka
7398bf01c2
Modify LowerFCOPYSIGN to handle Mips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:48:50 +00:00
Akira Hatanaka
4d0eb637f0
Fix 64-bit immediate patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:10:24 +00:00
Jim Grosbach
577b09155f
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:46:59 +00:00
Jim Grosbach
8524bca750
Thumb2 alias for long-form pop and friends.
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rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca
ARM support the .arm and .thumb directives for assembly mode switching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:51:15 +00:00
Jim Grosbach
d552a644be
Tidy up. Move MachO tests to MachO directory.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:50:28 +00:00
Eli Friedman
f91abd22be
Support vector bitcasts in the AsmPrinter. PR11495.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:50:54 +00:00
Eli Friedman
26323442d5
Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:11:56 +00:00
Hal Finkel
099730dfb7
delaying restore-cr changed assigned registers in some tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 20:55:46 +00:00
Hal Finkel
327ca3a753
add a test case that uses RESTORE_CR
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 20:55:41 +00:00
Justin Holewinski
4c7ffb6a7e
PTX: Continue to fix up the register mess.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:39:48 +00:00
Craig Topper
cb6bd11bd6
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 09:04:59 +00:00
NAKAMURA Takumi
18851edbc4
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
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FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 06:48:26 +00:00
Jim Grosbach
23261af193
ARM mode 'mul' operand ordering tweak.
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Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2
Thumb2: MUL two-operand form encoding operand order fix.
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Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:03:45 +00:00
Craig Topper
1ff73d7a67
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 04:59:07 +00:00
Jim Grosbach
df33e0d05e
Thumb2 encoding choice correction for PLD.
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Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
286ea03382
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
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MC/MachO assumes x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:56:05 +00:00
Andrew Trick
8a5d792944
LSR: prune undesirable formulae early.
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It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:13:31 +00:00
Chad Rosier
ed42c5f778
[arm-fast-isel] Doublewords only require word-alignment.
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rdar://10528060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
3e572ac2fb
Align ARM constant pool islands via their basic block.
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Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:43:02 +00:00
Jim Grosbach
d9a6e8978d
Fix ARM handling of tBcc branch relaxation.
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rdar://10069056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:08:19 +00:00
Chad Rosier
dce42b75dc
Probably not a good idea to convert a single vector load into a memcpy. We
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don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 00:19:08 +00:00
Chad Rosier
d8bd26ee24
Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio
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where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:37:00 +00:00
Jim Grosbach
713c70238c
Tweak ADDrr fix. Bad check for explicit .w
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:27:04 +00:00
Jim Grosbach
6e507c645d
Update tests for r145860. Add a few new ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:21:28 +00:00
Akira Hatanaka
d6bc5237d8
Add definitions of 64-bit extract and insert instrucions and make
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PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 21:26:34 +00:00
Jim Grosbach
da84786bee
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 21:06:26 +00:00
Akira Hatanaka
2bf08ec854
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
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O32 with relocation-model=pic too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 21:03:03 +00:00
Jim Grosbach
253ef7a779
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 20:29:59 +00:00
Hal Finkel
fef3f9aed3
Add test case - this input used to crash because of duplicate generation of SPILL_CRs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 17:55:22 +00:00
Hal Finkel
3fd0018af1
enable PPC register scavenging by default (update tests and remove some FIXMEs)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 17:55:17 +00:00
Hal Finkel
c4785181a1
remove wasted space for extra bit copies of CR2 subregs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 17:55:06 +00:00
NAKAMURA Takumi
27de2a54f3
test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 07:54:57 +00:00
Nadav Rotem
1608769abe
Add support for vectors of pointers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 06:29:09 +00:00
Anton Korobeynikov
0cb2a45cce
Emit the ctors in the proper order on ARM/EABI.
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Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
80b1ae9292
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
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AnalyzeBranch doesn't change the successor, just the order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 21:24:48 +00:00
Sanjoy Das
199ce33b3b
Check for stack space more intelligently.
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libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 09:32:07 +00:00
Sanjoy Das
40f8222e1e
Fix a bug in the x86-32 code generated for segmented stacks.
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Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 09:21:07 +00:00
Chad Rosier
9eff1e33f6
[arm-fast-isel] Unaligned stores of floats require special care.
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rdar://10510150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 02:21:57 +00:00
Pete Cooper
de2e27cc52
Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur
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Turns out long long + unsigned long long is unsigned. Doh!
Fixes http://llvm.org/bugs/show_bug.cgi?id=11455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 00:04:30 +00:00
Chad Rosier
24fbf2bf16
Add support for constant folding the pow intrinsic.
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rdar://10514247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 00:00:03 +00:00
Akira Hatanaka
99f50fb3ee
Test cases for 64-bit multiplication and division.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145717 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:31:36 +00:00
Akira Hatanaka
fa341d919f
Fix test cases to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:28:09 +00:00
Jim Grosbach
c4f0b309ee
ARM tests for VLD1 single lane w/ writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:03:52 +00:00
Chad Rosier
b74c865841
[arm-fast-isel] After promoting a function parameter be sure to update the
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argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 20:25:18 +00:00
Hal Finkel
427876757f
specify cpu for test to fix failure on some darwin systems with a g4+ cpu
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 19:38:17 +00:00
Jim Grosbach
dad2f8e7fb
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 18:52:30 +00:00
Craig Topper
138a5c66b9
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 07:16:01 +00:00
Hal Finkel
2457544630
adjust the instruction ordering in some PPC tests: changes due to postRA haz. rec.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 04:58:12 +00:00
Chad Rosier
aebc3aae3f
Prevent library calls from being folded if -fno-builtin has been specified.
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rdar://10500969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145639 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 22:14:50 +00:00
Pete Cooper
165695d261
Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145618 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 19:13:26 +00:00
Eric Christopher
7d5a61e975
For 64-bit the rest of the general regs are ok for the q constraint. Make
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sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 08:12:41 +00:00
Eli Friedman
522fb8cc01
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145573 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 04:49:21 +00:00
Pete Cooper
dbaad16959
Removed use of grep from test and moved it to be with other icmp tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145570 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 04:35:26 +00:00
Pete Cooper
65a6b57c33
Added instcombine pattern to spot comparing -val or val against 0.
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(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"
Fixes <rdar://problem/10482509>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 03:58:40 +00:00
Jan Sjödin
dd649e35e5
Support for encoding all FMA4 instructions and tablegen patterns for all
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remaining FMA4 instructions and intrinsics with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Eli Friedman
3dad610aaa
Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.
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<rdar://problem/10497732>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 21:54:15 +00:00
Jim Grosbach
e30171ba0c
Add some tests for all-lanes VLD1 parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 19:37:38 +00:00
Nadav Rotem
78647434ea
Add test arch to make it pass on non x86 targets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 17:34:28 +00:00
Nadav Rotem
f3993125b1
Add a tripple to the test
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 11:20:56 +00:00
Nadav Rotem
18197d7425
X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 10:13:37 +00:00