Dan Gohman
126a54f1fa
Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result
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is returned through a bitcast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137402 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 00:36:31 +00:00
Dan Gohman
a7f7db2ebd
Don't let arbitrary calls disrupt nested retain+release pairs if
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the retains and releases all use the same SSA pointer value.
Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 00:26:31 +00:00
Dan Gohman
d8e48c4821
Use an actual reverse-CFG reverse-postorder for the bottom-up traversal,
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rather than plain postorder, so that CFG constructs like single-exit loops
are reliably visited in a sensible order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137398 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 00:24:29 +00:00
Jakob Stoklund Olesen
9b7ff12dd1
Simplify the interference checking code a bit.
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This is possible now that we now longer provide an interface to iterate
the interference overlaps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 00:22:04 +00:00
Jim Grosbach
857e1a7b3f
ARM vector compare to zero instruction assembly parsing support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 23:51:13 +00:00
Andrew Trick
b1831c6640
Allow loop unrolling to get known trip counts from ScalarEvolution.
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SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.
This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 23:36:16 +00:00
Jakob Stoklund Olesen
8facc7def8
Remove the InterferenceResult class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:46:06 +00:00
Jakob Stoklund Olesen
fe026e1829
Eliminate the last use of InterferenceResult.
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The Query class now holds two iterators instead of an InterferenceResult
instance. The iterators are used as bookmarks for repeated
collectInterferingVRegs calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:46:04 +00:00
Akira Hatanaka
9029cf20e1
Enclose directive .cprestore with .set macro and nomacro to silence assembler
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warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:42:31 +00:00
Jim Grosbach
d30970fb6c
Remove no-longer-true comments. These are for the assembler, also.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:30:30 +00:00
Jim Grosbach
342ebd5f38
ARM STRT assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:18:00 +00:00
Owen Anderson
41ff834e91
Make the USAT16 operand decoder auto-generate-able.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:10:11 +00:00
Owen Anderson
adf2b094cb
Add another accidentally omitted predicate operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:08:38 +00:00
Owen Anderson
1fb6673bc2
Add missing predicate operand on SMLA and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:05:38 +00:00
Jim Grosbach
dd32ba337a
ARM load shifted register pre-index fix shift value asm parser encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:05:09 +00:00
Owen Anderson
796d6b7602
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137364 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:52:38 +00:00
Owen Anderson
05b0c9f41e
Making SEL decodings auto-generate-able.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:50:56 +00:00
Bruno Cardoso Lopes
ef8d6999f3
Add a dag combine to xform 256-bit shuffles into simple vector
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inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137362 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:50:44 +00:00
Jim Grosbach
89958d50c3
Tidy up comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137359 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:41:59 +00:00
Owen Anderson
cbfc044acd
Fix decoding support for STREXD and LDREXD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:34:58 +00:00
Jakob Stoklund Olesen
9942ba9c0e
Remove more dead code.
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collectInterferingVRegs will be the primary function for interference
checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:18:34 +00:00
Jim Grosbach
7b8f46cf9e
ARM STRH assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:17:22 +00:00
Dan Gohman
fa7eed1f8e
Fix typos in comments, and delete an unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:06:32 +00:00
Akira Hatanaka
1f8d822023
Add isIndirectBranch flag.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:05:37 +00:00
Jakob Stoklund Olesen
98985f959c
Privatize an unused part of the LiveIntervalUnion::Query interface.
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No clients are iterating over interference overlaps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:00:42 +00:00
Owen Anderson
508e1d3db5
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:47:56 +00:00
Jakob Stoklund Olesen
bb688cec09
Remove some dead code.
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The InterferenceResult iterator turned out to be less important than we
thought it would be. LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:41:41 +00:00
Jim Grosbach
45251b3707
Tidy up. Remove unused template parameter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:41:13 +00:00
Owen Anderson
9fe72bcd37
Improve operand validation for Thumb2 addressing modes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:40:40 +00:00
Jim Grosbach
14605d1a67
ARM STRD assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:28:23 +00:00
Andrew Trick
c12d9b9dfb
Fix for LoopInfo::updateUnloop. Remove subloop blocks from former
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ancestor loops.
I have a unit test that depends on scev-unroll, which unfortunately
isn't checked in. But I will check it in when I can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:27:32 +00:00
Owen Anderson
26d2f0ac91
Continue to tighten decoding by performing more operand validation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:21:46 +00:00
Jim Grosbach
ade7d00f5a
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:13:35 +00:00
Jim Grosbach
10348e70d5
ARM STRBT assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:04:56 +00:00
Jim Grosbach
548340c4bf
ARM STR(immediate) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:22:40 +00:00
Owen Anderson
71156a6e00
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes
59353b436a
Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:59:13 +00:00
Owen Anderson
2b7b238e84
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:55:42 +00:00
Owen Anderson
3dac0bec7e
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:41:59 +00:00
Benjamin Kramer
0fa5e053a9
Plug a memory leak.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:39:28 +00:00
Owen Anderson
ae0bc5deaa
Improve error checking in the new ARM disassembler. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:24:51 +00:00
Jim Grosbach
f6713916fb
ARM push of a single register encodes as pre-indexed STR.
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Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:07:11 +00:00
Andrew Trick
5c1ff1f2f2
Cleanup. Another thorough review by Nick!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 17:54:58 +00:00
Jim Grosbach
f8fce711e8
ARM pop of a single register encodes as post-indexed LDR.
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Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 17:35:48 +00:00
Nadav Rotem
6236f7f2b6
Add a comment, per Bruno's CR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 17:05:47 +00:00
Nadav Rotem
f80a894bf0
[AVX] When joining two XMM registers into a YMM register, make sure that the
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lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137310 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 16:49:36 +00:00
Nadav Rotem
5e742a3e1b
[AVX] If the data which is going to be saved is already in two XMM registers
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(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.
Before:
vinsertf128 $1, %xmm3, %ymm0, %ymm3
vinsertf128 $0, %xmm1, %ymm3, %ymm1
vmovaps %ymm1, 416(%rsp)
After:
vmovaps %xmm3, 416+16(%rsp)
vmovaps %xmm1, 416(%rsp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 16:41:21 +00:00
Chris Lattner
f4ea68fa5a
fix PR10605 / rdar://9930964 by adding a pretty scary missed check.
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It's somewhat surprising anything works without this. Before we would
compile the testcase into:
test: # @test
movl $4, 8(%rdi)
movl 8(%rdi), %eax
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
now we produce:
test: # @test
movl 8(%rdi), %eax
movl $4, 8(%rdi)
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes
b02c0ace20
Cleanup: Remove Int_ CVTSS2SI* forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 02:52:36 +00:00
Bruno Cardoso Lopes
5f1d8abf75
Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing
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infinite recursive calls in legalize. Fix PR10562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137296 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes
a5134a0ea3
Use the splat index to generate the desired shuffle. Otherwise we
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could only get undefs and the vector shuffle becomes an undef,
generating wrong code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 02:49:41 +00:00
Eli Friedman
586272d67c
Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).
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Fixes PR9693.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 01:48:05 +00:00
Devang Patel
5bc942cc3c
Stay within 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 23:58:09 +00:00
Jim Grosbach
59999264e6
ARM LDRT assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 23:43:54 +00:00
Jim Grosbach
e15defc56c
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 23:23:47 +00:00
Andrew Trick
fb62b8deb3
Reapplying r136844.
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An algorithm for incrementally updating LoopInfo within a
LoopPassManager. The incremental update should be extremely cheap in
most cases and can be used in places where it's not feasible to
regenerate the entire loop forest.
- "Unloop" is a node in the loop tree whose last backedge has been removed.
- Perform reverse dataflow on the block inside Unloop to propagate the
nearest loop from the block's successors.
- For reducible CFG, each block in unloop is visited exactly
once. This is because unloop no longer has a backedge and blocks
within subloops don't change parents.
- Immediate subloops are summarized by the nearest loop reachable from
their exits or exits within nested subloops.
- At completion the unloop blocks each have a new parent loop, and
each immediate subloop has a new parent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 23:22:57 +00:00
Jim Grosbach
623a454b0f
ARM LDRH(immediate) assembly parsing and encoding support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 22:42:16 +00:00
Jim Grosbach
251bf25e7e
ARM LDRD(register) assembly parsing and encoding.
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Add support for literal encoding of #-0 along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 21:56:18 +00:00
Devang Patel
b549bcfe6c
Distinguish between two copies of one inlined variable. Take 2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137253 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 21:50:54 +00:00
Devang Patel
c722c3d5ff
While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 21:25:34 +00:00
Devang Patel
9ce256421a
Revert unintentional parts of previous check-in.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 21:16:49 +00:00
Devang Patel
bf47fdb91c
Start using LexicalScopes utility. No intetional functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 20:55:27 +00:00
Jim Grosbach
53642c5335
Fix typo. Not quite sure how that slipped in there.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 20:49:18 +00:00
Jim Grosbach
2fd2b87ded
ARM LDRD(immediate) assembly parsing and encoding support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 20:29:19 +00:00
Nadav Rotem
614061bfb4
When performing a truncating store, it is sometimes possible to rearrange the
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data in-register prior to saving to memory. When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 19:30:14 +00:00
Devang Patel
103b8e653c
Provide utility to extract and use lexical scoping information from machine instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 19:04:06 +00:00
Owen Anderson
8533ebad6f
Add initial support for decoding NEON instructions in Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 19:01:10 +00:00
Andrew Trick
7cb3dcb927
Comments. Thanks for the spell check Nick!
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Also, my apologies for spoiling the autocomplete on SimplifyInstructions.cpp. I couldn't think of a better filename.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 18:07:05 +00:00
Bruno Cardoso Lopes
6ad251358e
The following X86 pattern is incorrect:
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def : Pat<(X86Movss VR128:$src1,
(bc_v4i32 (v2i64 (load addr:$src2)))),
(MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:45:17 +00:00
Eli Friedman
1cc5e38830
Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:39:11 +00:00
Owen Anderson
fd9085dca3
Tabs --> spaces.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:38:05 +00:00
Owen Anderson
10cbaab7b7
Cleanups based on Nick Lewycky's feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:36:48 +00:00
Owen Anderson
e66ef2d5f5
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:21:20 +00:00
Rafael Espindola
f5ade5d39a
Add support for the R and Q constraints.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 16:26:42 +00:00
Bob Wilson
21ab6c066d
Clarify a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 05:02:22 +00:00
Andrew Trick
39f40299a6
Invoke SimplifyIndVar when we partially unroll a loop. Fixes PR10534.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 04:29:49 +00:00
Andrew Trick
bddb7f8210
Cleanup. Make ScalarEvolution an explicit argument of the
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SimplifyIndVar utility since it is required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 04:22:26 +00:00
Andrew Trick
ea23daa446
SimplifyIndVar: make foldIVUser iterative to fold a chain of operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137199 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 04:01:31 +00:00
Benjamin Kramer
4a1a5eb95b
Update CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 03:51:58 +00:00
Andrew Trick
4b4bb71bcd
Added a SimplifyIndVar utility to simplify induction variable users
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based on ScalarEvolution without changing the induction variable phis.
This utility is the main tool of IndVarSimplifyPass, but the pass also
restructures induction variables in strange ways that are sensitive to
pass ordering. This provides a way for other loop passes to simplify
new uses of induction variables created during transformation. The
utility may be used by any pass that preserves ScalarEvolution. Soon
LoopUnroll will use it.
The net effect in this checkin is to cleanup the IndVarSimplify pass
by factoring out the SimplifyIndVar algorithm into a standalone utility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 03:46:27 +00:00
Andrew Trick
2d31ae3d9d
Cleanup. Added LoopBlocksDFS::perform for simple clients.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137195 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 01:59:05 +00:00
Bruno Cardoso Lopes
155a92a491
Fix a bug in vpermilps mask checking. Fix PR10560
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 01:54:17 +00:00
Andrew Trick
b1eede1281
Fix the LoopUnroller to handle nontrivial loops and partial unrolling.
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These are not individual bug fixes. I had to rewrite a good chunk of
the unroller to make it sane. I think it was getting lucky on trivial
completely unrolled loops with no early exits. I included some fairly
simple unit tests for partial unrolling. I didn't do much stress
testing, so it may not be perfect, but should be usable now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 00:28:10 +00:00
Owen Anderson
33e57515b1
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 00:03:03 +00:00
Jakob Stoklund Olesen
c66d36028b
Trim an unneeded header.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:49:21 +00:00
Jakob Stoklund Olesen
c70c2cafe1
Promote VMOVS to VMOVD when possible.
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On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
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vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:41:44 +00:00
Owen Anderson
de317f40f7
Tighten operand checking of register-shifted-register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:33:27 +00:00
Bruno Cardoso Lopes
d40aa24ebf
Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:27:13 +00:00
Owen Anderson
c36481c474
Tighten operand checking on memory barrier instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:25:42 +00:00
NAKAMURA Takumi
77c714027c
VMCore/BasicBlock.cpp: Don't assume BasicBlock::iterator might end with a non-PHInode Instruction in successors.
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Frontends(eg. clang) might pass incomplete form of IR, to step off the way beyond iterator end. In the case I had met, it took infinite loop due to meeting bogus PHInode.
Thanks to Jay Foad and John McCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:13:05 +00:00
NAKAMURA Takumi
8fc9b3db53
Fix whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:12:56 +00:00
Owen Anderson
35008c2f8d
Tighten operand checking on CPS instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:05:39 +00:00
Eli Friedman
21006d40ac
Representation of 'atomic load' and 'atomic store' in IR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:02:53 +00:00
Owen Anderson
51c9805c4b
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:48:45 +00:00
Bruno Cardoso Lopes
18deb04e9c
Add v16i16 and v32i8 store patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137166 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:39:53 +00:00
Chad Rosier
6ff9aa2aa7
Fix 80-column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:23:40 +00:00
Bruno Cardoso Lopes
cde4a1abd5
Use fp unpack instructions to unpack int types. Until we have AVX2, this
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is the best we can do for these patterns. This fix PR10554.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:18:37 +00:00
Eli Friedman
fc430a662f
Fix a couple ridiculous copy-paste errors. rdar://9914773 .
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:17:39 +00:00
Rafael Espindola
69cb216009
Add a C interface to PassManagerBuilder. It is missing the addExtension
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functionality since in the C api a pass is created and added to a pass
manager in a single call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:17:34 +00:00
Jim Grosbach
739b5576ad
Don't truncate MachO addresses.
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Assigned symbol addresses get truncated to 32-bits, even on 64-bit platforms.
That's obviously bogus.
For example,
.globl _foo
.equ _foo, 0x987654321ULL
rdar://9922863
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:12:37 +00:00