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948 Commits

Author SHA1 Message Date
Jim Grosbach
22378fd664 ARM assembly aliases for two-operand V[R]SHR instructions. 
rdar://11189467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-05 07:23:53 +00:00
Jim Grosbach
b657a90929 ARM assembly parsing for 'msr' plain 'cpsr' operand. 
Plain 'cpsr' is an alias for 'cpsr_fc'.

rdar://11153753

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-05 03:17:53 +00:00
Jim Grosbach
ad353c6303 ARM assembler should prefer non-aliases encoding of cmp. 
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-30 19:59:02 +00:00
Jim Grosbach
a45e3747e6 ARM encoding for VSWP got the second operand incorrect. 
Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-30 18:53:01 +00:00
Jim Grosbach
2d30d947ec ARM integrated assembler should encoding choice for add/sub imm. 
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.

rdar://11156277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-30 17:20:40 +00:00
Jim Grosbach
c0164f8608 ARM assembly parsing needs to be paranoid about negative immediates. 
Make sure to treat immediates as unsigned when doing relative comparisons.

rdar://11153621

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-30 16:31:31 +00:00
James Molloy
cb0809b82b Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch. 
Patch by Tim Northover!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-30 09:15:32 +00:00
Jim Grosbach
b22e70d835 ARM assembly 'cmp lr, #0' should not encode using 'cmn'. 
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.

rdar://11129224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-29 21:19:52 +00:00
Richard Barton
6e9d66c756 Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-28 10:18:11 +00:00
Eli Bendersky
cc85160672 Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 
* Removed test/lib/llvm.exp - it is no longer needed 
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
  left in the test suite so this code is no longer required. test/lit.cfg is
  now much shorter and clearer 
* Removed a lot of duplicate code in lit.local.cfg files that need access to
  the root configuration, by adding a "root" attribute to the TestingConfig
  object. This attribute is dynamically computed to provide the same
  information as was previously provided by the custom getRoot functions. 
* Documented the config.root attribute in docs/CommandGuide/lit.pod





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-25 09:02:19 +00:00
Kevin Enderby
9f2e160f7a Fix assembling ARM vst2 instructions with double-spaced registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 17:41:51 +00:00
Jim Grosbach
be7cf2b377 ARM ldm/stm register lists can be out of order. 
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.

rdar://11064740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 20:48:38 +00:00
Jim Grosbach
213d2e7dc3 ARM optional operand on MRC/MCR assembly instructions. 
rdar://11058464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 00:45:58 +00:00
Jim Grosbach
9426ac7b57 ARM vmrs system registers mvfr0 and mvfr1 handling. 
rdar://11058464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 00:27:18 +00:00
Jim Grosbach
b84ad4aa7d ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 21:34:14 +00:00
Kristof Beyls
8a6bcc3722 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 17:50:29 +00:00
Jim Grosbach
bc978a60d9 ARM vpush/vpop assembler mnemonics accept an optional size suffix. 
rdar://10988114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 23:16:31 +00:00
Jim Grosbach
7b25ecf6ad ARM BL/BLX instruction fixups should use relocations. 
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.

To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.

rdar://10927209

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-27 21:36:23 +00:00
Eli Bendersky
0f0c411079 Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed. 
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 06:28:33 +00:00
James Molloy
2d8955a77c Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends. 
Fixes PR11877



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-28 15:58:32 +00:00
James Molloy
34982576a4 Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. 
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 09:25:43 +00:00
Jim Grosbach
74423e32ce ARM assemly parsing and validation of IT instruction. 
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 19:52:01 +00:00
Jim Grosbach
a57a36abe7 NEON VLD4(all lanes) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 00:01:08 +00:00
Jim Grosbach
5e59f7e15e NEON VLD3(all lanes) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 23:47:04 +00:00
Jim Grosbach
88a54de799 NEON VST4(one lane) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 18:53:13 +00:00
Jim Grosbach
e983a134e7 NEON VLD4(one lane) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 18:37:25 +00:00
Jim Grosbach
1ac2060678 NEON Two-operand assembly aliases for VSRA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 17:55:36 +00:00
Jim Grosbach
5d9bad4098 Remove redundant test file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148820 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 17:55:32 +00:00
Jim Grosbach
5e497d3992 NEON Two-operand assembly aliases for VSLI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 17:49:15 +00:00
Jim Grosbach
d8ee0cc4e8 NEON Two-operand assembly aliases for VSRI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 17:46:58 +00:00
Jim Grosbach
28f1f9100f Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148817 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 17:46:54 +00:00
Jim Grosbach
539aab771f NEON VST4(multiple 4 element structures) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 00:58:13 +00:00
Jim Grosbach
8abe7e3364 NEON VLD4(multiple 4 element structures) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 00:43:17 +00:00
Jim Grosbach
4adb182342 NEON VST3(single element from one lane) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 00:07:41 +00:00
Jim Grosbach
d7433e2873 NEON VST3(multiple 3-element structures) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 23:45:44 +00:00
Jim Grosbach
c387fc66bd NEON VLD3(multiple 3-element structures) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 23:20:46 +00:00
Jim Grosbach
3a678af71d NEON VLD3 lane-indexed assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 21:53:26 +00:00
Jim Grosbach
8b31f95bdd Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 19:39:08 +00:00
Jim Grosbach
51222d1551 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 18:09:51 +00:00
Jim Grosbach
0b4c673886 Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 22:46:46 +00:00
Jim Grosbach
4050bc4cab ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:19:05 +00:00
Rafael Espindola
b975c27adc Fix incorrect relocation generation. Patch by Kristof Beyls. 
Fixes PR11214.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 21:36:43 +00:00
Jim Grosbach
8d9550bde9 ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 18:04:04 +00:00
Jim Grosbach
af33a0cfe0 ARM VFP optional data type on VMOV GPR<-->SPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:24:15 +00:00
Jim Grosbach
520dc78d92 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 21:04:19 +00:00
Jim Grosbach
2cc5cda464 Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:54:00 +00:00
Jim Grosbach
e6949b1399 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:40:55 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:38:54 +00:00
Jim Grosbach
06d738c76a Enable and fix a test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:20:00 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:46:29 +00:00
Jim Grosbach
514806b52e ARM enable a few more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:03:00 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 19:21:26 +00:00
Jim Grosbach
04b5d93250 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 00:59:38 +00:00
Jim Grosbach
2f196747f1 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:06:24 +00:00
Jim Grosbach
d22170e16a ARM NEON two-operand aliases for VPADD. 
rdar://10602276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:51:03 +00:00
Jim Grosbach
61b74b4247 ARM NEON implied destination aliases for VMAX/VMIN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636 ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:31:43 +00:00
Jim Grosbach
a738da7bd3 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:56:33 +00:00
Jim Grosbach
60d99a5278 ARM NEON VTBL/VTBX assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:27:11 +00:00
Jim Grosbach
9b1b390288 ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:25:46 +00:00
Jim Grosbach
ec04a3f8db ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:49:24 +00:00
Jim Grosbach
e90ac9bce9 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:35:22 +00:00
Jim Grosbach
8d11c6349f ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:30:24 +00:00
Jim Grosbach
a39cda7aff ARM assembler support for the target-specific .req directive. 
rdar://10549683


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:16:11 +00:00
Jim Grosbach
863d2af947 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1 ARM LDM/STM system instruction variants. 
rdar://10550269

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:48:29 +00:00
Jim Grosbach
0da6e867cf Test for 146516 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:06:59 +00:00
Jim Grosbach
55b02f28c1 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:50:38 +00:00
Jim Grosbach
0f293de207 ARM NEON two-operand aliases for VQDMULH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:40:37 +00:00
Jim Grosbach
e91e7bcadc ARM pre-UAL NEG mnemonic for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:23:22 +00:00
Jim Grosbach
840bf7eda7 ARM assembly aliases for BIC<-->AND (immediate). 
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 22:02:17 +00:00
Jim Grosbach
a4e3c7fc4b ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 21:28:25 +00:00
Jim Grosbach
8759c3f548 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:19:04 +00:00
Jim Grosbach
6b044c2609 ARM VSHR implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:06:06 +00:00
Jim Grosbach
318df74104 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:04:40 +00:00
Jim Grosbach
120313435d ARM VSUB implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:56:26 +00:00
Jim Grosbach
beef39ab63 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:53:19 +00:00
Jim Grosbach
9e7b42a40e ARM VQADD implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389 ARM a few more VMUL implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:42:35 +00:00
Jim Grosbach
730fe6c1b6 ARM NEON two-operand aliases for VSHL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:30:04 +00:00
Jim Grosbach
ff4cbb4c9a ARM NEON two-operand aliases for VSHL(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:12:35 +00:00
Jim Grosbach
a44f2c4a28 ARM optional destination operand variants for VEXT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:43:47 +00:00
Jim Grosbach
71a0a2ec0b Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:41:54 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:40:58 +00:00
Jim Grosbach
9fa0a743e6 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f ARM two-operand aliases for VADDW instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13 ARM two-operand aliases for VADD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:52:54 +00:00
Jim Grosbach
8524bca750 Thumb2 alias for long-form pop and friends. 
rdar://10542474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca ARM support the .arm and .thumb directives for assembly mode switching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:51:15 +00:00
Jim Grosbach
d552a644be Tidy up. Move MachO tests to MachO directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
18851edbc4 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. 
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 06:48:26 +00:00
Jim Grosbach
23261af193 ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:03:45 +00:00
Jim Grosbach
df33e0d05e Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
286ea03382 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. 
MC/MachO assumes x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145916 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:56:05 +00:00
Jim Grosbach
713c70238c Tweak ADDrr fix. Bad check for explicit .w 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:27:04 +00:00
Jim Grosbach
6e507c645d Update tests for r145860. Add a few new ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:21:28 +00:00
Jim Grosbach
da84786bee Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:06:26 +00:00
Jim Grosbach
253ef7a779 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:29:59 +00:00
Jim Grosbach
c4f0b309ee ARM tests for VLD1 single lane w/ writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:03:52 +00:00
Jim Grosbach
dad2f8e7fb Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:52:30 +00:00
Jim Grosbach
e30171ba0c Add some tests for all-lanes VLD1 parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:37:38 +00:00
Jim Grosbach
4c7edb3ad8 ARM assembly parsing and encoding for four-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:58:48 +00:00
Jim Grosbach
ed1f83f9af Enable some VST1 tests and add a few more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:40:32 +00:00
Chris Lattner
d2bf432b2b Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 06:54:59 +00:00
Jim Grosbach
9b1671bae7 Remove obsolete test. 
The PLD encoding is checked via the .s file now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:50:38 +00:00
Jim Grosbach
2abba8496c Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:48:37 +00:00
Jim Grosbach
47a906ac23 Update test for r144842. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:46:27 +00:00
Jim Grosbach
e43862b6a6 ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 23:19:15 +00:00
Jim Grosbach
9f302c4fb3 ARM assembly parsing two operand forms for shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:27:54 +00:00
Jim Grosbach
19885de61d ARM alternate size suffices for VTRN instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:49:46 +00:00
Jim Grosbach
a68e90c36e ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:29:42 +00:00
Jim Grosbach
bfb0a1717b ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:14:51 +00:00
Jim Grosbach
d2586daf06 ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:02:06 +00:00
Jim Grosbach
908f923cfc Testcase for r144684. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144685 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:56:17 +00:00
Jim Grosbach
1de0bd1945 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:29:45 +00:00
Jim Grosbach
dd47e0b5d4 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:43:46 +00:00
Jim Grosbach
e052b9afa1 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:32:59 +00:00
Jim Grosbach
ef448767a3 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:11:19 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Jim Grosbach
c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:34:43 +00:00
Jim Grosbach
ce485e7f70 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 21:27:40 +00:00
Jim Grosbach
5402637ff2 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:17:11 +00:00
Jim Grosbach
1b332860ae Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:10:12 +00:00
Jim Grosbach
ee10ff89a2 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 16:44:55 +00:00
Jim Grosbach
3c5d6e4df4 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:44:23 +00:00
Benjamin Kramer
70be28a5ad Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:59 +00:00
Jim Grosbach
89a6337085 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:36:30 +00:00
Jim Grosbach
5d0492cfc4 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 16:57:07 +00:00
Jim Grosbach
c73d73eb88 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 00:06:50 +00:00
Jim Grosbach
88484c0030 Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:33:59 +00:00
Jim Grosbach
036a67d670 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:16:55 +00:00
Jim Grosbach
a581328ceb Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 22:22:01 +00:00
Jim Grosbach
399cdca4d2 ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-25 00:14:01 +00:00
Jim Grosbach
5921675ff5 ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:26:05 +00:00
Jim Grosbach
12431329d6 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 22:16:58 +00:00
Jim Grosbach
1028132b90 Update test for r142801. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142806 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 17:26:26 +00:00
Jim Grosbach
224180e81b Assembly parsing for 4-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 23:58:57 +00:00
Jim Grosbach
4661d4cac3 Assembly parsing for 2-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Owen Anderson
cd20c58e98 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 22:23:58 +00:00
Owen Anderson
5096503184 Fix tests for corrected MSR encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 21:53:19 +00:00
Jim Grosbach
6b09c77b7a ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 15:04:25 +00:00
Jim Grosbach
760b46ce18 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 14:57:47 +00:00
Jim Grosbach
d0b614754e ARM VTBX (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 14:48:50 +00:00