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68b16541cc
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22072 Commits

Author SHA1 Message Date
Andrew Trick
68b16541cc ARM getOperandLatency rewrite. 
Match expectations of the new latency API. Cleanup and make the logic consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 19:42:00 +00:00
Andrew Trick
f377071bf8 ARM getOperandLatency should return -1 for unknown, consistent with API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 19:41:58 +00:00
Andrew Trick
ed7a51e692 Fix ARM getInstrLatency logic to work with the current API. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 19:41:55 +00:00
Manman Ren
e6fc9d40b3 PR13046: we can't replace usage of SUB with CMP in the lowering phase. 
It will cause assertion failure later on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158160 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 19:27:33 +00:00
Rafael Espindola
c07f5bbd3b Use a base register instead of an index register with the local dynamic model. 
Fixes pr13048.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 18:39:19 +00:00
Manman Ren
87253c2ebd X86: replace SUB with CMP if possible 
This patch will optimize the following
    movq    %rdi, %rax
    subq    %rsi, %rax
    cmovsq  %rsi, %rdi
    movq    %rdi, %rax
to
    cmpq    %rsi, %rdi
    cmovsq  %rsi, %rdi
    movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 00:42:47 +00:00
Manman Ren
2afde7782d Revert r157755. 
The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 23:53:03 +00:00
Benjamin Kramer
95a9d93772 Round 2 of dead private variable removal. 
LLVM is now -Wunused-private-field clean except for
- lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields.
- gtest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 19:47:08 +00:00
Benjamin Kramer
a7542d5f87 Remove unused private fields found by clang's new -Wunused-private-field. 
There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 18:25:08 +00:00
Chad Rosier
a97b180fc4 Add support for dynamic stack realignment in the presence of dynamic allocas on 
X86.
rdar://11496434


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 17:37:40 +00:00
Richard Barton
c8f2fcc9a3 Correct decoder for T1 conditional B encoding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 09:12:53 +00:00
Craig Topper
3949b8382d Mark several instructions SSE2 instead of SSE3 as they should be. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 06:45:27 +00:00
Andrew Trick
b7e0289fb3 misched: API for minimum vs. expected latency. 
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 21:11:27 +00:00
Yuan Lin
09b5df8996 Fix header file include order in NVPTX backend NV_CONTRIB 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158013 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 19:06:13 +00:00
Roman Divacky
3e77af4318 PPC32 uses R2 as the TLS register. Fix the copy and paste. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158004 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 17:14:17 +00:00
Andrew Trick
1d98530196 X86 itinerary properties. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 03:44:46 +00:00
Andrew Trick
f94f051cf5 ARM itinerary properties. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 03:44:43 +00:00
Andrew Trick
fc992996f7 misched: Added MultiIssueItineraries. 
This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 03:44:40 +00:00
Andrew Trick
d05b46115f whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 03:44:29 +00:00
Joel Jones
e061053051 Revert commit r157966 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157972 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 00:47:21 +00:00
Joel Jones
dd52bf2ed8 This change handles a another case for generating the bic instruction 
when a compile time constant is known.  This occurs when implicitly zero 
extending function arguments from 16 bits to 32 bits.

<rdar://problem/11481151>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157966 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 23:38:57 +00:00
Akira Hatanaka
94ccee2222 Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is 
inserted after the shift-left-logical node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 17:46:29 +00:00
Roman Divacky
fd42ed676e Implement local-exec TLS on PowerPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 17:36:38 +00:00
Hans Wennborg
70a07c7fc4 MIPS TLS: use the model selected by TargetMachine::getTLSModel(). 
This was mostly done already in r156162, but I missed one place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157929 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 14:02:08 +00:00
Hans Wennborg
d01d693c0b Better comments for TLS-related X86 MachineOperand flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157920 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 09:55:36 +00:00
Craig Topper
caea5e28b2 Add intrinsic forms for FMA instructions to opcode folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157917 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 07:46:16 +00:00
Craig Topper
fc5ab24493 Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 forms of scalar FMA instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157914 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 07:08:21 +00:00
Hal Finkel
77a9e0f318 Fix a copy-and-paste duplication error in the PPC 440 and A2 schedules (no functionality change). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157912 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 02:39:52 +00:00
Hal Finkel
77838f9ca9 Enable generating PPC pre-increment (r+imm) instructions by default. 
It seems that this no longer causes test suite failures on PPC64 (after r157159),
and often gives a performance benefit, so it can be enabled by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157911 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 02:21:00 +00:00
Craig Topper
a15f9d5311 Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157903 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 18:58:46 +00:00
Craig Topper
529ce07c5f Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 07:26:46 +00:00
Manman Ren
c73ea9102b Revert r157831 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157896 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 03:14:24 +00:00
Craig Topper
57ae246a6a Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loads to match instruction behavior. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157895 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 01:40:43 +00:00
Craig Topper
60dda38008 Add neverHasSideEffects and mayLoad to FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157894 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 00:30:49 +00:00
Benjamin Kramer
d9b0b02561 Fix typos found by http://github.com/lyda/misspell-check 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 10:20:22 +00:00
Chris Lattner
00edc3dea2 remove an unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157872 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 01:03:42 +00:00
Akira Hatanaka
4c8acecfe3 Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157867 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:05:11 +00:00
Akira Hatanaka
7664f05326 Set operation actions for load/store nodes in the Mips backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157866 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:04:42 +00:00
Akira Hatanaka
4d70ceed33 Add definitions of 32/64-bit unaligned load/store instructions for Mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157865 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:04:19 +00:00
Akira Hatanaka
1cd0ec007a Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which 
custom-lower unaligned load and store nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157864 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:03:49 +00:00
Akira Hatanaka
b6f1dc2f09 Define Mips specific unaligned load/store nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157863 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:03:12 +00:00
Akira Hatanaka
f66b7b1ff6 Expand unaligned i16 loads/stores for the Mips backend. 
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:02:45 +00:00
Akira Hatanaka
bed5b0db45 In MipsMCInstLower::LowerSymbolOperand, get offset from symbol if 
the MachineOperand type has a valid offset. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157861 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:02:11 +00:00
Jakob Stoklund Olesen
396618b43a Switch all register list clients to the new MC*Iterator interface. 
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 23:28:30 +00:00
Chad Rosier
bbff4ee92d [arm-fast-isel] Fix handling of the frameaddress intrinsic. If depth is 0 
then DestReg is undefined.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157840 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 21:12:31 +00:00
Jakob Stoklund Olesen
f152fe8d48 Switch some getAliasSet clients to MCRegAliasIterator. 
MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157837 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 20:36:54 +00:00
Manman Ren
73c2f7f5ed X86: peephole optimization to remove cmp instruction 
This patch will optimize the following:
  sub r1, r3
  cmp r3, r1 or cmp r1, r3
  bge L1
TO
  sub r1, r3
  bge L1 or ble L1

If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 19:49:33 +00:00
Manman Ren
68f25571e7 ARM: properly handle alignment for struct byval. 
Factor out the expansion code into a function.
This change is to be enabled in clang.

rdar://9877866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157830 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 19:33:18 +00:00
Hans Wennborg
f0234fcbc9 Implement the local-dynamic TLS model for x86 (PR3985) 
This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 16:27:21 +00:00
Craig Topper
14f094bb2b Enable automatic detection of FMA3 support to allow intrinsics to be used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157805 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 06:10:14 +00:00