Craig Topper
a124f94952
Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-21 01:12:36 +00:00
Craig Topper
0d86d462f8
Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-20 00:12:05 +00:00
Craig Topper
745a86bac9
Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 22:34:59 +00:00
Craig Topper
ba798c5e51
Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 21:01:54 +00:00
Craig Topper
98fc72940b
Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144999 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 17:46:46 +00:00
Craig Topper
54f952afac
Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144989 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 09:02:40 +00:00
Craig Topper
3113384a34
Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 07:33:10 +00:00
Craig Topper
1666cb6d63
Extend VPBLENDVB and VPSIGN lowering to work for AVX2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 07:07:26 +00:00
Craig Topper
60d9a9206e
Remove unused parameters from the AVX maskmov classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144985 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 04:49:22 +00:00
Nadav Rotem
cbbe33fde4
Add AVX2 vpbroadcast support
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144967 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 02:49:55 +00:00
Chad Rosier
424fe0e422
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 01:17:34 +00:00
Chad Rosier
944d82ba06
Add TODO comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144920 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 21:46:13 +00:00
Craig Topper
d90a191685
Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:49:38 +00:00
Chad Rosier
2fb82ce75d
Dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:24:49 +00:00
Craig Topper
ec43d1f553
Remove seemingly unnecessary duplicate VROUND definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:04:00 +00:00
Eli Friedman
9d434dbff3
Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
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names for fwrite and fputs.
Fixes <rdar://problem/9815881>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:27:36 +00:00
Chad Rosier
3bdb3c9b51
Don't unconditionally set the kill flag.
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rdar://10456186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:16:53 +00:00
Eli Friedman
d224c7879a
Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 00:21:52 +00:00
Jim Grosbach
2abba8496c
Generalize the fixup info for ARM mode.
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We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:48:37 +00:00
Akira Hatanaka
620db8947a
Lower 64-bit constant pool node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:44:38 +00:00
Akira Hatanaka
9b944a8da2
Lower 64-bit block address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:42:10 +00:00
Jim Grosbach
b84acd2468
Fix encoding of NOP used for padding in ARM mode .align.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:40:25 +00:00
Akira Hatanaka
74c76347d3
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
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nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:39:56 +00:00
Akira Hatanaka
4fd40b3604
64-bit jump register instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:36:01 +00:00
Evan Cheng
2b89498979
Another missing X86ISD::MOVLPD pattern. rdar://10450317
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144839 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:24:44 +00:00
Jim Grosbach
40a86ee20f
ARM assembly parsing for shifted register operands for MOV instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:50:05 +00:00
Jim Grosbach
efed3d1f58
Clean up debug printing of ARM shifted operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:46:50 +00:00
Jim Grosbach
b598b04409
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:12:24 +00:00
Jim Grosbach
48b368bcd5
ARM assembly parsing for RRX mnemonic.
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rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:05:59 +00:00
Pete Cooper
cd75e44173
Added missing comment about new custom lowering of DEC64
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:03:23 +00:00
Chad Rosier
508a1f4db1
Check to make sure we can select the instruction before trying to put the
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operands into a register. Otherwise, we may materialize dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:39:44 +00:00
Jim Grosbach
23f220705a
ARM mode aliases for bitwise instructions w/ register operands.
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rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:31:45 +00:00
Bob Wilson
d0405aaabc
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 17:09:59 +00:00
NAKAMURA Takumi
5c283e98c9
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 09:18:28 +00:00
Evan Cheng
b95fc31aa2
Sink codegen optimization level into MCCodeGenInfo along side relocation model
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and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 08:38:26 +00:00
Craig Topper
12755b07ab
Fix the execution domain on a bunch of SSE/AVX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144784 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:30:46 +00:00
Bob Wilson
eaab6ef6eb
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
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The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:11:57 +00:00
Craig Topper
2713d045e3
Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144777 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 05:02:04 +00:00
Chad Rosier
f56c60b571
Add FIXME comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 00:32:20 +00:00
Jakob Stoklund Olesen
3805d85e38
Enable -widen-vmovs by default.
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This will widen 32-bit register vmov instructions to 64-bit when
possible. The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.
The copies are only widened if they are marked as clobbering the whole
D-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 23:53:18 +00:00
Jim Grosbach
e43862b6a6
ARM assembly parsing for register range syntax for VLD/VST register lists.
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For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 23:19:15 +00:00
Jim Grosbach
5b2fb2083c
ARM assembly parsing for data type suffices on NEON VMOV aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:54:42 +00:00
Nadav Rotem
f8c10e5cb1
AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144720 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:50:37 +00:00
Jim Grosbach
9f302c4fb3
ARM assembly parsing two operand forms for shift instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:27:54 +00:00
Jim Grosbach
88d012a9c3
ARM VFP assembly parsing for VADD and VSUB two-operand forms.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:15:10 +00:00
Jim Grosbach
6cb4b08182
ARM accept an immediate offset in memory operands w/o the '#'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:14:41 +00:00
Pete Cooper
2d49689793
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
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by later instructions.
Only done for DEC64m right now.
Fixes <rdar://problem/6172640>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 21:57:53 +00:00
Jim Grosbach
5c984e451d
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
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'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 21:45:55 +00:00
Jim Grosbach
eaf2056709
ARM size suffix on VFP single-precision 'vmov' is optional.
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rdar://10435114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144698 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 21:18:35 +00:00
Jim Grosbach
25e0a87e91
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144695 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 21:01:30 +00:00
Jim Grosbach
19885de61d
ARM alternate size suffices for VTRN instructions.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:49:46 +00:00
Owen Anderson
22925d93e9
Fix a misplaced paren bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:30:41 +00:00
Jim Grosbach
a68e90c36e
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
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Yet more of rdar://10435076.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:29:42 +00:00
Jim Grosbach
bfb0a1717b
ARM assembly parsing for two-operand form of 'mul' instruction.
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rdar://10449856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:14:51 +00:00
Jim Grosbach
d2586daf06
ARM assembly parsing for two-operand form of 'mul' instruction.
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Ongoing rdar://10435114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:02:06 +00:00
Jim Grosbach
7f1ec9570d
Thumb2 two-operand 'mul' instruction wide encoding parsing.
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rdar://10449724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 19:55:16 +00:00
Owen Anderson
b589be9334
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 19:55:00 +00:00
Jim Grosbach
1de0bd1945
Thumb2 assembly parsing for mul.w in IT block fix.
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When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 19:29:45 +00:00
Akira Hatanaka
1b71950812
Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
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registers and instructions when ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:53:55 +00:00
Akira Hatanaka
ac20aad81c
Set nomacro before emitting the sequence of instructions that set global pointer
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register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:44:44 +00:00
Akira Hatanaka
160408546c
Simplify function PassByValArg64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:42:25 +00:00
Akira Hatanaka
870b3b2dd4
Delete files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:22:48 +00:00
Akira Hatanaka
73c38f0aa2
Remove MipsMCSymbolRefExpr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:20:08 +00:00
Jim Grosbach
c5a6a687fd
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 17:49:59 +00:00
Jay Foad
bf8356b37c
Fix typo in comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:50:05 +00:00
Jay Foad
978e0dfe46
Make use of MachinePointerInfo::getFixedStack. This removes all mention
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of PseudoSourceValue from lib/Target/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:34:52 +00:00
Jay Foad
d9190c0f14
Remove some unnecessary includes of PseudoSourceValue.h.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:24:32 +00:00
Craig Topper
44ec9fddc2
Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144629 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 06:39:01 +00:00
Craig Topper
4c077a1f04
Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144622 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 05:55:35 +00:00
Evan Cheng
eaa192af18
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
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integer variants. rdar://10437054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 02:12:34 +00:00
Jim Grosbach
bfc9429c2b
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 01:46:57 +00:00
Jakob Stoklund Olesen
c2ecf3efbf
Break false dependencies before partial register updates.
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Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.
The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.
The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 01:15:30 +00:00
Jim Grosbach
dd47e0b5d4
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:43:46 +00:00
Jim Grosbach
e052b9afa1
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:32:59 +00:00
Jim Grosbach
04db7f7a7d
Add explanatory comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:21:09 +00:00
Jim Grosbach
0530d0d5d9
Split out the plain '.{8|16|32|64}' suffix handling.
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Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:20:14 +00:00
Jim Grosbach
ef448767a3
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:11:19 +00:00
Chad Rosier
2c42b8c912
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
...
violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:04:09 +00:00
Jim Grosbach
ffc658b056
ARM VLDR/VSTR instructions don't need a size suffix.
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Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
Chad Rosier
909cb4f2f2
Add support for inlining small memcpys.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:46:17 +00:00
Chad Rosier
e489af8dce
Fix a performance regression from r144565. Positive offsets were being lowered
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into registers, rather then encoded directly in the load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:34:48 +00:00
Jim Grosbach
02e3d9268f
ARM assembly parsing type suffix options for VLDR/VSTR.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:28:39 +00:00
Evan Cheng
76c8f08567
Add a missing pattern for X86ISD::MOVLPD. rdar://10436044
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 20:35:52 +00:00
Chad Rosier
57b2997966
Add support for Thumb load/stores with negative offsets.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 20:22:27 +00:00
Benjamin Kramer
6296ee3ee2
Unbreak Release builds.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:51:48 +00:00
Pete Cooper
a77214a4c4
Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered
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Constant idx case is still done in tablegen but other cases are then expanded
Fixes <rdar://problem/10435460>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:38:42 +00:00
Akira Hatanaka
788dc0f4e5
32-to-64-bit extended load.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144554 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:06:14 +00:00
Akira Hatanaka
4961709688
AnalyzeCallOperands function for N32/64.
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N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:02:54 +00:00
Akira Hatanaka
bad53f41c2
Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:01:09 +00:00
Justin Holewinski
a3f7e229b6
PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 18:58:20 +00:00
Akira Hatanaka
47a4ab84fe
Remove variable that keeps the size of area used to save byval or variable
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argument registers on the callee's stack frame, along with functions that set
and get it.
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144549 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 18:56:20 +00:00
Jim Grosbach
430052b084
Tidy up. 80 column.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 17:52:47 +00:00
Craig Topper
dcce244dd8
Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 08:07:55 +00:00
Craig Topper
3426a3efef
Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 06:46:21 +00:00
Chad Rosier
dc9205d9c2
Add support for ARM halfword load/stores and signed byte loads with negative
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offsets.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 04:09:28 +00:00
Craig Topper
e6a6277d36
Add BLSI, BLSMSK, and BLSR to getTargetNodeName.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 17:31:07 +00:00
Chad Rosier
9eb674880b
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 09:44:21 +00:00
Chad Rosier
a517ab155b
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 05:14:43 +00:00
Chad Rosier
5be833de76
Fix comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 04:25:02 +00:00
Chad Rosier
b29b950bf2
Add support for emitting both signed- and zero-extend loads. Fix
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SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 02:23:59 +00:00
Craig Topper
7be5dfd1a1
Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 09:58:49 +00:00
Akira Hatanaka
7386612a16
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144453 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:38:12 +00:00
Akira Hatanaka
6df3e7b162
Implement Mips64's handling of byval arguments in LowerCall.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144452 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:34:50 +00:00
Akira Hatanaka
3a5257de21
Implement Mips64's handling of byval arguments in LowerFormalArguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144449 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:29:58 +00:00
Akira Hatanaka
deab22a556
64-bit arbitrary immediate pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:25:00 +00:00
Akira Hatanaka
2c5d65202e
Function for handling byval arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:20:46 +00:00
Daniel Dunbar
b8ebca83f4
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
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- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:10:57 +00:00
Jim Grosbach
9588c10b69
ARM refactor simple immediate asm operand render methods.
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These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 00:58:43 +00:00
Jim Grosbach
742c4bac07
Re-apply 144430, this time with the associated isel and disassmbler bits.
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Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 00:31:53 +00:00
Jim Grosbach
4d06138d53
Oops. Missed the isel half of this. revert while I sort that out.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:51:31 +00:00
Jim Grosbach
10a630dea6
ARM assembly parsing for VST1 two-register encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:45:47 +00:00
Jim Grosbach
c7352f8ca0
ARM optional size suffix for VLDR/VSTR syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:34:43 +00:00
Chad Rosier
11add26ec2
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:31:03 +00:00
Daniel Dunbar
b12f97534c
CMake: Fix CMake build for new Mips tblgen file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144423 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:12:56 +00:00
Jim Grosbach
7aef99b677
ARM vldm and vstm VFP instructions can take a data type suffix.
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It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:08:10 +00:00
Daniel Dunbar
f779757ceb
Target/LLVMBuild: Order components alphabetically.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:59:16 +00:00
Bruno Cardoso Lopes
47b92f3d83
Mips MC object code emission improvements:
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"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144414 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:58:42 +00:00
Jim Grosbach
c3937b97c0
Nuke no longer accurate comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:30:06 +00:00
Andrew Trick
95bc85e4ee
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
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Fixes PR8113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:18:09 +00:00
Jim Grosbach
ce485e7f70
ARM allow Q registers in vldm/vstm register lists.
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rdar://9672822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 21:27:40 +00:00
Dan Bailey
96e6458903
allow non-device function calls in PTX when natively handling device-side printf
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 14:45:12 +00:00
Dan Bailey
b812ee6d78
add rules in tabgen for PTX COPY_ADDRESS of frameindex
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144387 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 14:45:06 +00:00
Benjamin Kramer
eea66f63d9
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 12:39:41 +00:00
Benjamin Kramer
7fb12ef5a6
Remove the unnecessary dependency on libMBlazeCodeGen from libMBlazeDisassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 12:39:35 +00:00
Craig Topper
46154eb6fd
Add lowering for AVX2 shift instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 07:39:23 +00:00
Chad Rosier
1c47de87c7
Rename variables to avoid confusion. No functionallity change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 06:27:41 +00:00
Chad Rosier
a07d3fc693
Add support for using immediates with select instructions.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 06:20:39 +00:00
Akira Hatanaka
e184fec550
Do not try to detect DAG combine patterns for integer multiply-add/sub if value
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type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144373 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:18:21 +00:00
Akira Hatanaka
59068067cb
64-bit atomic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:14:30 +00:00
Akira Hatanaka
46ac4399b1
Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:11:56 +00:00
Akira Hatanaka
c742e4fc90
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:06:38 +00:00
Akira Hatanaka
642b109713
64-bit versions of jal, jalr and bal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:03:54 +00:00
Akira Hatanaka
a1fa08f66a
Emit Mips64's sequence of instructions that set global register in prologue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:00:29 +00:00
Akira Hatanaka
d5cf5a631f
Fix printing of MCSymbolRegExpr. Needs three closing parentheses for
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VK_Mips_GPOFF_HI/LO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 03:58:36 +00:00
Eli Friedman
15f58c56e9
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 03:16:38 +00:00
Chad Rosier
646abbfa30
When loading a value, treat an i1 as an i8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 02:38:59 +00:00
Bill Wendling
c739577d3c
If we have to reset the calculation of the compact encoding, then also reset the
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"saved register" index.
<rdar://problem/10430076>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 00:59:14 +00:00
Chad Rosier
4e89d97e3a
Add support for using MVN to materialize negative constants.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 00:36:21 +00:00
Daniel Dunbar
5ed5506f18
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 00:23:56 +00:00
Jim Grosbach
0352b4679e
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
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rdar://10429490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:58:34 +00:00
Jim Grosbach
83ec87755e
ARM let processInstruction() tranforms chain.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:42:14 +00:00
Jim Grosbach
5402637ff2
Thumb2 parsing for push/pop w/ hi registers in the reglist.
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rdar://10130228.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:17:11 +00:00
Jim Grosbach
fae02597bb
Thumb1 diagnostics for reglist on PUSH/POP fix.
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Was not checking the first register in the register list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:01:27 +00:00
Jim Grosbach
1b332860ae
Thumb MUL assembly parsing for 3-operand form.
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Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 22:10:12 +00:00
Daniel Dunbar
eaf4221cef
build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler
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that depends on MBlazeCodeGen. This is a layering violation that should really
be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 22:00:37 +00:00
Chad Rosier
16455ce1a4
When in ARM mode, LDRH/STRH require special handling of negative offsets.
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For correctness, disable this for now.
rdar://10418009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 21:09:49 +00:00
Jim Grosbach
d475f8612b
ARM .thumb_func directive for quoted symbol names.
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Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 20:48:53 +00:00
Jim Grosbach
ee10ff89a2
ARM assembly parsing for LSR/LSL/ROR(immediate).
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More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0
ARM assembly parsing for ASR(immediate).
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Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 16:44:55 +00:00
Daniel Dunbar
977665c24a
build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for
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consistency with other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 15:35:14 +00:00