Commit Graph
7717 Commits
Author SHA1 Message Date
Paul Redmond 86cdbc9c29 enable SDISel sincos optimization for GNU environments
- add sincos to runtime library if target triple environment is GNU
- added canCombineSinCosLibcall() which checks that sincos is in the RTL and
  if the environment is GNU then unsafe fpmath is enabled (required to
  preserve errno)
- extended sincos-opt lit test

Reviewed by: Hal Finkel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175283 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 18:45:18 +00:00
Tim Northover 1e8839302b AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 09:33:43 +00:00
Tim Northover 148ac534fc AArch64: refactor frame handling to use movz/movk for overlarge offsets.
In the near future litpools will be in a different section, which means that
any access to them is at least two instructions. This makes the case for a
movz/movk pair (if total offset <= 32-bits) even more compelling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 09:33:26 +00:00
Reed Kotler 5cf38fd763 Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 01:04:38 +00:00
Nadav Rotem 6cc4b8d1eb Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 18:28:52 +00:00
Weiming Zhao 7248451c43 Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 18:10:21 +00:00
Vincent Lejeune 7867885737 R600: Do not fold single instruction with more that 3 kcache read
It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175183 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 16:57:19 +00:00
Kristof Beyls b1d081230e Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 14:46:12 +00:00
Elena Demikhovsky 60b3e18d67 Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).
Added a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 08:20:26 +00:00
Michel Danzer d4addbe78a R600: Add lit tests for texture sampling instruction selection.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 07:43:51 +00:00
Andrew Trick 05fdb82535 Reapply "s/grep/FileCheck/ in some tests"
This reverts commit fd1335e982.

Use a triple this time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 03:45:08 +00:00
Andrew Trick fd1335e982 Revert "s/grep/FileCheck/ in some tests"
This reverts commit 8b75e6bc35.

The FileCheck tests are not equivalent:

test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input
; CHECK: jmp init
         ^
<stdin>:1:2: note: scanning from here
 .section __TEXT,__text,regular,pure_instructions
 ^
<stdin>:13:2: note: possible intended match here
 jmp _init ## TAILCALL
 ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 03:00:57 +00:00
Weiming Zhao c0c2816fb3 temporarily revert the patch due to some conflicts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 23:24:40 +00:00
Anshuman Dasgupta 666e0d3bc4 Hexagon: add support for predicate-GPR copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 22:56:34 +00:00
Tom Stellard 76308d8d28 R600: Add support for 128-bit parameters
NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 22:05:20 +00:00
Eli Bendersky fa7c9efcd3 s/grep/FileCheck/ in some tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 22:00:37 +00:00
Eli Bendersky 8b75e6bc35 s/grep/FileCheck/ in some tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:46:38 +00:00
Weiming Zhao 3019fbbe6a Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:43:02 +00:00
Chad Rosier 5867302b16 [ms-inline asm] Fix up test case for non-Darwin platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:41:58 +00:00
Jyotsna Verma f6563427c4 Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:38:46 +00:00
Chad Rosier 7b0bc3fe3e [ms-inline-asm] Add support for memory references that have non-immediate
displacements.
rdar://12974533


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:33:44 +00:00
Reed Kotler 6b9d461780 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 20:28:27 +00:00
David Peixotto af7c042af1 PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 19:21:47 +00:00
Benjamin Kramer f09e02f01a X86: Disable generation of rep;movsl when %esi is used as a base pointer.
This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.

Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 13:40:35 +00:00
Reed Kotler 8080696103 Make jumptables work for -static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 08:32:14 +00:00
Elena Demikhovsky d29804f80d Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 08:02:04 +00:00
Eric Christopher 23571f4f2c Check i1 as well as i8 variables for 8 bit registers for x86 inline
assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 06:01:05 +00:00
Eric Christopher a4e8694053 Finish obviously broken thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 06:01:00 +00:00
Paul Redmond de53477c91 Fix the lit test added in r174972
Patch by: Kevin Schoedel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174974 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 16:07:27 +00:00
Jyotsna Verma 6b8d2026ba Hexagon: Add support to generate predicated absolute addressing mode
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 16:06:23 +00:00
Paul Redmond 5c97450df7 PR14562 - Truncation of left shift became undef
DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32))
into (shl i32 v, 32) into undef. To prevent this, check the shift count
against the final result size.

Patch by: Kevin Schoedel
Reviewed by: Nadav Rotem


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 15:21:21 +00:00
Justin Holewinski 7eacad03ef [NVPTX] Disable vector registers
Vectors were being manually scalarized by the backend.  Instead,
let the target-independent code do all of the work.  The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 14:18:49 +00:00
Arnold Schwaighofer d9316dacf5 ARM NEON: Handle v16i8 and v8i16 reverse shuffles
Lower reverse shuffles to a vrev64 and a vext instruction instead of the default
legalization of storing and loading to the stack. This is important because we
generate reverse shuffles in the loop vectorizer when we reverse store to an
array.

  uint8_t Arr[N];
  for (i = 0; i < N; ++i)
    Arr[N - i - 1] = ...

radar://13171760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 01:58:32 +00:00
Krzysztof Parzyszek 71490fa946 Extend Hexagon hardware loop generation to handle various additional cases:
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174904 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11 21:37:55 +00:00
Justin Holewinski ff5adad9f3 [NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture is not valid in this case, and was causing incorrect optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174896 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11 18:56:35 +00:00
Reed Kotler b2d1275188 Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the
same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is 
important as well as for other passes which need an accurate count of 
program size. There will be other similar putbacks to this for various
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08 21:42:56 +00:00
Hal Finkel 089a5f8a8c DAGCombiner: Constant folding around pre-increment loads/stores
Previously, even when a pre-increment load or store was generated,
we often needed to keep a copy of the original base register for use
with other offsets. If all of these offsets are constants (including
the offset which was combined into the addressing mode), then this is
clearly unnecessary. This change adjusts these other offsets to use the
new incremented address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08 21:35:47 +00:00
Bob Wilson 8f637adbd3 Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.
Aside from the question of whether we report a warning or an error when we
can't satisfy a requested stack object alignment, the current implementation
of this is not good.  We're not providing any source location in the diagnostics
and the current warning is not connected to any warning group so you can't
control it.  We could improve the source location somewhat, but we can do a
much better job if this check is implemented in the front-end, so let's do that
instead.  <rdar://problem/13127907>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174741 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08 20:35:15 +00:00
Reed Kotler 61b97b8c17 When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08 03:57:41 +00:00
Tom Stellard 1234c9be42 R600: Add support for SET*_DX10 instructions
These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 14:02:35 +00:00
Tom Stellard 2a77cf7f47 R600: Add tests for unsupported condition codes.
All of the le and lt variants are unsupported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174608 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 14:02:33 +00:00
Tom Stellard b4409610a2 R600: Fix assembly name for SETGT_INT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 14:02:27 +00:00
Reed Kotler 24b339dcdc Make sure we call externals from libraries properly when -static.
For example, when we are doing mips16 hard float or soft float.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174583 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 04:34:51 +00:00
Reed Kotler 6e3443eed4 Enable jumps when in -static mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 03:49:51 +00:00
Eli Bendersky 16221a60a0 This is a follow-up on r174446, now taking Atom processors into
account. Atoms use LEA for updating SP in prologs/epilogs, and the
exact LEA opcode depends on the data model.

Also reapplying the test case which was added and then reverted
(because of Atom failures), this time specifying explicitly the CPU in
addition to the triple. The test case now checks all variations (data
mode, cpu Atom vs. Core).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 20:43:57 +00:00
Tim Northover 8a06229c89 Implement external weak (ELF) symbols on AArch64
Weakly defined symbols should evaluate to 0 if they're undefined at
link-time. This is impossible to do with the usual address generation
patterns, so we should use a literal pool entry to materlialise the
address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 16:43:33 +00:00
Eli Bendersky a859afa859 Remove this test in the meantime, since it won't pass on Atom. Atom uses lea
to move the stack pointer in prologs/epilogs. I will fix the test and add it
back later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 03:15:00 +00:00
Manman Ren 9c5861fdbd Attempt to recover gdb bot after r174445.
Failure: undefined symbol 'Lline_table_start0'.
Root-cause: we use a symbol subtraction to calculate at_stmt_list, but
the line table entries are not dumped in the assembly.
Fix: use zero instead of a symbol subtraction for Compile Unit 0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 00:59:41 +00:00
Eli Bendersky 61b057a6fd Test for r174446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 23:31:48 +00:00
Manman Ren 43213cf1ac Dwarf: support for LTO where a single object file can have multiple line tables
We generate one line table for each compilation unit in the object file.
Reviewed by Eric and Kevin.

rdar://problem/13067005


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 21:52:47 +00:00