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17175 Commits

Author SHA1 Message Date
Bob Wilson
b1dfa7a8e0 Add support for NEON VLD2-dup instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:26 +00:00
Bob Wilson
f3d2f9d4be Another minor refactoring for VLD1DUP instructions. 
The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:15 +00:00
Bob Wilson
364a72a8e5 Add entry in getTargetNodeName() for ARMISD::VBICIMM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:11 +00:00
Anton Korobeynikov
94c5ae0875 Move more PEI-related hooks to TFI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 23:05:25 +00:00
Anton Korobeynikov
cd775ceff0 Move callee-saved regs spills / reloads to TFI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 23:05:03 +00:00
Rafael Espindola
5bf7c534cf Lower TLS_addr32 and TLS_addr64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 20:43:02 +00:00
Rafael Espindola
bfd2d26159 Implement the data16 prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 20:29:45 +00:00
Bob Wilson
bce55776af Refactor. Set alignment bit in VLD1-dup instruction classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 07:12:02 +00:00
Bob Wilson
2a0e97431e Add NEON VLD1-dup instructions (load 1 element to all lanes). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 06:35:16 +00:00
Bob Wilson
8d41294664 Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions. 
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from.  As far as I can tell now,
these instruction stages are clearly intended to overlap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 06:35:09 +00:00
Daniel Dunbar
36d76a8dbc MC/Mach-O: Switch to using MachOFormat.h. 
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 04:38:36 +00:00
Rafael Espindola
fd46797d0d Remove the unused TheTarget member. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-26 04:24:21 +00:00
Rafael Espindola
2ace1b68ac Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120147 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-25 17:14:16 +00:00
Benjamin Kramer
c62feda741 Namespacify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120146 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-25 16:42:51 +00:00
Wesley Peck
42e75a3cf1 Updating MBlaze .mask and .frame directives to match GCC's output and fixing regression introduced in 120095 by checking MCStreamer::hasRawTextSupport. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120097 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-24 16:32:35 +00:00
Wesley Peck
82dc040d06 1. Fixing error where basic block labels were not being printed out when they need to be for the MBlaze backend because AsmPrinter::isBlockOnlyReachableByFallthrough does not take into account delay slots. 
2. Re-adding .mask and .frame directives in printed assembly.
3. Adding .ent and .end directives in printed assembly.
4. Minor cleanups to MBlaze backend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-24 15:39:32 +00:00
Kalle Raiskila
7de8101668 Use i8 as SETCC result type for i1 in SPU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120092 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-24 12:59:16 +00:00
Kalle Raiskila
702a4046a9 Allow for 'fcmp ogt' in SPU. 
Fix by Visa Putkinen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120090 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-24 11:42:17 +00:00
Benjamin Kramer
c21a821e9f The srem -> urem transform is not safe for any divisor that's not a power of two. 
E.g. -5 % 5 is 0 with srem and 1 with urem.

Also addresses Frits van Bommel's comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 20:33:57 +00:00
Jason W Kim
13534672de Move the ARM reloc constants to Support/ELF.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120035 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 19:40:36 +00:00
Bob Wilson
626613d5e8 Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations. 
We need to check if the individual vector elements are sign/zero-extended
values.  For now this only handles constants values.  Radar 8687140.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120034 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 19:38:38 +00:00
Benjamin Kramer
b70ebd2aa3 InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is positive. 
This allows to transform the rem in "1 << ((int)x % 8);" to an and.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 18:52:42 +00:00
Kalle Raiskila
0cc5b1f60e Division by pow-of-2 is not cheap on SPU, do it with 
shifts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 13:27:59 +00:00
Rafael Espindola
beb6898df8 Implement the rex64 prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120017 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 11:23:24 +00:00
Rafael Espindola
d93ceeb125 Produce a relocation for pcrel absolute values. Based on a patch by David Meyer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 07:20:12 +00:00
Wesley Peck
bf17cfa3f9 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 03:31:01 +00:00
Rafael Espindola
d80f8d08ce Remove duplicated constants. Thanks to Jason for noticing it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 21:49:05 +00:00
Benjamin Kramer
93f8455d73 InstCombine: Implement X - A*-B -> X + A*B. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 20:31:27 +00:00
Evan Cheng
ab5c703fdb Fix epilogue codegen to avoid leaving the stack pointer in an invalid 
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 18:12:04 +00:00
Kalle Raiskila
d87e571e62 Fix a bug with extractelement on SPU. 
In the attached testcase, the element was
never extracted (missing rotate).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119973 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 16:28:26 +00:00
Benjamin Kramer
ce750f0332 Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization. 
This currently only catches the most basic case, a two-case switch, but can be
extended later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 09:45:38 +00:00
Duncan Sands
3d93893895 Fix a compiler warning about Kind being used uninitialized 
when assertions are disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119962 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 09:38:00 +00:00
Eric Christopher
9d89311df8 Pseudos default to 4byte size, let the instruction size field notice 
that branch tables are special.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 23:38:19 +00:00
Wesley Peck
4b04713423 Implement ELF object file writing support for the MBlaze backend. Its not perfect yet, but it works for many tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 22:06:28 +00:00
Wesley Peck
46a928b864 Implement branch analysis in the MBlaze backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 21:53:36 +00:00
Wesley Peck
6e749f31c6 Make it a little bit more explicit that the MBlaze backend only supports upto 
32-bit immediate values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 21:39:46 +00:00
Wesley Peck
5437ba48ce Fix an error in the MBlaze delay slot filler where instructions that already 
fill a delay slot are moved to fill a different delay slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 21:36:12 +00:00
Chris Lattner
8bc1e45295 apparently tailcalls are better on darwin/x86-64 than on linux? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 18:59:20 +00:00
Bill Wendling
dcf0a47b76 More Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 11:49:36 +00:00
Bill Wendling
af2b573614 Add encoding for ARM "trap" instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 11:05:29 +00:00
Bill Wendling
9717fa9f29 The "trap" instruction is one of this which doesn't have a condition code. Hack 
the code to not add a "condition code" if it's trap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 10:56:05 +00:00
Bill Wendling
7d0affdf02 - Give "trap" the correct encoding, at least according to Darwin's assembler. 
- Add comments saying where the encodings for other instructions came from.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 10:55:23 +00:00
Chris Lattner
cbf5d74e6a implement PR8524, apparently mainline gas accepts movq as an alias for movd 
when transfering between i64 gprs and mmx regs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119931 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 08:18:57 +00:00
Chris Lattner
3e41106de4 add some random notes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119925 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 07:05:31 +00:00
Owen Anderson
aa54524a44 Use by-name rather than by-order operand matching for some NEON encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119923 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 06:47:06 +00:00
Chris Lattner
75d8f599e7 optimize: 
void a(int x) { if (((1<<x)&8)==0) b(); }

into "x != 3", which occurs over 100 times in 403.gcc but in no
other program in llvm-test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119922 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 06:44:42 +00:00
Chris Lattner
79a980ad85 tail calls on x86 are implemented. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119920 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 06:10:27 +00:00
Jim Grosbach
0eb49c57f0 BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119918 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 01:26:01 +00:00
Bill Wendling
5cc88a205d A few more thumb instruction MC encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119913 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:52:33 +00:00
Eric Christopher
827656dab4 Rewrite address handling to use a structure with all the possible address 
mode variables. Handle frame indexes in load/store and allocas again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:38:27 +00:00
Eric Christopher
13df1a0bac STRH only needs the additional operand, not t2STRH. Also invert conditional 
to match the one from the load emitter above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119911 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:01:38 +00:00
Anton Korobeynikov
0dbe54e844 Make this compile on case-sensitive file systemsw 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119905 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 16:14:57 +00:00
Anton Korobeynikov
82f58740c7 Move some more hooks to TargetFrameInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 15:59:32 +00:00
Duncan Sands
59d2dad59e On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics, 
so don't claim they are.  They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory.  This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this).  Add some nasty checking to try
to catch this kind of thing in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 11:25:00 +00:00
Bill Wendling
a09cc2b429 Add more Thumb add instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 01:18:47 +00:00
Bill Wendling
95a6d1759d Add Thumb encodings for some add instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119882 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 01:00:29 +00:00
Bill Wendling
6179c31e07 Add more encodings for Thumb instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 00:53:35 +00:00
Bill Wendling
20272a7c5a Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same 
value that the one in ARMMCCodeEmitter.cpp does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 00:26:37 +00:00
Jim Grosbach
078e239f69 Fix ARM LDR* post-indexed operand encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:14:43 +00:00
Bill Wendling
1228038ed9 Encodings for the compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119868 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:14:32 +00:00
Owen Anderson
b16926940e The Vm and Vn register fields must be the same for a register-register vmov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:12:43 +00:00
Evan Cheng
ff96b63d6f Fix a cut-n-paste-error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119866 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:01:16 +00:00
Jim Grosbach
7b6ab402fe Operand names 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119864 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:43:08 +00:00
Jim Grosbach
a30a51b16a trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119863 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:42:55 +00:00
Eric Christopher
b371658083 Don't need to save piecemeal now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:39:56 +00:00
Eric Christopher
2d630d7bc9 Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:37:58 +00:00
Bill Wendling
0ae28e4447 Add encodings for some of the thumb ADD instructions. Tests will come once the 
asm parser can handle them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:37:33 +00:00
Eric Christopher
88de86b550 Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:36:41 +00:00
Jim Grosbach
efaeb41aec Clarify operand names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:36:02 +00:00
Eric Christopher
0d58122e12 Refactor address mode handling into a single struct (ala x86), this 
should give allow a wider range of addressing modes.

No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119856 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:30:02 +00:00
Jim Grosbach
6571101cb7 Fix encoding for ARM MLS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119855 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:22:37 +00:00
Jim Grosbach
2aeb6121a1 Add ARM encoding information for STRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:14:31 +00:00
Jim Grosbach
a1b4175b8e Shuffle things around a bit to keep like things together. Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:06:57 +00:00
Bill Wendling
ba46dc06e6 Revert accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:06:18 +00:00
Bill Wendling
a898166d38 Change long binary encodings to use hex instead. It's more readable. Also 
initialize missing bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119849 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:02:18 +00:00
Jim Grosbach
953557f445 Factor out operand encoding bits for ARM addressing mode 2 store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119846 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:35:06 +00:00
Jim Grosbach
e2d54af47f Delete another dead class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119844 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:16:08 +00:00
Jim Grosbach
fc0cb4b906 whitespace tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:14:37 +00:00
Jim Grosbach
9ef65cbbc6 Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119841 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:14:02 +00:00
Jim Grosbach
9558b4cdc4 Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119840 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:07:51 +00:00
Jim Grosbach
9cb15b5be5 Add ARM binary encoding information for the rest of the indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119821 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 19:41:26 +00:00
Jim Grosbach
0c2283a910 Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 18:18:37 +00:00
Jim Grosbach
f1ce7cc1d1 ARM LDRD binary encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 18:16:46 +00:00
Jim Grosbach
3ea4daaf50 Remove hard tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119810 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 18:01:37 +00:00
Jim Grosbach
7a08864860 Remove trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 17:11:02 +00:00
Benjamin Kramer
7920d96964 Avoid release build warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 16:36:02 +00:00
Owen Anderson
8b8640a964 Fix decoding ambiguities of stdrex and ldrex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 13:11:50 +00:00
Evan Cheng
1f190c8bdf These instructions are thumb2 only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119793 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 06:28:11 +00:00
Evan Cheng
e8e67e13d4 Fix an obvious oversight. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 06:15:10 +00:00
Rafael Espindola
195a0ce484 Change some methods in MCDwarf.cpp to be able to handle an arbitrary 
MCStreamer instead of just MCObjectStreamer. Address changes cannot
be as efficient as we have to use DW_LNE_set_addres, but at least
most of the logic is shared.

This will be used so that, with CodeGen still using EmitDwarfLocDirective,
llvm-gcc is able to produce debug_line sections without needing an
assembler that supports .loc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119777 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 02:26:16 +00:00
Bill Wendling
602890dd8e Add MC encodings for some Thumb instructions. Test for a few of them. The "bx 
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119774 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 01:33:10 +00:00
Bill Wendling
cb21d1c9fd Use array_pod_sort because the list is contiguous. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:38:19 +00:00
Owen Anderson
91a7c59134 Provide Thumb2 encodings for strex and ldrex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119768 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:28:38 +00:00
Jim Grosbach
817c1a6ddd Minor cleanups to a few llvm_unreachable() calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:27:09 +00:00
Bill Wendling
d1fadd8c5d An 'unreachable' shouldn't have a '0 &&' prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119762 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:05:15 +00:00
Bill Wendling
50d0f58944 Add support for parsing the writeback ("!") token. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:43:05 +00:00
Jason W Kim
837caa9313 Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM. 
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:37:15 +00:00
Owen Anderson
71c11825bf Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:29:56 +00:00
Anton Korobeynikov
d9e3385ced Move getInitialFrameState() to TargetFrameInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:25:52 +00:00
Jim Grosbach
75b7b879c0 ARM Encoding information for UXTAH and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:24:22 +00:00
Tanya Lattner
9684a7c128 Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first). 
Added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 22:06:46 +00:00
Bill Wendling
24d22d2764 Don't allocate the SmallVector of Registers. It gets messy figuring out who 
should delete what when the object gets copied around. It's also making valgrind
upset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:50:54 +00:00
Owen Anderson
8ee9779658 Provide Thumb2 encodings for mov's that come from MOVCC SDNodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:46:31 +00:00
Jim Grosbach
c884aff5f4 Add ARM encoding information for LDRH post-increment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119743 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:43:37 +00:00
Anton Korobeynikov
d0c3817669 Move hasFP() and few related hooks to TargetFrameInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:19:35 +00:00
Bob Wilson
d5448bb6e8 Split up ARM LowerShift function. 
This function was being called from two different places for completely
unrelated reasons.  During type legalization, it was called to expand 64-bit
shift operations.  During operation legalization, it was called to handle
Neon vector shifts.  The vector shift code was not written to check for
illegal types, since it was assumed to be only called after type legalization.
Fixed this by splitting off the 64-bit shift expansion into a separate
function.  I don't have a particular testcase for this; I just noticed it
by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:16:28 +00:00
Owen Anderson
612fb5b9a6 More Thumb2 encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119737 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:15:19 +00:00
Owen Anderson
821752e2e6 Fill out the set of Thumb2 multiplication operator encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119733 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 20:32:18 +00:00
Bill Wendling
707120047e Missed the _RET versions of LDMIA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 19:44:29 +00:00
Eric Christopher
8b3ca6216d Rewrite stack callee saved spills and restores to use push/pop instructions. 
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.

Adjust all testcases accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119725 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 19:40:05 +00:00
Jim Grosbach
056ab107ff ARMPseudoInst instructions should default to being considered a single 4-byte 
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119713 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 18:01:40 +00:00
Chris Lattner
c146c4d47a trivial QoI improvement. On this invalid input: 
sahf	movl	344(%rdi),%r14d
we used to produce:

t.s:2:1: error: unexpected token in argument list

^

we now produce:
t.s:1:11: error: unexpected token in argument list
sahf	movl	344(%rdi),%r14d
    	    	^

rdar://8581401


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119676 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 02:53:02 +00:00
Rafael Espindola
5c0556341e Change CodeGen to use .loc directives. This produces a lot more readable output 
and testing is easier.  A good example is the unknown-location.ll test that
now can just look for ".loc 1 0 0".  We also don't use a DW_LNE_set_address for
every address change anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119613 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 02:04:25 +00:00
Evan Cheng
5c71c7a137 Silence compiler warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119610 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:43:23 +00:00
Jim Grosbach
1251e1a8df Remove trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:39:50 +00:00
Jim Grosbach
99594eb1de ARM PseudoInst instructions don't need or use an assembler string. Get rid of 
the operand to the pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119607 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:38:26 +00:00
Evan Cheng
1b4886dd00 Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:28:51 +00:00
Jim Grosbach
c6961f140a Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:20:48 +00:00
Jim Grosbach
53694265a9 Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not 
just pretend to be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:15:56 +00:00
Owen Anderson
35141a9ba3 Try again at providing Thumb2 encodings for basic multiplication operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:08:42 +00:00
Jim Grosbach
160f8f0e67 Refactor a few ARM load instructions to better parameterize things and re-use 
common encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 00:46:58 +00:00
Owen Anderson
424216453f Revert r119593 while I figure out my testing disagrees with the buildbot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119597 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 00:42:51 +00:00
Owen Anderson
18333616cd Provide correct Thumb2 encodings for basic multiplication operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119593 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 00:19:10 +00:00
Jim Grosbach
85eb54cf0c Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark 
it as such. Add some encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 23:33:14 +00:00
Owen Anderson
2f7aed39a3 Second attempt at correct encodings for Thumb2 bitfield instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119575 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 22:16:31 +00:00
Jim Grosbach
0129be281e Fix comment typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:57:51 +00:00
Bob Wilson
05646099a0 Change ARMGlobalMerge to keep BSS globals in separate pools. 
This completes the fixes for Radar 8673120.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:25:39 +00:00
Bob Wilson
619a372617 Fix ARMGlobalMerge pass to check if globals are entirely within range. 
It is generally not sufficient to check if the starting offset is in range
of the maximum offset that can be efficiently used for the target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119565 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:25:36 +00:00
Bob Wilson
72831dc905 Change the symbol for merged globals from "merged" to "_MergedGlobals". 
This makes it more clear that the symbol is an internal, compiler-generated
name and gives a little more description about its contents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119564 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:25:33 +00:00
Bob Wilson
edf046716c Fix the ARMGlobalMerge pass to look at variable sizes instead of pointer sizes. 
It was mistakenly looking at the pointer type when checking for the size of
global variables.  This is a partial fix for Radar 8673120.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:25:27 +00:00
Jim Grosbach
f8dabac604 Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly 
in the MC lowering process.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119559 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:05:55 +00:00
Evan Cheng
6b19491468 Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119558 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:56:30 +00:00
Owen Anderson
5aba9f694f Revert r119551, which broke buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119555 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:48:51 +00:00
Owen Anderson
23465a06f4 Provide Thumb2 encodings for bitfield instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119551 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:35:29 +00:00
Evan Cheng
c4af4638df Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, 
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:13:28 +00:00
Rafael Espindola
f2dc4aa562 make isVirtualSection a virtual method on MCSection. Chris' suggestion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119547 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:03:54 +00:00
Owen Anderson
46c478e802 More miscellaneous Thumb2 encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119546 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 19:57:38 +00:00
Bill Wendling
df8d94da01 Add missing opcodes now that this function's used in more than one place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119539 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 19:16:20 +00:00
Jim Grosbach
89e14c7579 More ARM encoding bits. LDRH now encodes properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 18:11:11 +00:00
Evan Cheng
baa45f7298 Revert r119109 for now. It's breaking 176.gcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 09:31:04 +00:00
Che-Liang Chiou
3f409f7fef Add simple arithmetics and %type directive for PTX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119485 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 08:08:49 +00:00
Evan Cheng
3642e64c11 Simplify code that toggle optional operand to ARM::CPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119484 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 08:06:50 +00:00
Chris Lattner
b75c651e22 tidy up 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119462 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 05:41:32 +00:00
Bill Wendling
2567eec423 The machine instruction no longer encodes the submode as a separate operand. We 
should get the submode from the load/store multiple instruction's opcode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 05:31:09 +00:00
Bill Wendling
0f63075613 Proper encoding for VLDM and VSTM instructions. The register lists for these 
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 04:32:08 +00:00
Bill Wendling
6bc105a7b9 Add binary emission stuff for VLDM/VSTM. This reuses the 
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 00:45:23 +00:00
Bill Wendling
3380f6a4d0 Use the correct variable names so that the encodings will be correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 23:44:49 +00:00
Dan Gohman
742bf87efa Reapply r118917. With pseudo-instruction expansion moved to 
a different pass, the complicated interaction between cmov expansion
and fast isel is no longer a concern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119400 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 22:43:23 +00:00
Oscar Fuentes
975176e5c6 Fix assembling X86CompilationCallback_Win64.asm on VS 10. 
Patch by Louis Zhuang!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 22:07:47 +00:00
Rafael Espindola
af6b580875 Add .loc methods to the streamer. 
Next: Add support for the !HasDotLocAndDotFile case to the MCAsmStreamer
and then switch codegen to use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 21:20:32 +00:00