when an implicitely defined register is later used by an alias. For example:
call foo
%reg1024 = mov %AL
The call implicitely defines EAX but only AL is used. Before this fix
no information was available on AL. Now EAX and all its aliases except
AL get defined and die at the call instruction whereas AL lives to be
killed by the assignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10813 91177308-0d34-0410-b5e6-96231b3b80d8
LiveVariables::HandlePhysRegDef private they use information that is
not in memory when LiveVariables finishes the analysis.
Also update the TwoAddressInstructionPass to not use this interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10755 91177308-0d34-0410-b5e6-96231b3b80d8
This should get hunked over to the Sparc backend, along with
MachineCodeForInstruction and a bunch of files in include/llvm/Codegen,
but those battles will have to wait for a later time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10731 91177308-0d34-0410-b5e6-96231b3b80d8
of the register allocator as follows:
before after
mesa 2.3790 1.5994
vpr 2.6008 1.2078
gcc 1.9840 0.5273
mcf 0.2569 0.0470
eon 1.8468 1.4359
twolf 0.9475 0.2004
burg 1.6807 1.3300
lambda 1.2191 0.3764
Speedups range anyware from 30% to over 400% :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10712 91177308-0d34-0410-b5e6-96231b3b80d8
A = B op C where A == C, but this cannot really occur in practice
because of SSA form. Add an assert to check that just to be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10682 91177308-0d34-0410-b5e6-96231b3b80d8
saved register it has a longer free range than ECX (which is defined
every time there is a fnuction call) which makes ECX a better register
to reserve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10635 91177308-0d34-0410-b5e6-96231b3b80d8
which denotes the register we would like to be assigned to (virtual or
physical). In register allocation, if this hint exists and we can map
it to a physical register (it is either a physical register or it is a
virtual register that already got assigned to a physical one) we use
that register if it is available instead of a random one in the free
pool.
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with live intervals was missing registers that were used before they
were defined (in the arbitrary order live intervals numbers
instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10603 91177308-0d34-0410-b5e6-96231b3b80d8
nesting level when computing it. Right now the allocator uses:
w = sum_over_defs_uses( 10 ^ nesting level );
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10569 91177308-0d34-0410-b5e6-96231b3b80d8
* Move sparc specific code out of generic code
* Eliminate the getOffset() method which made INVALID_FRAME_OFFSET
necessary, which made pulling in MAX_INT as a sentinal necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10553 91177308-0d34-0410-b5e6-96231b3b80d8
instruction pass. This also fixes all remaining bugs for this new
allocator to pass all tests under test/Programs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10515 91177308-0d34-0410-b5e6-96231b3b80d8
more operands and the two first operands are constrained to be the
same. The pass takes an instruction of the form:
a = b op c
and transforms it into:
a = b
a = a op c
and also preserves live variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10512 91177308-0d34-0410-b5e6-96231b3b80d8
killing instruction is tracked. This causes the LiveIntervals to
create bogus intervals. The workaound is to add a range to the
interval from the redefinition to the end of the basic block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10510 91177308-0d34-0410-b5e6-96231b3b80d8
Move some of the longer LiveIntervals::Interval method out of the
header and add debug information to them. Fix bug and simplify range
merging code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10509 91177308-0d34-0410-b5e6-96231b3b80d8
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8
bug where spill instructions were added to the next basic block
instead of the end of the current one if the instruction that required
the spill was the last in the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10272 91177308-0d34-0410-b5e6-96231b3b80d8
externally-visible linkage, and SaveStateToModule must default to true for llc.
I don't remember why I made it const; perhaps it should be deconstified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9858 91177308-0d34-0410-b5e6-96231b3b80d8
each instruction produces as "operand" -1, and the other operands as 0
.. n, as before. PhyRegAlloc::saveState() is refactored into
PhyRegAlloc::saveStateForValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9842 91177308-0d34-0410-b5e6-96231b3b80d8
implementing verifySavedState().
In saveState(), use the new AllocInfo::AllocStateTy enum, and increment
Insn each time through the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9617 91177308-0d34-0410-b5e6-96231b3b80d8
Prototype option to save state in a global instead of as a Constant in
the Module. (Turned off, for now, with the on/off switch welded in the off
position. You get the idea.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9500 91177308-0d34-0410-b5e6-96231b3b80d8
Make FnAllocState contain vectors of AllocInfo, instead of LLVM Constants.
Give doFinalization a method comment, and let it do the work of converting
AllocInfos to LLVM Constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9451 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix order of #includes
* Make code layout more consistent
* Eliminate extraneous whitespace and comment-lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9433 91177308-0d34-0410-b5e6-96231b3b80d8
* Make file description more readable
* Make code layout more consistent, include comment in assert so it's visible
during execution if it hits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9430 91177308-0d34-0410-b5e6-96231b3b80d8
Try to improve method comments a little.
Get rid of some excess whitespace; put braces on previous line when possible.
Add stub for method to verify the work of saveState().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9385 91177308-0d34-0410-b5e6-96231b3b80d8
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:
if (const unsigned* AS = TID.ImplicitDefs) {
for (int i = 0; AS[i]; ++i) {
// use AS[i]
}
}
was changed to:
for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
// use *AS
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8960 91177308-0d34-0410-b5e6-96231b3b80d8
Shorten the markSuggestedColorUsable method.
Add a switch for saving reg. alloc. state (coming soon).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8697 91177308-0d34-0410-b5e6-96231b3b80d8
(I also zapped printMachineCode() and printLabel() at the previous checkin,
but forgot to mention it.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8646 91177308-0d34-0410-b5e6-96231b3b80d8
PhyRegAlloc.cpp:
Don't include TargetMachine.h or TargetRegInfo.h, because these are provided
by PhyRegAlloc.h.
Merge class RegisterAllocator into class PhyRegAlloc.
Simplify & move ctor, dtor to PhyRegAlloc.h.
Make some of PhyRegAlloc's reference members into pointer members,
so they can be more easily messed with.
MarkAllocatedRegs() becomes a member method, with fewer args.
PhyRegAlloc.h:
Include Pass.h, TargetMachine.h and TargetRegInfo.h. Don't declare
TargetRegInfo forward.
Give AddedInstrns the obvious clear() method.
Make some of PhyRegAlloc's reference members into pointer members,
so they can be more easily messed with.
Add prototype for markAllocatedRegs().
Remove unused inline void constructLiveRanges().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8641 91177308-0d34-0410-b5e6-96231b3b80d8
we no longer need to find the live-before set of the delayed
branch since that set is now included the live-before/after
set of the instructions in each delay slot. Just assert that instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7796 91177308-0d34-0410-b5e6-96231b3b80d8
so get rid of the def/use parameters that were getting passed in.
**** This now changes the semantics of these methods to preserve the flags,
not clobber them!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7602 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a lot more DEBUG output, which is better structured than before
* Fix bug: Jello/2003-08-04-PhysRegLiveFailure.llx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7583 91177308-0d34-0410-b5e6-96231b3b80d8
spilling values used by an instruction in the delay slot of the branch
(which will eventually be moved before the branch).
2. Bug fix: Delete the delay slot instr, not the branch instr, when
moving delay slot instr. out!!!!
3. Move code to insert caller-saves moved here from SparcRegInfo:
it is now machine-independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7389 91177308-0d34-0410-b5e6-96231b3b80d8
machine-independent.
Fix problem with using branch operand reg. as temp. reg. when
spilling values used by an instruction in the delay slot of the branch
(which will eventually be moved before the branch).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7385 91177308-0d34-0410-b5e6-96231b3b80d8
info (since multiple reg types may share the same reg class).
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7329 91177308-0d34-0410-b5e6-96231b3b80d8
found to consider regType info (since multiple reg types may share
the same reg class, e.g., single and double on Sparc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7327 91177308-0d34-0410-b5e6-96231b3b80d8
(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same
register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7152 91177308-0d34-0410-b5e6-96231b3b80d8
not just an Instruction*, at least in one unfortunate case:
the first operand to the va_arg instruction.
Modify ValueToDefVecMap to map from Value*, not Instruction*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7052 91177308-0d34-0410-b5e6-96231b3b80d8
SETTING the operand to be an immediate or have verified that one of the operands
is really a SignExtended or Unextended immediate value already, which warrants
an 'i' opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6662 91177308-0d34-0410-b5e6-96231b3b80d8
the loop, and in both cases. In the first case, it is a VReg that is a constant
so it may be actually converted to a constant. In the second case, it is already
a constant, but then if it doesn't change its type (e.g. to become a register
and have the value loaded from memory if it is too large to live in its
instruction field), we must change the opcode BEFORE the 'continue', otherwise
we miss the opportunity.
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This pass should be moved to lib/Target/Sparc since it's sparc specific
It also needs a file comment.
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In particular these classes are the last that link the noncopyable classes
with the hash_map, vector, and list classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6552 91177308-0d34-0410-b5e6-96231b3b80d8
TmpInstruction constructors because every TmpInstruction object has
to be registered with a MachineCodeForInstruction to prevent leaks.
This simplifies the user's code.
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preallocated. While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.
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call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
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and passes the real code to a memory-outputting code emitter. This may be
removed at a later point in development.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6379 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
* *** Finally mark values that are inputs to PHIs as killed when appropriate.
This should make the generated code quite a bit better. For example, the
local-ra will not have to spill PHI inputs at the end of predecessor BB's
anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6117 91177308-0d34-0410-b5e6-96231b3b80d8
* Change getVarInfo to take real virtual register numbers and offset them
itself. This has caused me so much grief, it's not even funny.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6115 91177308-0d34-0410-b5e6-96231b3b80d8
look nicer and removed useless stuff.
Also renamed a few variables, moved them into namespaces, converted outputting
to a file into a print to std::cerr with a DEBUG() guard, as all passes should
do anyway.
No functional changes have been made. However, this code now compiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5769 91177308-0d34-0410-b5e6-96231b3b80d8
* Lines must be wrapped at 80 chars. This is a hard limit.
* Consistent style on functions, braces, if, for, etc. Code must be readable.
No functional changes have been made, even though I added a new typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5768 91177308-0d34-0410-b5e6-96231b3b80d8
