Chris Lattner
f3231de60b
arm only needs to emit one .align directive for hidden nlp's, not one
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per pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 18:02:16 +00:00
Chris Lattner
c076a97939
make sure that arm nonlazypointers are aligned properly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78573 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 18:01:34 +00:00
Chris Lattner
e1e8a82986
Fix a weird ppc64-specific link error during an llvm-gcc build:
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ld: bad offset (0x00000091) for lo14 instruction pic-base fix-up in ___popcountdi2 from libgcc/./_popcountsi2_s.o
The problem is that the non lazy symbol pointers need to be 8 byte aligned
on ppc64 and .section doesn't have an implicit alignment like ".non_lazy_symbol_pointer"
does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78572 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 17:58:51 +00:00
Chris Lattner
12b2bda61a
fix some warnings for the MSVC build, by Yonggang Luo!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78571 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 17:35:42 +00:00
David Goodwin
bcf81629b8
Checkpoint scheduling itinerary changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 15:56:13 +00:00
Evan Cheng
65f2e7887a
Watch out for empty BB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78562 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 08:10:13 +00:00
Evan Cheng
8442d00a0e
rev, rev16, and revsh do not set CPSR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78561 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 07:58:45 +00:00
Evan Cheng
0d3007bb32
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 07:20:37 +00:00
Evan Cheng
26cc252a43
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78559 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 06:57:42 +00:00
Evan Cheng
19068ba71a
Add support for folding loads / stores into 16-bit moves used by Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78558 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 06:32:05 +00:00
Evan Cheng
2294645642
80 col violation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78557 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 05:51:48 +00:00
Evan Cheng
052053bbe3
Use tMOVgpr2gpr instead of t2MOVr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78556 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 05:49:43 +00:00
Evan Cheng
e8af1f9afe
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 02:37:24 +00:00
Evan Cheng
09d97354ed
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78549 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 02:06:53 +00:00
Chris Lattner
ff4bc460c5
Make the big switch: Change MCSectionMachO to represent a section *semantically*
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instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78547 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 01:39:42 +00:00
Benjamin Kramer
c6ca847a4e
Use abs64 instead abs; some platforms don't have a 64-bit abs overload. Noticed by Yonggang Luo!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78543 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 22:37:07 +00:00
Evan Cheng
a56c57e5f0
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78540 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 19:17:19 +00:00
Daniel Dunbar
5fe6338ac8
llvm-mc/AsmParser: Implement user defined super classes.
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- We can now discriminate SUB32ri8 from SUB32ri, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 07:20:21 +00:00
Daniel Dunbar
98164afb01
Extend comment on ParserMatchClass .td field, and add some missing
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classes for X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78524 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 06:00:04 +00:00
Daniel Dunbar
6745d42e8e
llvm-mc/AsmParser: Define match classes in the .td file.
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-2 FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78523 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 05:18:30 +00:00
Chris Lattner
93b6db3de9
sink the 'name' and 'isdirective' state out of MCSection into its derived classes.
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This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 23:39:42 +00:00
Anton Korobeynikov
8e9ece75db
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 23:10:41 +00:00
Chris Lattner
ba44633a3b
add a note about dead zero extends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78511 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 22:46:59 +00:00
Chris Lattner
892e182393
1. Make MCSection an abstract class.
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2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 22:41:53 +00:00
Eric Christopher
b4dc13cab7
Add crc32 instruction and intrinsics. Add a new class of prefix
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bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
New test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 21:55:08 +00:00
Jakob Stoklund Olesen
46151de6a0
Add support for READCYCLECOUNTER in Blackfin back-end.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78506 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 21:42:22 +00:00
Chris Lattner
f7427e558d
add new PIC16Section class, this time hopefully not breaking the build :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78505 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 21:37:01 +00:00
Daniel Dunbar
245f05843f
llvm-mc/AsmMatcher: Switch token matching to use the new string matcher.
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Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78504 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 21:22:41 +00:00
Daniel Dunbar
fb373909be
Revert r78501, it doesn't build.
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--- Reverse-merging r78501 into '.':
U lib/Target/PIC16/PIC16TargetObjectFile.cpp
D lib/Target/PIC16/PIC16Section.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78503 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 21:12:40 +00:00
Chris Lattner
50e38121d1
make PIC16 create its own custom MCSection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78501 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:55:25 +00:00
Chris Lattner
7c599d056a
make target-specific TLOF impls (except PIC16) create target-specific
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MCSection instances.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78500 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:52:13 +00:00
Chris Lattner
5277b22687
eliminate TargetLoweringObjectFileSparc in favor of a TAI hook.
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A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78498 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:43:12 +00:00
Chris Lattner
9aee18186c
give pic16 a target-specific section creation name too
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78496 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:23:47 +00:00
Chris Lattner
0c0cb71233
now that getOrCreateSection is all object-file specific,
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give the impls an object-file-specific name. In the future
they can take different arguments etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78495 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:22:20 +00:00
Chris Lattner
fbf1d271e6
sink getOrCreateSection down into all the object file implementations,
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now that they create *all* the sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:14:13 +00:00
Bruno Cardoso Lopes
71435a3975
Use reloc_absolute_word_sext relocation for X86::MOV64(ri/mi)32 instructions,
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since they are in 64 bit mode with i64immSExt32 imms. JIT is not affected since
it handles both word absolute relocations in the same way
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78479 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 17:47:41 +00:00
Daniel Dunbar
cf1e764a1c
Update CMake
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78475 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 17:03:13 +00:00
Anton Korobeynikov
06af2ba809
Add insert_elt / extract_elt patterns for v4f32 stuff.
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Did anyone tests v4f32 ever?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78470 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 14:06:07 +00:00
Anton Korobeynikov
3405201bce
Lane number should be printed w/o hash
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78469 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 14:05:53 +00:00
Anton Korobeynikov
baf31088f1
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 13:35:48 +00:00
Andrew Lenharth
20c08e534f
move this fp select into a pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78464 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 12:49:07 +00:00
Daniel Dunbar
a3741fa28b
llvm-mc/AsmMatcher: Improve match code.
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- This doesn't actually improve the algorithm (its still linear), but the
generated (match) code is now fairly compact and table driven. Still need a
generic string matcher.
- The table still needs to be compressed, this is quite simple to do and should
shrink it to under 16k.
- This also simplifies and restructures the code to make the match classes more
explicit, in anticipation of resolving ambiguities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78461 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 07:50:56 +00:00
Bob Wilson
b6ab51e829
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
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so I generalized the class for VTRN in the .td file to handle all 3 of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 06:13:25 +00:00
Bob Wilson
64efd90f8c
Implement Neon VTRN instructions. For now, anyway, these are selected
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directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 05:53:00 +00:00
Evan Cheng
3eff16e27a
Add a skeleton Thumb2 instruction size reduction pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78456 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 03:21:23 +00:00
Evan Cheng
8fb903604e
Code refactoring. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 03:20:32 +00:00
Evan Cheng
57834cdee5
tADDhirr should target GPR, not tGPR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78454 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 03:19:44 +00:00
Evan Cheng
34f8a029e3
I can type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78453 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 02:54:37 +00:00
Chris Lattner
41aefdcdd1
make printInstruction return void since its result is omitted. Make the
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error condition get trapped with an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78449 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 01:32:19 +00:00
Chris Lattner
2698cb6811
don't check the result of printInstruction anymore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78444 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 00:05:42 +00:00
Anton Korobeynikov
941222eea0
Do not generate 32-bit call on win64 when imm does not fit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78443 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 23:59:21 +00:00
David Goodwin
767a952a6f
Make NEON single-precision FP support the default for cortex-a8 (again).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 23:32:33 +00:00
Chris Lattner
db0a9706e7
remove a bunch of now-dead crud from the asmprinter and TAI interfaces.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 23:16:27 +00:00
Anton Korobeynikov
a55fd4a23f
Unbreak the stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 22:51:13 +00:00
Andrew Lenharth
7116b7bb0c
avoid this libcall with long inline expansion
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78420 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 22:37:20 +00:00
Anton Korobeynikov
32a1b25781
2 more vdup.32 cases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 22:36:50 +00:00
Evan Cheng
fcc716352b
A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78418 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 22:36:37 +00:00
Bill Wendling
1232167ce3
Reformatting of lines. Put multiple DEBUG statements under one DEBUG statement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78411 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 21:33:25 +00:00
Evan Cheng
d77c7aba83
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78410 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 21:19:10 +00:00
Daniel Dunbar
2724915c17
llvm-mc/AsmMatcher: Tweaks in response to feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 20:33:39 +00:00
Evan Cheng
f12288e8aa
This is done.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78399 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 19:34:52 +00:00
Evan Cheng
e118cb6146
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78398 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 19:34:35 +00:00
Evan Cheng
1d2426c470
Fix support to use NEON for single precision fp math.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 19:30:41 +00:00
Sanjiv Gupta
394a1a21a1
Minor fixes to avoid using invalid debugloc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78383 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 11:00:02 +00:00
Benjamin Kramer
b8d222def1
Simplify code and avoid allocations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78382 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 10:42:28 +00:00
Daniel Dunbar
6812cd18aa
Improve disabling of X86 AsmMatcher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 09:06:38 +00:00
Daniel Dunbar
7ddca30f31
Disable X86 AsmMatcher for now, it is causing gcc-4.0 to run out of memory on
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i386-apple-darwin9. This presumably will get fixed once the generated code
improves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 08:45:03 +00:00
Daniel Dunbar
20927f26fc
llvm-mc/AsmMatcher: Move to a slightly more sane matching design.
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- Still not very sane, but a least its not 60k lines on X86. :)
- In terms of correctness, currently some things are hard wired for X86, and we
still don't properly resolve ambiguities (this is ignoring the instructions
we don't even match due to funny .td stuff or other corner cases).
The high level changes:
1. Represent tokens which are significant for matching explicitly as separate
operands. This uniformly handles not only the instruction mnemonic, but
also 'signficiant' syntax like the '*' in "call * ...".
2. Separate the matching of operands to an instruction from the construction of
the MCInst. In theory this can be done during matching, but since the number
of variations is small I think it makes sense to decompose the problems.
3. Improved a few of the mechanisms to at least successfully flatten / tokenize
the assembly strings for PowerPC and ARM.
4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
moving towards for handling ambiguous instructions. The high-bit is to infer
a partial ordering of the operand classes (and force the user to specify one
if we can't) and use that to resolve ambiguities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78378 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 08:26:05 +00:00
Evan Cheng
b6879b2b84
Error out, rather than infinite looping, if constant island pass can't converge.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78377 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 07:35:21 +00:00
Evan Cheng
53c67c0218
tBfar is bl, which clobbers LR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78370 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 05:45:07 +00:00
Sanjiv Gupta
85019e15eb
Run memsel inserter just before emit assembly to avoid tinkering by other passes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78369 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 05:44:27 +00:00
Andrew Lenharth
a3c6073fd3
These should be expanded
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78365 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 02:17:44 +00:00
Dan Gohman
7db949df78
Fix a bunch of namespace pollution.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 01:32:21 +00:00
Evan Cheng
861986401e
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 00:34:42 +00:00
Nicolas Geoffray
6f62cffd63
Output the new StructType constructor, which takes the context of the
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module as first argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78340 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 21:31:35 +00:00
Devang Patel
2251666d44
Use DebugInfoFinder
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78334 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 20:53:24 +00:00
Bob Wilson
b36ec86c01
Implement Neon VST[234] operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 18:47:44 +00:00
David Goodwin
8b7d7ade85
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 16:52:47 +00:00
Chris Lattner
24f654c8a4
Fix several fixmes and clean up code by sinking *all* section
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creation activity into the target-specific subclasses of TLOF.
Before this, globals with explicit sections could be created by
the base class.
1. make getOrCreateSection protected, add a new getExplicitSectionGlobal
pure virtual method to assign sections to globals with a specified
section.
2. eliminate getSpecialCasedSectionGlobals, which is now PIC specific.
3. eliminate the getKindForNamedSection virtual method, which is
now just a static method for ELF.
4. Add implementions of getExplicitSectionGlobal for ELF/PECOFF/Darwin/PIC16.
They are now all detangled and understandable, woo! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78319 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 16:39:58 +00:00
Chris Lattner
759b88898d
go through PIC16TargetObjectFile to make sections instead of
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creating them directly in the pic16 asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78317 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 16:27:28 +00:00
Anton Korobeynikov
d7697d0167
We need to sext global addresses in kernel code model, not zext
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78299 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 11:23:24 +00:00
Dan Gohman
aae317ac32
Fix a bug in x86's PreprocessForRMW logic that was exposed
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by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78297 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 09:22:57 +00:00
Anton Korobeynikov
186fa1d0df
Missed part of recent kernel codemodel tweaks
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 09:11:19 +00:00
Bob Wilson
0cedab9a0d
Neon does not actually have VLD{234}.64 instructions.
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These operations will have to be synthesized from other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 00:24:27 +00:00
Bob Wilson
70cd88fb7b
Add a new pre-allocation pass to assign adjacent registers for Neon instructions
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that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78256 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 23:12:45 +00:00
Anton Korobeynikov
b5e0172405
Better handle kernel code model. Also, generalize the things and fix one
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subtle bug with small code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78255 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 23:01:26 +00:00
Dan Gohman
59e34921a5
Use GR32 for copies between GR32_NOSP and GR32_NOREX, as neither
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is a subset of the other, but both are subsets of GR32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78250 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 22:18:26 +00:00
David Goodwin
7bfdca0206
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 21:02:22 +00:00
Chris Lattner
cafbdc5c09
remove the 'DataSectionStartSuffix' and 'TextSectionStartSuffix' knobs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78242 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 20:49:52 +00:00
Anton Korobeynikov
058c251d4a
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
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hardfloat case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 20:15:19 +00:00
Dan Gohman
be0cf7dbc2
hasSuperClass tests for a strict superset relation, rather than
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a superset relation. This code wants to test the regular superset
relation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 20:13:45 +00:00
Anton Korobeynikov
14d9495403
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78232 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 19:40:16 +00:00
Anton Korobeynikov
567d14f07c
Missed pieces for ARM HardFP ABI.
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Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78225 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 19:04:42 +00:00
Andrew Lenharth
7f285c8024
Use elf Object File directly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78220 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 18:13:04 +00:00
Daniel Dunbar
e22f4da01d
Remove some dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78219 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 18:12:37 +00:00
Dan Gohman
74f6f9a931
Enable the new no-SP register classes by default. This is to address
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PR4572. A few tests have some minor code regressions due to different
coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78217 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 17:40:24 +00:00
Bob Wilson
7f0f2515a0
Remove a redundant declaration.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78216 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 17:39:44 +00:00
Anton Korobeynikov
9e155d61da
Convert bswap test to filecheck, add more test entries & convert stuff to filecheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78212 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 16:50:53 +00:00
Dan Gohman
22f7d57dde
Fix a bug in the PIC16 backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78211 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 16:46:43 +00:00
David Goodwin
ce3c1f2a0e
Disable NEON single-precision FP support for Cortex-A8, for now...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 16:40:57 +00:00
Devang Patel
bccdcb1857
Remove dead code. MDNode and MDString are not Constant anymore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78207 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 16:40:02 +00:00
Anton Korobeynikov
93e21f7b6f
Add memory versions of some instructions.
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Patch by Neale Ferguson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78203 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 16:16:11 +00:00
David Goodwin
1f0e404c87
By default, for cortex-a8 use NEON for single-precision FP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 16:01:19 +00:00
Anton Korobeynikov
1e0039d6cf
Special constants as destinations does not work as expected - drop the patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78191 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 14:42:00 +00:00
Andrew Lenharth
1ad11a896c
Alpha: Get section directives right
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78189 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 13:59:57 +00:00
Anton Korobeynikov
0802a1e1e8
Cleanup in dbg_stoppoint handling in CBE. Patch by Sandeep Patel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78182 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 09:31:40 +00:00
Anton Korobeynikov
e392c8336f
Minor arm CBE fixes. Patch by Sandeep.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78181 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 09:31:07 +00:00
Anton Korobeynikov
e641b527e8
Emit module-level inline asm for CBE.
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Patch by Sandeep Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78180 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 09:29:56 +00:00
Bruno Cardoso Lopes
52d0851446
- Remove custom handling of jumptables by the elf writter (this was
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a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78176 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 06:57:03 +00:00
Evan Cheng
61f4b721b2
80 col violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78175 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 06:41:25 +00:00
Dan Gohman
c3c9c486e4
Teach X86FastISel how to handle CCValAssign::BCvt, which is used for
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MMX arguments. This fixes PR4684.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78163 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 05:33:42 +00:00
Chris Lattner
26d054d903
Clarify common linkage and the requirements on it. Enforce
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them in the verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78160 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 05:21:07 +00:00
Chris Lattner
58bed8fc29
expose SectionKindForGlobal to curious clients, named as
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getKindForGlobal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78156 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 04:25:40 +00:00
Bob Wilson
aa289d5e7f
Oops. I didn't mean to commit this piece yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78146 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 02:47:13 +00:00
Dan Gohman
98ca4f2a32
Major calling convention code refactoring.
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Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
Dan Gohman
5b0d72e850
Remove an unnecessary flush in the CppBackend's output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78138 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:06:38 +00:00
Dan Gohman
1c55fab534
Don't flush the raw_ostream between each MachineFunction. These flush
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calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78137 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 00:49:25 +00:00
Bob Wilson
4a3d35abef
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
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Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 00:49:09 +00:00
Bruno Cardoso Lopes
e55fef36a9
1) Proper emit displacements for x86, using absolute relocations where necessary
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for ELF to work.
2) RIP addressing: Use SIB bytes for absolute relocations where RegBase=0,
IndexReg=0.
3) The JIT can get the real address of cstpools and jmptables during
code emission, fix that for object code emission
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78129 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 00:11:21 +00:00
Evan Cheng
35d6c41fde
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 23:47:55 +00:00
Bob Wilson
c00479253b
Replace dregsingle operand modifier with explicit escaped curly brackets.
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For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 21:39:33 +00:00
Mike Stump
4dcff6db72
Restlyize to match other targets, fixes cmake build to boot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78105 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 21:27:06 +00:00
Evan Cheng
9e7a312391
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 21:12:13 +00:00
Chris Lattner
275bb1bd12
remove a random reference to subtarget. Even without this, we
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still get "intel syntax" instructions from llc with
-x86-asm-syntax=intel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78103 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 21:12:08 +00:00
David Goodwin
53e4471adc
Add NEON single-precision FP support for fabs and fneg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 20:39:05 +00:00
Chris Lattner
f9c1ccf280
rip out SectionEndDirectiveSuffix support, only uses by
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the masm backend. If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78096 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 20:09:41 +00:00
Jakob Stoklund Olesen
71d342e854
Most flags are reserved registers on Blackfin.
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The only exception is CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78089 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 19:16:55 +00:00
Evan Cheng
3425df44b5
In thumb mode, r7 is used as frame register. This fixes pr4681.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 18:46:17 +00:00
David Goodwin
b84f3d427c
Match common pattern for FNMAC. Add NEON SP support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 18:44:29 +00:00
Sanjiv Gupta
ada097a853
Legalize i64 store operations generated by inst-combine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78082 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 17:59:16 +00:00
David Goodwin
42a83f2d15
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 17:53:06 +00:00
Daniel Dunbar
7145e9be64
Avoid compiler warning (in -Asserts mode)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78070 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 16:46:12 +00:00
Chris Lattner
ec409759e9
enhance codegen to put 16-bit character strings into the
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__TEXT,__ustring section on darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78068 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 16:27:13 +00:00
Chris Lattner
7e88a50428
fix a fixme: don't create an explicit "CStringSection" for ELF,
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it is just being used as a prefix, so forward substitute it directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 16:19:50 +00:00
Chris Lattner
1850e5add1
Add support emiting for 2/4 byte mergable strings to the ".rodata.str*"
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section on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78066 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 16:13:09 +00:00
Anton Korobeynikov
939ba32747
Ooops, I was too fast to commit the wrong fix :(
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78060 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 11:18:31 +00:00
Anton Korobeynikov
20e037a8c5
Fix a typo - this unbreaks llvm-gcc build on arm
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78059 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 11:12:51 +00:00
Evan Cheng
eb084d1671
Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78057 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 08:34:18 +00:00
Chris Lattner
3b24c01720
make MergeableCString be a SectionKind "abstract class", and
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add new concrete versions for 1/2/4-byte mergable strings.
These are not actually created yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78055 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 05:35:56 +00:00
Daniel Dunbar
4b3d57228c
No really, it's unused.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78047 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 04:08:40 +00:00
Daniel Dunbar
214e22396f
Remove now unused Module argument to createTargetMachine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78043 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 04:02:45 +00:00
Evan Cheng
f0409ea488
Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78032 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 01:56:09 +00:00
Evan Cheng
27934da97b
Load / store multiple pass fixes for Thumb2. Not enabled yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78031 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 01:43:45 +00:00
Evan Cheng
fa2ea1a8cf
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 01:41:15 +00:00
Bob Wilson
a599bff101
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
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results to fixed registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78025 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 00:36:16 +00:00
Bob Wilson
916afdbc2d
Minor cleanup. No functional changes intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 00:25:01 +00:00
Ted Kremenek
f6e75c3435
Update CMake files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78020 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 23:44:01 +00:00
Chris Lattner
7b59e2493d
remove an unneeded section switch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78014 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 23:02:45 +00:00
Chris Lattner
2dfddee396
switch ppc to using SwitchToSection instead of textual section stuff.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78013 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 22:52:21 +00:00
Chris Lattner
5e44e472d6
use TLOF to compute the section for a function instead of
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replicating the logic manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78011 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 22:32:50 +00:00