Commit Graph

10440 Commits

Author SHA1 Message Date
Bill Wendling
8b4b874cc6 Match this pattern so that we can generate simpler code:
%a = ...
  %b = and i32 %a, 2
  %c = srl i32 %b, 1
  %d = br i32 %c, 

into

  %a = ...
  %b = and %a, 2
  %c = X86ISD::CMP %b, 0
  %d = X86ISD::BRCOND %c ...

This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 01:47:50 +00:00
Bill Wendling
bddc442a00 Doxygen-ify comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67727 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 01:46:56 +00:00
Gabor Greif
0c8f7dc67c do not rely on callee being operand 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67681 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25 06:32:59 +00:00
Evan Cheng
42bf74be14 CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25 01:47:28 +00:00
Evan Cheng
7db860d4de Don't print global names twice with -asm-verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67667 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25 01:08:42 +00:00
Dan Gohman
a96dc14968 I was convinced that it's ok to allow a second i8 return value
to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67588 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24 01:04:34 +00:00
Evan Cheng
f1c0ae9de5 Do not emit comments unless -asm-verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24 00:17:40 +00:00
Dale Johannesen
1b25cb2416 Fix internal representation of fp80 to be the
same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67562 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 21:16:53 +00:00
Dan Gohman
f871ccb853 Now that errs() is properly non-buffered, there's no need to
explicitly flush it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67526 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 15:57:19 +00:00
Dan Gohman
2004eb6272 Correct some comments. Operand numbers start at 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 15:40:10 +00:00
Evan Cheng
fb11288109 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 08:01:15 +00:00
Dan Gohman
3aff0a63f9 Fix a grammaro in a comment that Bill noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 05:02:44 +00:00
Dan Gohman
82f84159e0 Add comments explaining why there's only one register for
i8 return values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 04:28:24 +00:00
Bruno Cardoso Lopes
bdfbb74d34 Removed AFGR32 register class
Handle odd registers allocation in FGR32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-21 00:05:07 +00:00
Bob Wilson
2a14c521ca Fix a few more indentation problems and an 80-column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67416 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20 23:16:43 +00:00
Bob Wilson
2dc4f54324 No functional changes. Fix indentation and whitespace only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67412 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20 22:42:55 +00:00
Sanjiv Gupta
e9d81f0ad8 Fixed comment for libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67373 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20 14:10:20 +00:00
Sanjiv Gupta
6b830e6d0d Reformatting. Inserted code comments. Cleaned interfaces.
Removed unncessary code. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20 13:42:20 +00:00
Mon P Wang
bc65ca8de5 Added option to enable generating less precise mad (multiply addition)
for those architectures that support the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20 05:06:58 +00:00
Nick Lewycky
9c0f146d50 Remove strange extra semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67287 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-19 05:51:39 +00:00
Nate Begeman
7cee81703d Add support to tablegen for naming the nodes themselves, not just the operands,
in selectiondag patterns.  This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67286 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-19 05:21:56 +00:00
Bruno Cardoso Lopes
b53db4fb32 Added support for Mips O32 Calling Convention
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67280 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-19 02:12:28 +00:00
Chris Lattner
ff81ebf758 Disable the "call to immediate" optimization on x86-64. It is
not safe in general because the immediate could be an arbitrary
value that does not fit in a 32-bit pcrel displacement.  
Conservatively fall back to loading the value into a register
and calling through it.

We still do the optzn on X86-32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-18 00:43:52 +00:00
Scott Michel
a82d3f7c57 CellSPU:
Revert inadvertent mis-fix of fneg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67084 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 16:45:16 +00:00
Dan Gohman
9626447e70 Recognize bswapl as bswap too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67072 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 02:45:40 +00:00
Dan Gohman
d73566609e Recognize "bswapq" as an alternate spelling for the bswap instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67071 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 02:17:27 +00:00
Scott Michel
7ea02ffe91 CellSPU:
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
  to the constant pool when they correspond to SPU's shufb instruction's
  special mask values. This avoids the overhead of performing a shuffle on a
  zero-filled vector just to get the special constant when the memory load
  suffices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 01:15:45 +00:00
Scott Michel
6e1d1470c2 CellSPU:
Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the
llvm-gcc bootstrap a bit further along.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-16 18:47:25 +00:00
Bruno Cardoso Lopes
98ea4635ae This causes incorrect stack frame allocation when the last object is an array allocated on the stack which would lead
the compiled program to run over its stack. Thanks to Gil Dogon


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67034 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-15 23:28:07 +00:00
Dan Gohman
72bb0a64af Use %rip-relative addressing on x86-64 whenever practical, as
it has a smaller encoding than absolute addressing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67002 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-14 02:33:41 +00:00
Dan Gohman
9a49d31b6f Don't forego folding of loads into 64-bit adds when the other
operand is a signed 32-bit immediate. Unlike with the 8-bit
signed immediate case, it isn't actually smaller to fold a
32-bit signed immediate instead of a load. In fact, it's
larger in the case of 32-bit unsigned immediates, because
they can be materialized with movl instead of movq.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67001 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-14 02:07:16 +00:00
Dan Gohman
474d3b3f40 Improve FastISel's handling of truncates to i1, and implement
ptrtoint and inttoptr in X86FastISel. These casts aren't always
handled in the generic FastISel code because X86 sometimes needs
custom code to do truncation and zero-extension.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 23:53:06 +00:00
Dan Gohman
14ea1ec232 Fix FastISel's assumption that i1 values are always zero-extended
by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 20:42:20 +00:00
Rafael Espindola
520ebe6c2f add 8 and 16 bit TLS moves.
add a fixme note on how to remove code duplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66932 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 19:39:55 +00:00
Rafael Espindola
9b922aa3b8 Improve sext and zext of TLS variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66922 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 18:37:06 +00:00
Chris Lattner
44ceb8a341 generalize this code so that fast isel handles integer truncates to i1, which
codegen to the same thing as integer truncates to i8 (the top bits are 
just undefined).  This implements rdar://6667338


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 16:36:42 +00:00
Bill Wendling
105be5ac99 These instructions have special lowering that may lower them to SSE
instructions. Prevent that if we don't want implicit uses of SSE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66877 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 08:41:47 +00:00
Evan Cheng
1606e8e4cd Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.


Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 07:51:59 +00:00
Chris Lattner
cee56e7d33 generalize the previous code to use the full generality of LEA
for i32/i64 expressions (we could also do i16 on cpus where
i16 lea is fast, but I didn't add this).  On the example, we now
generate:

_test:
	movl	4(%esp), %eax
	cmpl	$42, (%eax)
	setl	%al
	movzbl	%al, %eax
	leal	4(%eax,%eax,8), %eax
	ret

instead of:

_test:
	movl	4(%esp), %eax
	cmpl	$41, (%eax)
	movl	$4, %ecx
	movl	$13, %eax
	cmovg	%ecx, %eax
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66869 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 05:53:31 +00:00
Chris Lattner
97a29a5fee optimize the case of cond ? 42 : 41 and friends. This compiles the
example to:

_test:
	movl	4(%esp), %eax
	cmpl	$41, (%eax)
	setg	%al
	movzbl	%al, %eax
	orl	$4294967294, %eax
	ret

instead of:

        movl    4(%esp), %eax
        cmpl    $41, (%eax)
	movl	$4294967294, %ecx
	movl	$4294967295, %eax
	cmova	%ecx, %eax
	ret

which is smaller in code size and faster. rdar://6668608



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 05:22:11 +00:00
Dan Gohman
77502c9344 Enhance address-mode folding of ISD::ADD to handle cases where the
operands can't both be fully folded at the same time. For example,
in the included testcase, a global variable is being added with
an add of two values. The global variable wants RIP-relative
addressing, so it can't share the address with another base
register, but it's still possible to fold the initial add.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66865 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 02:25:09 +00:00
Evan Cheng
a065200eaf Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 18:15:39 +00:00
Chris Lattner
d1980a5acd Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
related transformations out of target-specific dag combine into the
ARM backend.  These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).

Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0  -> (zext(cond) << 3).  This happens frequently
with the recently added cp constant select optimization, but is a
very general xform.  For example, we now compile the second example
in const-select.ll to:

_test:
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        seta    %al
        movzbl  %al, %eax
        movl    4(%esp), %ecx
        movsbl  (%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl    4(%esp), %eax
        leal    4(%eax), %ecx
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        cmovbe  %eax, %ecx
        movsbl  (%ecx), %eax
        ret

This passes multisource and dejagnu.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 06:52:53 +00:00
Chris Lattner
2b9f434908 improve comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 06:46:02 +00:00
Evan Cheng
536e66764b On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66776 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 05:59:15 +00:00
Sanjiv Gupta
054401b9f2 Forgot to check-in this as part of 7761.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66763 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 03:20:07 +00:00
Sanjiv Gupta
d076570a66 Banksel optimization is now based on the section names of symbols, since the symbols in one section will always be put into one bank.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66761 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 02:10:45 +00:00
Dan Gohman
30143763b9 Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the
assembly text output uses an indirect call ("call *") instead of a direct call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66735 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 23:01:47 +00:00
Rafael Espindola
b316f90e57 optimize i8 and i16 tls values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66725 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 22:40:04 +00:00
Bill Wendling
f9abd7e33e Add a -no-implicit-float flag. This acts like -soft-float, but may generate
floating point instructions that are explicitly specified by the user.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 22:30:01 +00:00
Duncan Sands
4dc2b39bf8 It makes no sense to have a ODR version of common
linkage, so remove it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66690 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 20:14:15 +00:00
Mon P Wang
6b3ef693d7 For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66684 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 18:47:57 +00:00
Chris Lattner
eda2ec35a1 fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66660 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 16:14:25 +00:00
Duncan Sands
5f4ee1fc5d Remove the one-definition-rule version of extern_weak
linkage: this linkage type only applies to declarations,
but ODR is only relevant to globals with definitions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66650 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 08:08:06 +00:00
Mon P Wang
37b9a19653 Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66645 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 06:35:11 +00:00
Chris Lattner
47b4ce8529 formatting change, reduce indentation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 05:48:52 +00:00
Sanjiv Gupta
c29f0c7dde Mark the Defs and Uses of STATUS register correctly, plus some reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66540 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-10 10:35:34 +00:00
Dan Gohman
3328adda6b Add more information to the EFLAGS note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66515 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-10 00:26:23 +00:00
Dan Gohman
ad93e1e5fc Add a note about EFLAGS optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-09 23:47:02 +00:00
Evan Cheng
8c6b991635 ARM target now also recognize triplets like thumbv6-apple-darwin and set thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66435 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-09 20:25:39 +00:00
Evan Cheng
6501153fc0 ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66429 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-09 19:15:00 +00:00
Chris Lattner
087fcf3e89 do not export all the X86FastISel symbols, ever.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66382 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 18:44:31 +00:00
Evan Cheng
4b1747430a Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66365 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 04:02:49 +00:00
Chris Lattner
ff9dcee534 add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66360 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 03:04:26 +00:00
Chris Lattner
b34487dcba add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66359 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 01:54:43 +00:00
Duncan Sands
667d4b8de6 Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr.  These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global.  In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time.   This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function.  If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body.  The
code generators on the other hand map weak and weak_odr linkage
to the same thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-07 15:45:40 +00:00
Dan Gohman
3112581441 Arithmetic instructions don't set EFLAGS bits OF and CF bits
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66318 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-07 01:58:32 +00:00
Dan Gohman
1f4af262d5 Don't use plain INC32 and DEC32 on x86-64; it needs
INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66207 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-05 21:32:23 +00:00
Dan Gohman
51bb47480e When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand.
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66206 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-05 21:29:28 +00:00
Dan Gohman
4bfcf2a2a6 Fix the "test" optimization to recognize "dec" as an add of
negative one, as subtracts of immediates are canonicalized
to adds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66180 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-05 19:32:48 +00:00
Dan Gohman
076aee32e8 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66058 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 19:44:21 +00:00
Dan Gohman
fc53fc657e Correct this comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66057 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 19:24:25 +00:00
Dan Gohman
b37a8206b6 When using MachineInstr operand indices on SDNodes, the number
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66056 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 19:23:38 +00:00
Evan Cheng
ae3f2b6c77 Fix PR3666: isel calls to constant addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 06:48:53 +00:00
Dan Gohman
29582d1223 Revert r66004 for now; it's causing a variety of test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66008 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 03:54:19 +00:00
Dan Gohman
12bbc52aa7 Teach the x86 backend to eliminate "test" instructions by using the EFLAGS
result from add, sub, inc, and dec instructions in simple cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66004 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 02:33:24 +00:00
Evan Cheng
599a6a88ce Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 01:41:49 +00:00
Dan Gohman
09a2609e20 Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC
instructions. These aren't used yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-03 19:53:46 +00:00
Bob Wilson
f2950b0051 Use early exit to reduce indentation. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-03 19:26:27 +00:00
Dan Gohman
0f8b53f19d Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-03 02:55:14 +00:00
Bob Wilson
24e338e8a3 Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle
arbitrary vector sizes.  Add an optional MinSplatBits parameter to specify
a minimum for the splat element size.  Update the PPC target to use the
revised interface.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65899 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-02 23:24:16 +00:00
Bob Wilson
a27ea9e89f Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new
method in a BuildVectorSDNode "pseudo-class".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65747 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-01 01:13:55 +00:00
Mon P Wang
9feb5dd568 Added another darwin subtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65662 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-28 00:25:30 +00:00
Rafael Espindola
9a58023c6c Refactor TLS code and add some tests. The tests and expected results are:
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 13:37:18 +00:00
Dale Johannesen
ded2b20e7e Alignment values for i64 and f64 on ppc64 were wrong,
possibly for the reason suggested by the comment.
No wonder it didn't work very well.  This unblocks
bootstrap with assertions on ppc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65601 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 00:56:35 +00:00
Evan Cheng
236aa8a503 ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65499 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-26 03:12:02 +00:00
Evan Cheng
a87008d90b Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-25 22:49:59 +00:00
Nick Lewycky
20babb112c Add a totally synthetic situation I came up with while looking at a bug in
related code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65437 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-25 06:52:48 +00:00
Scott Michel
df38043a46 Remove all "cached" data from BuildVectorSDNode, preferring to retrieve
results via reference parameters.

This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65426 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-25 03:12:50 +00:00
Bill Wendling
57f0db833d Overhaul my earlier submission due to feedback. It's a large patch, but most of
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-24 08:30:20 +00:00
Dan Gohman
e9865945ad Fast-isel can't do TLS yet, so it should fall back to SDISel
if it sees TLS addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65341 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-23 22:03:08 +00:00
Evan Cheng
242b38bae5 Only v1i16 (i.e. _m64) is returned via RAX / RDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65313 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-23 09:03:22 +00:00
Nate Begeman
b9a47b824f Generate better code for v8i16 shuffles on SSE2
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
  cleanups.
New tests that test the above.

Examples:

New:
_shuf2:
	pextrw	$7, %xmm0, %eax
	punpcklqdq	%xmm1, %xmm0
	pshuflw	$128, %xmm0, %xmm0
	pinsrw	$2, %eax, %xmm0

Old:
_shuf2:
	pextrw	$2, %xmm0, %eax
	pextrw	$7, %xmm0, %ecx
	pinsrw	$2, %ecx, %xmm0
	pinsrw	$3, %eax, %xmm0
	movd	%xmm1, %eax
	pinsrw	$4, %eax, %xmm0
	ret

=========

New:
_shuf4:
	punpcklqdq	%xmm1, %xmm0
	pshufb	LCPI1_0, %xmm0

Old:
_shuf4:
	pextrw	$3, %xmm0, %eax
	movsd	%xmm1, %xmm0
	pextrw	$3, %xmm1, %ecx
	pinsrw	$4, %ecx, %xmm0
	pinsrw	$5, %eax, %xmm0

========

New:
_shuf1:
	pushl	%ebx
	pushl	%edi
	pushl	%esi
	pextrw	$1, %xmm0, %eax
	rolw	$8, %ax
	movd	%xmm0, %ecx
	rolw	$8, %cx
	pextrw	$5, %xmm0, %edx
	pextrw	$4, %xmm0, %esi
	pextrw	$3, %xmm0, %edi
	pextrw	$2, %xmm0, %ebx
	movaps	%xmm0, %xmm1
	pinsrw	$0, %ecx, %xmm1
	pinsrw	$1, %eax, %xmm1
	rolw	$8, %bx
	pinsrw	$2, %ebx, %xmm1
	rolw	$8, %di
	pinsrw	$3, %edi, %xmm1
	rolw	$8, %si
	pinsrw	$4, %esi, %xmm1
	rolw	$8, %dx
	pinsrw	$5, %edx, %xmm1
	pextrw	$7, %xmm0, %eax
	rolw	$8, %ax
	movaps	%xmm1, %xmm0
	pinsrw	$7, %eax, %xmm0
	popl	%esi
	popl	%edi
	popl	%ebx
	ret

Old:
_shuf1:
	subl	$252, %esp
	movaps	%xmm0, (%esp)
	movaps	%xmm0, 16(%esp)
	movaps	%xmm0, 32(%esp)
	movaps	%xmm0, 48(%esp)
	movaps	%xmm0, 64(%esp)
	movaps	%xmm0, 80(%esp)
	movaps	%xmm0, 96(%esp)
	movaps	%xmm0, 224(%esp)
	movaps	%xmm0, 208(%esp)
	movaps	%xmm0, 192(%esp)
	movaps	%xmm0, 176(%esp)
	movaps	%xmm0, 160(%esp)
	movaps	%xmm0, 144(%esp)
	movaps	%xmm0, 128(%esp)
	movaps	%xmm0, 112(%esp)
	movzbl	14(%esp), %eax
	movd	%eax, %xmm1
	movzbl	22(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	42(%esp), %eax
	movd	%eax, %xmm1
	movzbl	50(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm1, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	77(%esp), %eax
	movd	%eax, %xmm1
	movzbl	84(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	104(%esp), %eax
	movd	%eax, %xmm1
	punpcklbw	%xmm1, %xmm0
	punpcklbw	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	punpcklbw	%xmm3, %xmm1
	movzbl	127(%esp), %eax
	movd	%eax, %xmm0
	movzbl	135(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	155(%esp), %eax
	movd	%eax, %xmm0
	movzbl	163(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm0, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	188(%esp), %eax
	movd	%eax, %xmm0
	movzbl	197(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	217(%esp), %eax
	movd	%eax, %xmm4
	movzbl	225(%esp), %eax
	movd	%eax, %xmm0
	punpcklbw	%xmm4, %xmm0
	punpcklbw	%xmm2, %xmm0
	punpcklbw	%xmm3, %xmm0
	punpcklbw	%xmm1, %xmm0
	addl	$252, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65311 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-23 08:49:38 +00:00
Bill Wendling
ef4cfc749a Propagate debug loc info through prologue/epilogue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65298 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-23 00:42:30 +00:00
Scott Michel
4214a5531c Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 23:36:09 +00:00
Evan Cheng
779aee1fea Add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 08:13:45 +00:00
Evan Cheng
6140a8b057 Be bug compatible with gcc by returning MMX values in RAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65274 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 08:05:12 +00:00
Evan Cheng
c94ebef1b1 Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 08:04:23 +00:00
Anton Korobeynikov
b5bd026a75 Drop bunch of half-working stuff in the ext_weak linkage support.
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).

The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65230 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 11:53:32 +00:00
Bill Wendling
5a45d76c25 Make sure this doesn't access .end() too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65213 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 01:11:36 +00:00
Bill Wendling
8aa374b629 Make sure we don't dereference the .end() of the container.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65211 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 01:07:26 +00:00
Bill Wendling
3d2445f5d9 Propagate more debug loc infos. This also includes some code cleaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65207 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 00:43:56 +00:00
Bill Wendling
2625f9b2e4 We need to propagate the debug location information even when dealing with the
prologue/epilogue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65206 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 00:32:08 +00:00
Evan Cheng
79fb3b434f Support return of MMX values in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65152 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-20 20:43:02 +00:00
Torok Edwin
474479fce7 add note about sin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65137 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-20 18:42:06 +00:00
Bill Wendling
cb819f13d7 Put code that generates debug labels into TableGen so that it can be used by
everyone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64978 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 23:12:06 +00:00
Dan Gohman
38deef9ce5 Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64915 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 16:37:45 +00:00
Nate Begeman
d6b7a242d3 Add support to the JIT for true non-lazy operation. When a call to a function
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64906 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 08:31:02 +00:00
Dan Gohman
97357614b5 Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 05:45:50 +00:00
Evan Cheng
caa0c2cadd GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64877 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 02:19:52 +00:00
Scott Michel
fdc40a0a69 Remove trailing whitespace to reduce later commit patch noise.
(Note: Eventually, commits like this will be handled via a pre-commit hook that
 does this automagically, as well as expand tabs to spaces and look for 80-col
 violations.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64827 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-17 22:15:04 +00:00
Chris Lattner
a66878b881 add a horrible note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-17 01:16:14 +00:00
Bill Wendling
86e6cb924b --- Merging (from foreign repository) r64714 into '.':
U    include/llvm/CodeGen/DebugLoc.h
U    lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp

Enable debug location generation at -Os. This goes with the reapplication of the
r63639 patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64715 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-17 01:04:54 +00:00
Dan Gohman
9fbb52db98 Delete trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64694 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-16 23:14:14 +00:00
Dan Gohman
35188eb54d MachineLICM now handles these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64620 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-15 23:24:52 +00:00
Dan Gohman
b5aa3ad1e7 The x86-64 red zone is now being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-14 03:30:05 +00:00
Evan Cheng
c7ce29b04f Teach x86 target -soft-float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64496 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 22:36:38 +00:00
Dale Johannesen
948175785d Remove non-DebugLoc versions of BuildMI from IA64, Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64438 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:34:39 +00:00
Dale Johannesen
8d13f8f104 Remove non-DebugLoc versions of BuildMI from X86.
There were some that might even matter in X86FastISel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64437 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:33:27 +00:00
Dale Johannesen
0b4581f16c missed file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:32:04 +00:00
Dale Johannesen
d552eee4a0 Remove non-DebugLoc versions of buildMI from Sparc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64435 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:31:35 +00:00
Dale Johannesen
01b36e6436 Remove non-DebugLoc versions of BuildMI from Alpha and Cell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:30:42 +00:00
Dale Johannesen
bd9ef18f74 Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64432 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:29:03 +00:00
Dale Johannesen
536a2f1f84 Remove refs to non-DebugLoc version of BuildMI from PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64431 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:27:39 +00:00
Dale Johannesen
8a43d98644 and one more file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64430 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:26:21 +00:00
Dale Johannesen
b67284057e Remove refs to non-DebugLoc versions of BuildMI from ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:25:56 +00:00
Bill Wendling
92c1e12647 Revert this. It was breaking stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:16:35 +00:00
Bill Wendling
54fc7d6714 Turn off the old way of handling debug information in the code generator. Use
the new way, where all of the information is passed on SDNodes and machine
instructions.


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2009-02-13 02:01:04 +00:00
Dale Johannesen
c5b5051357 Check in missing file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64410 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12 23:24:44 +00:00
Dale Johannesen
21b5541814 Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.



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2009-02-12 23:08:38 +00:00
Dale Johannesen
78e3e521cd Arrange to print constants that match "n" and "i" constraints
in inline asm as signed (what gcc does).  Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.



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2009-02-12 20:58:09 +00:00
Chris Lattner
8c4d1b2bcf fix PR3538 for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64384 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12 17:38:23 +00:00
Chris Lattner
f902d246b6 fix PR3538 for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64383 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12 17:37:15 +00:00
Chris Lattner
1823c92aa7 fix the X86 backend to just drop llvm.declare nodes for VLAs instead of
leaving them in the DAG and then getting selection errors.  This is a 
fix for PR3538.



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2009-02-12 17:33:11 +00:00
Bill Wendling
d1c321a89a Move debug loc info along when the spiller creates new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12 00:02:55 +00:00
Bill Wendling
fbef3101a5 Propagate DebugLoc info for spiller call-backs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-11 21:51:19 +00:00
Dan Gohman
d293e0d2dc Don't try to set an EFLAGS operand to dead if no instruction was created.
This fixes a bug introduced by r61215.


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2009-02-11 19:50:24 +00:00
Evan Cheng
1d76864df3 Handle llvm.x86.sse2.maskmov.dqu in 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64240 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-10 22:06:28 +00:00
Evan Cheng
7403eeaa88 80 col violations.
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2009-02-10 21:39:44 +00:00
Sanjiv Gupta
2cc753170b Function temporaries can not overlap with retval or args.See the comment in source code to know the reason. Anything having .auto. in its name is local to a function in nature irrespective of the linkage specified. print static local variables in module level IDATA section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64199 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-10 04:20:26 +00:00
Evan Cheng
a0eedac226 Implement FpSET_ST1_*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64186 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09 23:32:07 +00:00
Dan Gohman
333014e256 Use doxygen comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64150 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09 18:12:09 +00:00
Evan Cheng
dc54d317e7 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.


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2009-02-09 07:14:22 +00:00
Chris Lattner
be685cc72a add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64093 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-08 20:44:19 +00:00
Dale Johannesen
6f38cb61a9 Use getDebugLoc forwarder instead of getNode()->getDebugLoc.
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64026 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-07 19:59:05 +00:00
Dan Gohman
1fdbc1dd4e Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.


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2009-02-07 16:15:20 +00:00
Dale Johannesen
0469280776 Needs this file too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63993 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-07 00:56:46 +00:00
Dale Johannesen
b300d2aa3e Get rid of the last non-DebugLoc versions of getNode!
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base.  There's no
sensible way to associate debug info with these.  I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. 
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.



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2009-02-07 00:55:49 +00:00
Dan Gohman
2d0a1cc416 Refactor some repeated logic into a separate function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63989 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-07 00:43:41 +00:00
Dan Gohman
288b824cef Make a comment a doxygen comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-07 00:42:54 +00:00