"asm printering" happens through MCStreamer. This also
Streamerizes PIC16 debug info, which escaped my attention.
This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
return an error status in all failure cases, printing
messages to debugs() only when debugging is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100229 91177308-0d34-0410-b5e6-96231b3b80d8
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100118 91177308-0d34-0410-b5e6-96231b3b80d8
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
aes instead of sse4.2. Add a brief todo for a subtarget flag and rework
the aeskeygenassist instruction to more closely match the docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100078 91177308-0d34-0410-b5e6-96231b3b80d8
SSEDomainFix will collapse to the domain with the lower number when it has a
choice. The SSEPackedSingle domain often has smaller instructions, so prefer
that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99952 91177308-0d34-0410-b5e6-96231b3b80d8
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99910 91177308-0d34-0410-b5e6-96231b3b80d8
create symbols. It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.
This fixes rdar://7807601.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99902 91177308-0d34-0410-b5e6-96231b3b80d8
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99838 91177308-0d34-0410-b5e6-96231b3b80d8
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.
The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.
This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.
The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
handles dead implicit results more aggressively. More
to come, I think this is now just a data entry problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99486 91177308-0d34-0410-b5e6-96231b3b80d8
addl $12, %esp
popl %esi
popl %edi
popl %ebx
popl %ebp
jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL
The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.
The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99455 91177308-0d34-0410-b5e6-96231b3b80d8
--- Reverse-merging r99440 into '.':
U test/MC/AsmParser/X86/x86_32-bit_cat.s
U test/MC/AsmParser/X86/x86_32-encoding.s
U include/llvm/IntrinsicsX86.td
U include/llvm/CodeGen/SelectionDAGNodes.h
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99450 91177308-0d34-0410-b5e6-96231b3b80d8
not get an "Unknown immediate size" assert failure when used. All instructions
of this form have an 8-bit immediate. Also added a test case of an example
instruction that is of this form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
ISD node. The only change in the generated isel code are comments
like:
< // Src: (X86dec_flag:i16 GR16:i16:$src)
---
> // Src: (X86dec_flag:i16:i32 GR16:i16:$src)
because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case. Wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99369 91177308-0d34-0410-b5e6-96231b3b80d8
This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99345 91177308-0d34-0410-b5e6-96231b3b80d8
caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99032 91177308-0d34-0410-b5e6-96231b3b80d8
override prefix and only the r/m16 forms should have had that. Also for variant
one, the AT&T syntax, added suffixes to all forms. Also added the missing
64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
- MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98955 91177308-0d34-0410-b5e6-96231b3b80d8
dag isel gen instead of instruction properties. This
allows the oh-so-useful behavior of matching a variadic
non-root node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
can't match or just have no testcases. Will remove after
confirmation from dan that they really are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98930 91177308-0d34-0410-b5e6-96231b3b80d8
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
temporary workaround for matching inc/dec on x86_64 to the correct instruction.
- This hack will eventually be replaced with a robust mechanism for handling
matching instructions based on the available target features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98858 91177308-0d34-0410-b5e6-96231b3b80d8
- Although it would be nice to allow this decoupling, the assembler needs to be able to reason about MCSymbolRefExprs in too many places to make this viable. We can use a target specific encoding of the variant if this becomes an issue.
- This patch also extends llvm-mc to support parsing of the modifiers, as opposed to lumping them in with the symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98592 91177308-0d34-0410-b5e6-96231b3b80d8
32-bit indices. Instead of shuffling each element out of the index vector,
when all indices are needed, just store the input vector to the stack and
load the elements out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98588 91177308-0d34-0410-b5e6-96231b3b80d8
to is local to the translation unit, we need to place fill the value of that
symbol into the non-lazy pointer.
This should conclude all Darwin changes for placing the LSDA into the TEXT
section. There is some cleanup to do. I.e., there's no longer a special need for
target-specific code here. But that can come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98564 91177308-0d34-0410-b5e6-96231b3b80d8
MachineInstr -> MCInst. This is what the assembler backend wants,
it relaxes from smaller to larger things. This fixes rdar://7750815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98493 91177308-0d34-0410-b5e6-96231b3b80d8
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98463 91177308-0d34-0410-b5e6-96231b3b80d8
instead of label ID's. This cleans up and regularizes a bunch
of code and makes way for future progress.
Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places. This is very sad and disturbing. :(
One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction. There should not be any
functionality change from doing this, but I'm not an EH expert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98459 91177308-0d34-0410-b5e6-96231b3b80d8
and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98450 91177308-0d34-0410-b5e6-96231b3b80d8
no arguments instead of having to come up with a unique name.
This also makes the code less fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98364 91177308-0d34-0410-b5e6-96231b3b80d8
an MCExpr and not an MCSymbol. Change it to take an MCStreamer,
which is currently unused.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98278 91177308-0d34-0410-b5e6-96231b3b80d8
which doesn't support .quad correctly because it is
"really really old". PR6528.
Yet another reason the mc assembler should take over ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98205 91177308-0d34-0410-b5e6-96231b3b80d8
indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98199 91177308-0d34-0410-b5e6-96231b3b80d8
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
We cannot use a normal call here since it has extra unmodelled side
effects (it changes stack pointer). This should fix PR5292.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97884 91177308-0d34-0410-b5e6-96231b3b80d8
This code:
float floatingPointComparison(float x, float y) {
double product = (double)x * y;
if (product == 0.0)
return product;
return product - 1.0;
}
produces this:
_floatingPointComparison:
0000000000000000 cvtss2sd %xmm1,%xmm1
0000000000000004 cvtss2sd %xmm0,%xmm0
0000000000000008 mulsd %xmm1,%xmm0
000000000000000c pxor %xmm1,%xmm1
0000000000000010 ucomisd %xmm1,%xmm0
0000000000000014 jne 0x00000004
0000000000000016 jp 0x00000002
0000000000000018 jmp 0x00000008
000000000000001a addsd 0x00000006(%rip),%xmm0
0000000000000022 cvtsd2ss %xmm0,%xmm0
0000000000000026 ret
The "jne/jp/jmp" sequence can be reduced to this instead:
_floatingPointComparison:
0000000000000000 cvtss2sd %xmm1,%xmm1
0000000000000004 cvtss2sd %xmm0,%xmm0
0000000000000008 mulsd %xmm1,%xmm0
000000000000000c pxor %xmm1,%xmm1
0000000000000010 ucomisd %xmm1,%xmm0
0000000000000014 jp 0x00000002
0000000000000016 je 0x00000008
0000000000000018 addsd 0x00000006(%rip),%xmm0
0000000000000020 cvtsd2ss %xmm0,%xmm0
0000000000000024 ret
for a savings of 2 bytes.
This xform can happen when we recognize that jne and jp jump to the same "true"
MBB, the unconditional jump would jump to the "false" MBB, and the "true" branch
is the fall-through MBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97766 91177308-0d34-0410-b5e6-96231b3b80d8
These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG
reads AX in order to avoid reading AH with a REX instruction.
Fix PR6489.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97742 91177308-0d34-0410-b5e6-96231b3b80d8
register if it isn't possible to match the indexes *and* the base.
This fixes some fast isel rejects of load instructions on oggenc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97739 91177308-0d34-0410-b5e6-96231b3b80d8
'dsload' pattern. tblgen doesn't check patterns to see if they're
textually identical. This allows better factoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97630 91177308-0d34-0410-b5e6-96231b3b80d8
that they are not destination type specific. This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97629 91177308-0d34-0410-b5e6-96231b3b80d8
CopyToReg/CopyFromReg/INLINEASM. These are annoying because
they have the same opcode before an after isel. Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.
With that done, give IsLegalToFold a new flag that causes it to
ignore chains. This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing. This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.
I currently #if out the dead code in the X86 backend and MSP
backend, I'll remove it for real in a follow-on patch.
The testcase changes are:
test/CodeGen/X86/sse3.ll: we generate better code
test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was
miscompiling this before, we now generate correct code
Convert it to filecheck while I'm at it.
test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
folding to make anton happy. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97596 91177308-0d34-0410-b5e6-96231b3b80d8
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.
Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97354 91177308-0d34-0410-b5e6-96231b3b80d8
necessary to swap the operands to handle NaN and negative zero properly.
Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97025 91177308-0d34-0410-b5e6-96231b3b80d8
place where an i32 imm was required, the old isel just got lucky.
This fixes CodeGen/X86/x86-64-and-mask.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96894 91177308-0d34-0410-b5e6-96231b3b80d8
don't alis it in the MMX .td file with a different width,
split into two X86ISD opcodes. This fixes an x86 testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96859 91177308-0d34-0410-b5e6-96231b3b80d8
during a tail call. A parameter might overwrite this stack slot during the tail
call.
The sequence during a tail call is:
1.) load return address to temp reg
2.) move parameters (might involve storing to return address stack slot)
3.) store return address to new location from temp reg
If the stack location is marked immutable CodeGen can colocate load (1) with the
store (3).
This fixes bug 6225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96783 91177308-0d34-0410-b5e6-96231b3b80d8
SSE min and max instructions. The real thing this code needs to be
concerned about is negative zero.
Update the sse-minmax.ll test accordingly, and add tests for
-enable-unsafe-fp-math mode as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96775 91177308-0d34-0410-b5e6-96231b3b80d8
create an X86ISD::Cmp node with result type i64 on the
CodeGen/X86/shift-i256.ll testcase and the new isel was assert on it
downstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96768 91177308-0d34-0410-b5e6-96231b3b80d8
it to follow the mode needed by the new isel. Instead of returning
the input and output chains, it just returns the (currently only one,
which is a silly limitation) node that has input and output chains.
Since we want the old thing to still work, add a new
SelectScalarSSELoad to emulate the old interface. The XXX suffix
and the wrapper will eventually go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96715 91177308-0d34-0410-b5e6-96231b3b80d8
dragonegg self-host build. I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier. The
symptom of the 96556 miscompile is the following crash:
llvm[3]: Compiling AlphaISelLowering.cpp for Release build
cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
Stack dump:
0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
g++: Internal error: Aborted (program cc1plus)
This occurs when building LLVM using LLVM built by LLVM (via
dragonegg). Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM. Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.
Found by bisection.
r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96672 91177308-0d34-0410-b5e6-96231b3b80d8
