Bruno Cardoso Lopes
97dc60b759
Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix
...
PR10955 and PR10948.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 21:29:24 +00:00
Nadav Rotem
354efd88db
setOperationAction should be done on the return value of the type, not the operands.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 14:57:03 +00:00
Nadav Rotem
91e43fd17a
When promoting integer vectors we often create ext-loads. This patch adds a
...
dag-combine optimization to implement the ext-load efficiently (using shuffles).
For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 10:39:32 +00:00
Benjamin Kramer
5778fef314
Apply Duncan's test fix from r139986 to the avx version of that test too.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 00:41:38 +00:00
Duncan Sands
6bcd2196e5
Synthesize x86 max/min instructions also for vectors (i.e. produce
...
maxps and maxpd). This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it. Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-17 16:49:39 +00:00
Andrew Trick
cc32efd592
Test case trial and error. Not sure the proper way to check MBB names.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 03:57:19 +00:00
Andrew Trick
17bd2c5d68
Reduced a stronger test case for coalescer bug PR10920.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 03:46:49 +00:00
Eli Friedman
331120b1a4
Some legalization fixes for atomic load and store.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 21:20:49 +00:00
Jakob Stoklund Olesen
01afdb3a45
VirtRegMap is counting spill slots, not register spills.
...
Fix the stats counters to reflect that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 18:31:13 +00:00
Bruno Cardoso Lopes
0c4b9ff077
Change all checks regarding the presence of any SSE level to always
...
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 18:27:36 +00:00
Andrew Trick
b1afbac64b
[regcoalescing] bug fix for RegistersDefinedFromSameValue.
...
An improper SlotIndex->VNInfo lookup was leading to unsafe copy removal.
Fixes PR10920 401.bzip2 miscompile with no IV rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 01:09:33 +00:00
Nadav Rotem
436fe8498a
Add integer promotion support for vselect
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 14:42:15 +00:00
Bruno Cardoso Lopes
5ca0d14915
Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss".
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 02:36:14 +00:00
Devang Patel
d2aaaf3a75
Remove ancient debug info constructs from test cases, they are not relevant to test case's main objective.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 00:29:50 +00:00
Devang Patel
64789c582c
Remove unnecessary old test.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 00:28:54 +00:00
Akira Hatanaka
8395c91d56
Delete test cases that generate code for allegrex/psp and cannot be repurposed.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 22:29:13 +00:00
Eli Friedman
fe731214d2
Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:50:54 +00:00
Akira Hatanaka
a4b97f327d
Add pattern used to match MipsLo, which is needed when the instruction selector
...
tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:13:58 +00:00
Akira Hatanaka
302fdecf9d
Disable tests which generate code for allegrex or psp.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:00:35 +00:00
Nadav Rotem
e1490d1e43
update checked pattern
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 19:59:18 +00:00
Nadav Rotem
aec5861bb6
Add vselect target support for targets that do not support blend but do support
...
xor/and/or (For example SSE2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 19:17:42 +00:00
Andrew Trick
3c8015aa6c
Generalize this test's CHECK statements to handle different indvars modes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 02:46:27 +00:00
Bruno Cardoso Lopes
8970060a4c
Change testcase commandline to be more strict and silence buildbots
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139554 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 22:59:26 +00:00
Bruno Cardoso Lopes
5fc48100ee
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
...
destination types are equal!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 22:59:23 +00:00
Bruno Cardoso Lopes
457d53d9ce
Revert the wrong part of r139528, and fix testcases.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:24:07 +00:00
Bruno Cardoso Lopes
8e03a821f9
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
...
However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:40 +00:00
Eli Friedman
9f3b6a5a2a
Fix mistake in test runline.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 17:32:58 +00:00
Richard Osborne
a1d16b53e8
Associate a MemOperand with LDWCP nodes introduced during ISel.
...
This information is required if we want LDWCP to be hoisted out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:43:23 +00:00
Eli Friedman
cfeb55cdbc
Really un-XFAIL the testcase, like I said I would in r139458.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 02:02:27 +00:00
Richard Trieu
2db8628085
Fixed an assert from:
...
assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:26:21 +00:00
Akira Hatanaka
33ff5aeaa8
Fix test cases.
...
Generate code for Mips32r1 unless a Mips32r2 feature is tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:14:58 +00:00
Eli Friedman
9db817fd0c
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:04:06 +00:00
Akira Hatanaka
8ddf6531b8
Drop support for Mips1 and Mips2.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00
Nadav Rotem
8ffad56f8e
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:29:17 +00:00
Akira Hatanaka
d199d0c59c
Drop support for Allegrex. Allegrex implements a variant of Mips2.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:00:51 +00:00
Akira Hatanaka
ad5f0c9e73
Change default target architecture from Mips1 to Mips32r1 in preparation for
...
removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 01:13:27 +00:00
Devang Patel
9aee335c23
Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:59:09 +00:00
Bruno Cardoso Lopes
7ec8fb8830
Add a AVX version of a simple i64 -> f64 bitcast. This could be
...
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
7cf79a88c8
Reapply testcase from r139309!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:05:43 +00:00
Bruno Cardoso Lopes
caa60f15e4
Remove this crashing test, until I figure out what's going wrong here
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139309 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes
814c6ced85
Add AVX versions of blend vector operations and fix some issues noticed
...
in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
...
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:02 +00:00
Nadav Rotem
4b36e07487
This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139288 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:43:23 +00:00
Nadav Rotem
cbdd2d10ba
add a testcase for the previous patch
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:31:31 +00:00
Nadav Rotem
ffe3e7da84
Add X86-SSE4 codegen support for vector-select.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:11:19 +00:00
Eli Friedman
d5ccb0558f
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
...
This isn't exactly ideal, but it is good enough for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:48:32 +00:00
Duncan Sands
68b859f757
Another forgotten trampoline testcase.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139230 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 10:05:14 +00:00
Eli Friedman
981a010c09
Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.
...
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 02:23:42 +00:00
Devang Patel
541a81cc2b
While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 00:07:58 +00:00
Nick Lewycky
756a0a1f39
Disable these tests harder. They're XFAIL'd, but that means they still run, and
...
these tests all infinitely recurse, bringing my system down into swapping hell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 22:08:18 +00:00