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1444 Commits

Author SHA1 Message Date
Owen Anderson
70671845ad Continue the SimpleValueType-ification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 20:18:46 +00:00
Chris Lattner
f9bdeddb96 split MachO section handling stuff out to its out .h/.cpp file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78576 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 18:15:01 +00:00
Chris Lattner
f3231de60b arm only needs to emit one .align directive for hidden nlp's, not one 
per pointer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78574 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 18:02:16 +00:00
Chris Lattner
c076a97939 make sure that arm nonlazypointers are aligned properly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78573 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 18:01:34 +00:00
David Goodwin
bcf81629b8 Checkpoint scheduling itinerary changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 15:56:13 +00:00
Evan Cheng
65f2e7887a Watch out for empty BB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78562 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 08:10:13 +00:00
Evan Cheng
8442d00a0e rev, rev16, and revsh do not set CPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78561 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 07:58:45 +00:00
Evan Cheng
0d3007bb32 Duh. Most 16-bit Thumb rr instructions are two-address. Fix table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78560 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 07:20:37 +00:00
Evan Cheng
26cc252a43 CPSR can be livein; transfer predicate operands correctly; tMUL is two-address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78559 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 06:57:42 +00:00
Evan Cheng
19068ba71a Add support for folding loads / stores into 16-bit moves used by Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 06:32:05 +00:00
Evan Cheng
2294645642 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 05:51:48 +00:00
Evan Cheng
052053bbe3 Use tMOVgpr2gpr instead of t2MOVr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78556 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 05:49:43 +00:00
Evan Cheng
e8af1f9afe Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 02:37:24 +00:00
Evan Cheng
09d97354ed Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78549 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 02:06:53 +00:00
Chris Lattner
ff4bc460c5 Make the big switch: Change MCSectionMachO to represent a section *semantically* 
instead of syntactically as a string.  This means that it keeps track of the 
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and 
"attribute(section)", so we should now start getting errors about invalid 
section attributes from the compiler instead of the assembler on darwin.

Still todo: 
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
   S_GB_ZEROFILL segment type?



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78547 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 01:39:42 +00:00
Evan Cheng
a56c57e5f0 Add support to convert 32-bit instructions to 16-bit non-two-address ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78540 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-09 19:17:19 +00:00
Anton Korobeynikov
8e9ece75db Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 23:10:41 +00:00
Chris Lattner
892e182393 1. Make MCSection an abstract class. 
2. Move section switch printing to MCSection virtual method which takes a
   TAI.  This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and 
   TLOFELF::AtIsCommentChar.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 22:41:53 +00:00
Chris Lattner
0c0cb71233 now that getOrCreateSection is all object-file specific, 
give the impls an object-file-specific name.  In the future
they can take different arguments etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78495 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 20:22:20 +00:00
Daniel Dunbar
cf1e764a1c Update CMake 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78475 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 17:03:13 +00:00
Anton Korobeynikov
06af2ba809 Add insert_elt / extract_elt patterns for v4f32 stuff. 
Did anyone tests v4f32 ever?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78470 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 14:06:07 +00:00
Anton Korobeynikov
3405201bce Lane number should be printed w/o hash 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78469 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 14:05:53 +00:00
Anton Korobeynikov
baf31088f1 Use VLDM / VSTM to spill/reload 128-bit Neon registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 13:35:48 +00:00
Bob Wilson
b6ab51e829 Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, 
so I generalized the class for VTRN in the .td file to handle all 3 of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 06:13:25 +00:00
Bob Wilson
64efd90f8c Implement Neon VTRN instructions. For now, anyway, these are selected 
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 05:53:00 +00:00
Evan Cheng
3eff16e27a Add a skeleton Thumb2 instruction size reduction pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78456 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 03:21:23 +00:00
Evan Cheng
8fb903604e Code refactoring. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 03:20:32 +00:00
Evan Cheng
57834cdee5 tADDhirr should target GPR, not tGPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78454 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 03:19:44 +00:00
Evan Cheng
34f8a029e3 I can type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78453 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 02:54:37 +00:00
Chris Lattner
41aefdcdd1 make printInstruction return void since its result is omitted. Make the 
error condition get trapped with an assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78449 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 01:32:19 +00:00
David Goodwin
767a952a6f Make NEON single-precision FP support the default for cortex-a8 (again). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 23:32:33 +00:00
Anton Korobeynikov
a55fd4a23f Unbreak the stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78425 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 22:51:13 +00:00
Anton Korobeynikov
32a1b25781 2 more vdup.32 cases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 22:36:50 +00:00
Evan Cheng
fcc716352b A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78418 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 22:36:37 +00:00
Evan Cheng
d77c7aba83 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78410 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 21:19:10 +00:00
Evan Cheng
f12288e8aa This is done. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78399 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 19:34:52 +00:00
Evan Cheng
e118cb6146 Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78398 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 19:34:35 +00:00
Evan Cheng
1d2426c470 Fix support to use NEON for single precision fp math. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 19:30:41 +00:00
Evan Cheng
b6879b2b84 Error out, rather than infinite looping, if constant island pass can't converge. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78377 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 07:35:21 +00:00
Evan Cheng
53c67c0218 tBfar is bl, which clobbers LR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78370 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 05:45:07 +00:00
Dan Gohman
7db949df78 Fix a bunch of namespace pollution. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 01:32:21 +00:00
Evan Cheng
861986401e It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 00:34:42 +00:00
Bob Wilson
b36ec86c01 Implement Neon VST[234] operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 18:47:44 +00:00
David Goodwin
8b7d7ade85 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 16:52:47 +00:00
Bob Wilson
0cedab9a0d Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 00:24:27 +00:00
Bob Wilson
70cd88fb7b Add a new pre-allocation pass to assign adjacent registers for Neon instructions 
that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78256 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 23:12:45 +00:00
David Goodwin
7bfdca0206 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 21:02:22 +00:00
Anton Korobeynikov
058c251d4a Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly 
hardfloat case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 20:15:19 +00:00
Anton Korobeynikov
14d9495403 Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78232 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 19:40:16 +00:00
Anton Korobeynikov
567d14f07c Missed pieces for ARM HardFP ABI. 
Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78225 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 19:04:42 +00:00
Daniel Dunbar
e22f4da01d Remove some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78219 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 18:12:37 +00:00
Bob Wilson
7f0f2515a0 Remove a redundant declaration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78216 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 17:39:44 +00:00
David Goodwin
ce3c1f2a0e Disable NEON single-precision FP support for Cortex-A8, for now... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78209 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:40:57 +00:00
Devang Patel
bccdcb1857 Remove dead code. MDNode and MDString are not Constant anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78207 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:40:02 +00:00
David Goodwin
1f0e404c87 By default, for cortex-a8 use NEON for single-precision FP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:01:19 +00:00
Evan Cheng
61f4b721b2 80 col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78175 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 06:41:25 +00:00
Bob Wilson
aa289d5e7f Oops. I didn't mean to commit this piece yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78146 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 02:47:13 +00:00
Dan Gohman
98ca4f2a32 Major calling convention code refactoring. 
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 01:29:28 +00:00
Dan Gohman
1c55fab534 Don't flush the raw_ostream between each MachineFunction. These flush 
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78137 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 00:49:25 +00:00
Bob Wilson
4a3d35abef Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. 
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 00:49:09 +00:00
Evan Cheng
35d6c41fde Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 23:47:55 +00:00
Bob Wilson
c00479253b Replace dregsingle operand modifier with explicit escaped curly brackets. 
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:39:33 +00:00
Evan Cheng
9e7a312391 Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:12:13 +00:00
David Goodwin
53e4471adc Add NEON single-precision FP support for fabs and fneg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 20:39:05 +00:00
Evan Cheng
3425df44b5 In thumb mode, r7 is used as frame register. This fixes pr4681. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:46:17 +00:00
David Goodwin
b84f3d427c Match common pattern for FNMAC. Add NEON SP support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:44:29 +00:00
David Goodwin
42a83f2d15 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 17:53:06 +00:00
Anton Korobeynikov
939ba32747 Ooops, I was too fast to commit the wrong fix :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78060 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 11:18:31 +00:00
Anton Korobeynikov
20e037a8c5 Fix a typo - this unbreaks llvm-gcc build on arm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78059 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 11:12:51 +00:00
Evan Cheng
eb084d1671 Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78057 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 08:34:18 +00:00
Evan Cheng
f0409ea488 Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78032 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 01:56:09 +00:00
Evan Cheng
27934da97b Load / store multiple pass fixes for Thumb2. Not enabled yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78031 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 01:43:45 +00:00
Evan Cheng
fa2ea1a8cf Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 01:41:15 +00:00
Bob Wilson
a599bff101 Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the 
results to fixed registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78025 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 00:36:16 +00:00
Bob Wilson
916afdbc2d Minor cleanup. No functional changes intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 00:25:01 +00:00
Chris Lattner
5e44e472d6 use TLOF to compute the section for a function instead of 
replicating the logic manually.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 22:32:50 +00:00
Chris Lattner
f61159b574 convert macho stub emission to use SwitchToSection instead of 
textual sections.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78007 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 22:18:15 +00:00
Bob Wilson
a6d658620f Lower CONCAT_VECTOR during legalization instead of matching it during isel. 
Add a testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 20:36:38 +00:00
Benjamin Kramer
d5fe92efbc llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77971 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 13:33:33 +00:00
Evan Cheng
9072c8198d These are done. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77949 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 04:08:36 +00:00
Evan Cheng
a8e8984ee4 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 02:38:06 +00:00
Daniel Dunbar
e28039cfd1 Move most targets TargetMachine constructor to only taking a target triple. 
- The C, C++, MSIL, and Mips backends still need the module.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77927 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 23:37:13 +00:00
Daniel Dunbar
3be03406c9 Normalize Subtarget constructors to take a target triple string instead of 
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 22:11:08 +00:00
Chris Lattner
18a4c16726 move dwarf debug info section selection stuff from TAI to 
TLOF, unifying all the dwarf targets at the same time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77889 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 07:24:22 +00:00
Chris Lattner
24def37c85 ARM TAI no longer needs a TM, but createTargetAsmInfo() still does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77878 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 05:23:52 +00:00
Chris Lattner
d90183d25d Move the getInlineAsmLength virtual method from TAI to TII, where 
the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain.  It should be removed 
IMNSHO, but I'll leave that to ARMish folks to decide.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 05:20:37 +00:00
Chris Lattner
7bbd178d4b turn some templated inline functions into static functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77873 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 04:52:00 +00:00
Chris Lattner
9ba8c6872d remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfo 
defaults to being ELF.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77866 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 04:33:09 +00:00
Chris Lattner
8d4a0a328a remove TargetAsmInfo::TM, which is now dead. The basic TAI class now 
no longer depends on TM!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77863 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 04:27:24 +00:00
Chris Lattner
80ec2792b2 convert ctors/dtors section to be in TLOF instead of 
TAI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77842 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 00:34:36 +00:00
Chris Lattner
b80610cd13 REmove dead fields of TAI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77820 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 22:40:22 +00:00
Evan Cheng
25f7cfc3cc Workaround a couple of Darwin assembler bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 06:13:52 +00:00
Evan Cheng
13f8b36205 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 01:43:45 +00:00
Evan Cheng
b620724e61 Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 00:16:10 +00:00
Evan Cheng
a0ee862f2e t2BR_JT is mov pc, it's 2 byte long, not 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77744 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 22:22:22 +00:00
Evan Cheng
1119776b19 Thumb2 movcc need .w suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77743 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 22:21:55 +00:00
Chris Lattner
a87dea4f8c switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:48:30 +00:00
Evan Cheng
ff6ab17619 Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:35:56 +00:00
Evan Cheng
d26b14c34c - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset 
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77701 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:28:05 +00:00
Chris Lattner
f26e03bc7e refactor section construction in TLOF to be through an explicit 
initialize method, which can be called when an MCContext is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 17:42:42 +00:00