Commit Graph

71 Commits

Author SHA1 Message Date
Nick Lewycky
028700f544 Move parts of lib/Target that use CodeGen into lib/CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146702 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:58:58 +00:00
Evan Cheng
32f9763017 Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 06:41:08 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Evan Cheng
4db3cffe94 Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 17:57:27 +00:00
Evan Cheng
ab8be96fd3 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 01:14:12 +00:00
Evan Cheng
d5b03f252c Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 21:14:33 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 19:10:37 +00:00
Evan Cheng
15993f83a4 More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 21:26:13 +00:00
Jim Grosbach
d31d304f83 Clean up assembly statement separator support.
The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:46:34 +00:00
Andrew Trick
6e8f4c4048 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 04:28:06 +00:00
Nick Lewycky
476b242fe7 Add missing standard headers. Patch by Joerg Sonnenberger!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19 20:43:38 +00:00
Nick Lewycky
2402123413 Add missing std:: prefixes to some calls. C++ doesn't require that <cfoo>
headers provide symbols outside namespace std and the LLVM coding standards
state that we should prefix all of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19 20:42:43 +00:00
Evan Cheng
8239daf7c8 Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 00:45:17 +00:00
Evan Cheng
c8141dfc7f Use instruction itinerary to determine what instructions are 'cheap'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 02:08:50 +00:00
Evan Cheng
a0792de66c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 06:27:31 +00:00
Bob Wilson
064312de86 Spelling fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:28:21 +00:00
Evan Cheng
3ef1c8759a Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 01:29:16 +00:00
Evan Cheng
5f54ce3473 For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:18:55 +00:00
Dan Gohman
a606d955de Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:55 +00:00
Chris Lattner
33adcfb4d2 rename TAI -> MAI, being careful not to make MAILJMP instructions :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79777 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22 21:43:10 +00:00
Chris Lattner
af76e592c7 Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22 20:48:53 +00:00
Chris Lattner
d90183d25d Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain.  It should be removed 
IMNSHO, but I'll leave that to ARMish folks to decide.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02 05:20:37 +00:00
Chris Lattner
b6bbfebdc6 move a virtual method body to its .cpp file to avoid a #include
in a header.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02 04:58:19 +00:00
Chris Lattner
2a38688494 inline the global 'getInstrOperandRegClass' function into its callers
now that TargetOperandInfo does the heavy lifting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 21:36:49 +00:00
Chris Lattner
cb778a8634 1. Introduce a new TargetOperandInfo::getRegClass() helper method
and convert code to using it, instead of having lots of things
   poke the isLookupPtrRegClass() method directly.

2. Make PointerLikeRegClass contain a 'kind' int, and store it in
   the existing regclass field of TargetOperandInfo when the
   isLookupPtrRegClass() predicate is set.  Make getRegClass pass
   this into TargetRegisterInfo::getPointerRegClass(), allowing
   targets to have multiple ptr_rc things.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77504 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 21:10:12 +00:00
Evan Cheng
d923fc621f Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05 00:30:09 +00:00
Bob Wilson
d9df501704 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 17:16:43 +00:00
Chris Lattner
749c6f6b5e rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 07:27:27 +00:00
Chris Lattner
349c495200 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 03:13:06 +00:00
Chris Lattner
69244300b8 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 01:56:04 +00:00
Chris Lattner
6410552250 Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 01:03:04 +00:00
Chris Lattner
8aa797aa51 Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-30 23:10:15 +00:00
Chris Lattner
f73823000e More cleanups for MachineOperand:
- Eliminate the static "print" method for operands, moving it
    into MachineOperand::print.
  - Change various set* methods for register flags to take a bool
    for the value to set it to.  Remove unset* methods.
  - Group methods more logically by operand flavor in MachineOperand.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45461 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-30 21:56:09 +00:00
Chris Lattner
9a1ceaedc2 Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-30 20:49:49 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Dan Gohman
92dfe2001e Remove isReg, isImm, and isMBB, and change all their users to use
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-14 20:33:02 +00:00
Evan Cheng
14c4655403 isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37960 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:22:03 +00:00
Evan Cheng
0e4a276c72 Do not check isPredicated() on non-predicable instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37891 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:06:46 +00:00
Evan Cheng
bfd2ec4a8e Add a utility routine to check for unpredicated terminator instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 21:59:56 +00:00
Evan Cheng
f277ee4be7 Add missing const qualifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37341 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29 18:35:22 +00:00
Evan Cheng
d90733035d Rename a parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37307 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-23 07:21:11 +00:00
Evan Cheng
d9e9efb253 Remove. Not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37139 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-17 00:11:35 +00:00
Evan Cheng
e425956b72 Default implementation of TargetInstrInfo::getBlockSize().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37138 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 23:53:44 +00:00
Evan Cheng
02c602b333 PredicateInstruction returns true if the operation was successful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 21:53:07 +00:00
Evan Cheng
2eb80fa433 Add default implementation of PredicateInstruction().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37123 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 21:20:37 +00:00
Evan Cheng
cc22a7a2ad Move findTiedToSrcOperand to TargetInstrDescriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-08 18:45:48 +00:00
Evan Cheng
3cc3816cd4 Use MI's TargetInstrDescriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32352 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-08 07:57:56 +00:00
Evan Cheng
ba59a1e453 Match TargetInstrInfo changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32098 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-01 21:52:58 +00:00
Evan Cheng
6430bf0449 Remove the ugly SPARCV9 TargetInstrDescriptors hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32033 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-30 07:10:43 +00:00
Evan Cheng
ff608a7a69 commuteInstruction should propagate kill / dead info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31763 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-15 20:56:03 +00:00