Commit Graph

54 Commits

Author SHA1 Message Date
Jyotsna Verma
e41c7d4890 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:34:49 +00:00
Jyotsna Verma
4f2ef94d6a Hexagon: Use multiclass for gp-relative instructions.
Remove noV4T gp-relative instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 16:25:57 +00:00
Jyotsna Verma
7bb9585c6e Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 15:43:57 +00:00
Jyotsna Verma
97e602b574 Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 18:41:34 +00:00
Jyotsna Verma
cec50e6da2 Hexagon: Removed asserts regarding alignment and offset.
We are warning the user about the alignment, so we should not assert.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:08:03 +00:00
Jyotsna Verma
86df21767a Hexagon: Add patterns for zero extended loads from i1->i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 14:15:15 +00:00
Jyotsna Verma
a4dd8d6732 Hexagon: Handle i8, i16 and i1 Var Args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176647 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 20:28:34 +00:00
Jyotsna Verma
b6716187ca Hexagon: Add support to lower block address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 19:10:28 +00:00
Jyotsna Verma
0d44328ce8 reverting patch 176508.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 20:29:23 +00:00
Jyotsna Verma
c34f17140f Hexagon: Add support for lowering block address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 19:37:46 +00:00
Jyotsna Verma
18daead3ff Hexagon: Expand addc, adde, subc and sube.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 19:04:47 +00:00
Jyotsna Verma
ee0ef13eba Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 18:42:28 +00:00
Jyotsna Verma
ef94c6c85e Hexagon: Add constant extender support framework.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 17:37:13 +00:00
Anshuman Dasgupta
6585d3b64b Hexagon: Expand cttz, ctlz, and ctpop for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 19:39:40 +00:00
Jyotsna Verma
d6c98ae638 Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 16:13:27 +00:00
Anshuman Dasgupta
666e0d3bc4 Hexagon: add support for predicate-GPR copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 22:56:34 +00:00
Jyotsna Verma
f6563427c4 Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:38:46 +00:00
Jyotsna Verma
6b8d2026ba Hexagon: Add support to generate predicated absolute addressing mode
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 16:06:23 +00:00
Krzysztof Parzyszek
71490fa946 Extend Hexagon hardware loop generation to handle various additional cases:
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174904 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11 21:37:55 +00:00
Jyotsna Verma
1d3d2c57f5 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 19:20:45 +00:00
Jyotsna Verma
f2c4db97e1 Hexagon: Add testcase for post-increment store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174419 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 18:23:51 +00:00
Jyotsna Verma
691c365aad Hexagon: Use multiclass for absolute addressing mode stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 18:15:34 +00:00
Jyotsna Verma
4210da7253 Hexagon: Add V4 compare instructions. Enable relationship mapping
for the existing instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 16:42:24 +00:00
Jyotsna Verma
3e1635d08c Hexagon: Add V4 combine instructions and some more Def Pats for V2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04 15:52:56 +00:00
Jyotsna Verma
03b3771c6c Hexagon: Test case to confirm generation of indexed loads with zero offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 16:40:06 +00:00
Jyotsna Verma
a454ffd02a Add indexed load/store instructions for offset validation check.
This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17 18:42:37 +00:00
Matthew Curtis
ade50dc6c7 In hexagon convertToHardwareLoop, don't deref end() iterator
In particular, check if MachineBasicBlock::iterator is end() before
using it to call getDebugLoc();

See also this thread on llvm-commits:
   http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07 21:03:15 +00:00
Jyotsna Verma
61b632d9f7 Use multiclass to define store instructions with base+immediate offset
addressing mode and immediate stored value.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05 19:32:03 +00:00
NAKAMURA Takumi
d0a4a4bf5c test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the failure on i686 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167988 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 22:22:37 +00:00
Jyotsna Verma
cb02fa9d7f Added multiclass for post-increment load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 20:38:48 +00:00
Pranav Bhandarkar
4c3d3ecdf8 LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the
subreg_hireg of register pair Rp.

	* lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New
	 DenseMap similar to PeepholeMap that additionally records subreg info
	 too.
        (runOnMachineFunction): Record information in PeepholeDoubleRegsMap
        and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to
	the instruction Rx = COPY Rp1:logreg_subreg.
	* test/CodeGen/Hexagon/remove_lsr.ll: New test.
	



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163214 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 16:01:40 +00:00
Sergei Larin
3e59040810 Porting Hexagon MI Scheduler to the new API.
Change current Hexagon MI scheduler to use new converging
scheduler. Integrates DFA resource model into it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 14:49:56 +00:00
Jakob Stoklund Olesen
36d29bc723 Remove extra MayLoad/MayStore flags from atomic_load/store.
These extra flags are not required to properly order the atomic
load/store instructions. SelectionDAGBuilder chains atomics as if they
were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on
the memory operands of all atomic operations.

The volatile bit is enough to order atomic loads and stores during and
after SelectionDAG.

This means we set mayLoad on atomic_load, mayStore on atomic_store, and
mayLoad+mayStore on the remaining atomic read-modify-write operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 03:11:32 +00:00
Jakob Stoklund Olesen
4ad27eda29 Infer instruction properties from single-instruction patterns.
Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.

This causes a lot of instruction flags to change.

- Many instructions no longer have the UnmodeledSideEffects flag because
  their flags are now inferred from a pattern.

- Instructions with intrinsics will get a mayStore flag if they already
  have UnmodeledSideEffects and a mayLoad flag if they already have
  mayStore. This is because intrinsics properties are linear.

- Instructions with atomic_load patterns get a mayStore flag because
  atomic loads can't be reordered. The correct workaround is to create
  pseudo-instructions instead of using normal loads. PR13693.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 22:46:53 +00:00
Arnold Schwaighofer
d252aa43c9 [Hexagon] Don't mark callee saved registers as clobbered by a tail call
This was causing unnecessary spills/restores of callee saved registers.

Fixes PR13572.

Patch by Pranav Bhandarkar!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 19:54:01 +00:00
Bob Wilson
5f91a99427 Add test triples to fix win32 failures. Revert workaround from r161292.
I don't have a win32 system to test, so hopefully I got them all fixed here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 20:31:37 +00:00
Bob Wilson
53624a2df5 Refactor and check "onlyReadsMemory" before optimizing builtins.
This patch is mostly just refactoring a bunch of copy-and-pasted code, but
it also adds a check that the call instructions are readnone or readonly.
That check was already present for sin, cos, sqrt, log2, and exp2 calls, but
it was missing for the rest of the builtins being handled in this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161282 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 23:29:17 +00:00
Sirish Pande
0031af6615 Enable all Hexagon tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15 16:13:12 +00:00
Brendon Cahoon
5262abb268 Revert 156634 upon request until code improvement changes are made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14 19:35:42 +00:00
Sirish Pande
b33857040f Support for Hexagon feature, New Value Jump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 05:10:30 +00:00
Brendon Cahoon
6d532d8860 Hexagon constant extender support.
Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:56:59 +00:00
Sirish Pande
7517bbc91a Hexagon V5 FP Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 20:20:25 +00:00
Sirish Pande
26f61a158b Support for target dependent Hexagon VLIW packetizer.
This patch creates and optimizes packets as per Hexagon ISA rules.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 21:52:53 +00:00
Chandler Carruth
d410eaba04 Revert r155365, r155366, and r155367. All three of these have regression
test suite failures. The failures occur at each stage, and only get
worse, so I'm reverting all of them.

Please resubmit these patches, one at a time, after verifying that the
regression test suite passes. Never submit a patch without running the
regression test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23 18:25:57 +00:00
Sirish Pande
15e56ad885 Hexagon V5 (floating point) support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23 17:49:40 +00:00
Sirish Pande
1bfd24851e Support for Hexagon architectural feature, new value jump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23 17:49:28 +00:00
Sirish Pande
0dac3919e5 Support for Hexagon VLIW Packetizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155365 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23 17:49:20 +00:00
Sirish Pande
2f69e4cf32 Disable Hexagon test temporarily.
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.

The assert is as follows:
    assert(!MI->isTerminator() && !MI->isLabel() &&
               "Cannot schedule terminators or labels!");

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12 21:06:54 +00:00
Eli Bendersky
cc85160672 Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
* Removed test/lib/llvm.exp - it is no longer needed 
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
  left in the test suite so this code is no longer required. test/lit.cfg is
  now much shorter and clearer 
* Removed a lot of duplicate code in lit.local.cfg files that need access to
  the root configuration, by adding a "root" attribute to the TestingConfig
  object. This attribute is dynamically computed to provide the same
  information as was previously provided by the custom getRoot functions. 
* Documented the config.root attribute in docs/CommandGuide/lit.pod





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25 09:02:19 +00:00
Eli Bendersky
0f0c411079 Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 06:28:33 +00:00