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677 Commits

Author SHA1 Message Date
Owen Anderson
20ab29068d Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-12 07:39:39 +00:00
Anton Korobeynikov
f191c80cd7 Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-11 19:50:10 +00:00
Evan Cheng
cc41586b9d Much improved pic jumptable codegen: 
Then:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        imull   $4, %ecx, %ecx
        leal    LJTI1_0-"L1$pb"(%eax), %edx
        addl    LJTI1_0-"L1$pb"(%ecx,%eax), %edx
        jmpl    *%edx

        .align  2
        .set L1_0_set_3,LBB1_3-LJTI1_0
        .set L1_0_set_2,LBB1_2-LJTI1_0
        .set L1_0_set_5,LBB1_5-LJTI1_0
        .set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

Now:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        addl    LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
        jmpl    *%eax

		.align  2
		.set L1_0_set_3,LBB1_3-"L1$pb"
		.set L1_0_set_2,LBB1_2-"L1$pb"
		.set L1_0_set_5,LBB1_5-"L1$pb"
		.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43924 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-09 01:32:10 +00:00
Lauro Ramos Venancio
e0cb36b9fb [ARM] Implement __builtin_thread_pointer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43892 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-08 17:20:05 +00:00
Rafael Espindola
f1ba1cad38 Move the LowerMEMCPY and LowerMEMCPYCall to a common place. 
Thanks for the suggestions Bill :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-05 23:12:20 +00:00
Lauro Ramos Venancio
8699a97a2e [ARM] Fix code generation for: 
static __thread struct {
    int a;
    int b;
} teste = {0, 0};



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43722 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-05 18:33:37 +00:00
Duncan Sands
ca0ed74485 Eliminate the remaining uses of getTypeSize. This 
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43688 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-05 00:04:43 +00:00
Rafael Espindola
e0703c84dd Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold 
and by restructuring the X86 version.

New I just have to move this to a common place :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-31 14:39:58 +00:00
Rafael Espindola
fc05f402ea Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-31 11:52:06 +00:00
Dale Johannesen
ca4571e79f Support non-POSIX hosts by removing use of strncasecmp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43364 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-25 21:54:43 +00:00
Evan Cheng
4102eb57bb Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-22 22:11:27 +00:00
Rafael Espindola
7b73a5d6de split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43176 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-19 14:35:17 +00:00
Chris Lattner
3a7c33a853 Add an easy microoptimization I noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43164 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-19 03:29:26 +00:00
Evan Cheng
f0a0cddbcd - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. 
- Fix some copy+paste bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-18 22:40:57 +00:00
Evan Cheng
58184e6878 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-18 21:29:24 +00:00
Christopher Lamb
a4c791072f Fix a misnamed parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43145 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-18 19:29:45 +00:00
Chris Lattner
65a3323b0a legalizing the ret operation on f64 shouldn't introduce a new 
i64 bit convert needlessly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43116 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-18 06:17:07 +00:00
Evan Cheng
347d39f1fd Revert 42908 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42960 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-14 05:57:21 +00:00
Dan Gohman
8ddde0a151 Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42908 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 14:53:36 +00:00
Dan Gohman
f96e4de403 Set ISD::FPOW to Expand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-11 23:21:31 +00:00
Dan Gohman
525178cdbf Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to 
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-08 18:33:35 +00:00
Evan Cheng
66f0f64082 - Added a few target hooks to generate load / store instructions from / to any 
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-05 01:32:41 +00:00
Dan Gohman
cb406c2597 Use empty() member functions when that's what's being tested for instead 
of comparing begin() and end().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42585 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-03 19:26:29 +00:00
Gordon Henriksen
cd8bc05102 AsmPrinters overriding getAnalysisUsage should call super. 
And not super's super, either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42482 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-30 13:39:29 +00:00
Evan Cheng
9efce638d3 Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-26 06:25:56 +00:00
Dan Gohman
677ccc6e8b More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42316 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-25 20:27:06 +00:00
Evan Cheng
76a4023096 Honor user-defined section specification of a global, ignores whether its initializer is null. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42182 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-21 00:41:19 +00:00
Evan Cheng
17207ddf38 Enable if-conversion for ARM by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42156 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-20 00:48:22 +00:00
Evan Cheng
e71bff7405 Avoid referencing deleted instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-19 21:48:07 +00:00
Dan Gohman
92dfe2001e Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-14 20:33:02 +00:00
Bill Wendling
fe4afb17d3 Enable indirect encoding for the personality function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41873 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 23:55:40 +00:00
Evan Cheng
071a279e94 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:55:27 +00:00
Duncan Sands
f7331b3dd7 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 14:10:23 +00:00
Evan Cheng
be36798bfe 80 col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 22:22:23 +00:00
Chris Lattner
bf8ae84a21 Add some notes about better flag handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41808 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 21:43:18 +00:00
Owen Anderson
718cb665ca Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 04:06:50 +00:00
Dale Johannesen
eaf089430e Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-31 04:03:46 +00:00
Raul Herbster
8c132633c8 Instruction formats added used to generate multiply instructions of V5TE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41629 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:34:14 +00:00
Raul Herbster
b94e60872e Unused relocation type reloc_arm_absolute removed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41628 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:31:35 +00:00
Raul Herbster
9c1a3827ce Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41627 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:29:26 +00:00
Raul Herbster
37fb5b154c ARM instruction table was modified by adding information to generate multiply instruction of V5TE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41626 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:25:47 +00:00
Raul Herbster
d05c04c169 JITInfo now resolves function addrs and also relocations. It always emits a stub. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41625 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:21:27 +00:00
Evan Cheng
35b35c5c32 Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 05:52:20 +00:00
Evan Cheng
0ff94f7fcc Initial JIT support for ARM by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:37:15 +00:00
Dan Gohman
61e729e2e9 More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:21:54 +00:00
Evan Cheng
7fc77611ef Indexed loads each has 2 outputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 00:12:08 +00:00
Dan Gohman
f452207d20 More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40589 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-30 14:51:59 +00:00
Duncan Sands
36397f5034 Support for trampolines, except for X86 codegen which is 
still under discussion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-27 12:58:54 +00:00
Dan Gohman
b8275a3f6f Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-25 19:33:14 +00:00
Evan Cheng
ffbaccae02 No more noResults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-21 00:34:19 +00:00
Evan Cheng
8bd6035750 Added -print-emitted-asm to print out JIT generated asm to cerr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-20 21:56:13 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Evan Cheng
4558b807a2 Only adjust esp around calls in presence of alloca. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 00:42:58 +00:00
Chris Lattner
c3dbe70ce7 no email addrs in file headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 05:56:43 +00:00
Anton Korobeynikov
2365f51ed0 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-14 14:06:15 +00:00
Dale Johannesen
66a2a8f878 ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39782 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-12 16:45:35 +00:00
Dale Johannesen
5d9c4b6020 Fix hang compiling TimberWolf (allow for islands 
of size other than 4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39743 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 18:32:38 +00:00
Evan Cheng
8202010364 Didn't mean the last commit. Revert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38515 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 22:00:16 +00:00
Evan Cheng
c608ff22e7 Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 21:49:47 +00:00
Evan Cheng
13ab020ea0 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:08:01 +00:00
Chris Lattner
87bdba6d6a The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 17:25:29 +00:00
Evan Cheng
9ad6f03166 No need for ccop anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:34:09 +00:00
Evan Cheng
4b9cb7d135 Incorrect check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:23:19 +00:00
Evan Cheng
06aae67b83 Do away with ImmutablePredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:22:46 +00:00
Evan Cheng
dfb2ebac29 Print the s bit if the instruction is toggled to its CPSR setting form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37932 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 01:01:34 +00:00
Evan Cheng
04c813d00c PredicateDefOperand -> OptionalDefOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37931 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 01:00:49 +00:00
Evan Cheng
148b6a419f Initial ARM JIT support by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37926 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 21:15:40 +00:00
Evan Cheng
d54874a06d Unbreak the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37914 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:13:19 +00:00
Gabor Greif
a99be51bf5 Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:07:56 +00:00
Evan Cheng
0e1d37904a Reflects the chanegs made to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:18:20 +00:00
Evan Cheng
16b6598325 Added ARM::CPSR to represent ARM CPSR status register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:17:13 +00:00
Evan Cheng
ee568cf794 Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:15:27 +00:00
Evan Cheng
c85e832eb7 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:13:32 +00:00
Evan Cheng
3b5b8368f3 Added ARM::CPSR to represent ARM CPSR status register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37894 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:11:03 +00:00
John Criswell
e644ef7b09 Convert .cvsignore files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 16:35:07 +00:00
Evan Cheng
e2446c6076 Silence a warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37737 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 18:31:22 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 00:48:07 +00:00
Owen Anderson
0819a9d386 Fix the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37705 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 16:59:54 +00:00
Dan Gohman
ea859be53c Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 14:59:07 +00:00
Dale Johannesen
5411835165 Quote complex names for Darwin X86 and ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37700 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 00:54:56 +00:00
Evan Cheng
97e604e7d8 Be more conservative of duplicating blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37669 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 23:55:02 +00:00
Evan Cheng
277f0741c5 Allow predicated immediate ARM to ARM calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37659 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 21:05:09 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:26:51 +00:00
Evan Cheng
d42e56e166 Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37606 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-15 21:15:00 +00:00
Dale Johannesen
13e8b51e3e Handle blocks with 2 unconditional branches in AnalyzeBranch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-13 17:59:52 +00:00
Evan Cheng
bfd2ec4a8e Add a utility routine to check for unpredicated terminator instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 21:59:56 +00:00
Lauro Ramos Venancio
61718a6285 Define AsmTransCBE for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37527 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 21:06:23 +00:00
Evan Cheng
1fc7cb695c Fix ARM condition code subsumission check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37517 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 09:14:47 +00:00
Evan Cheng
f81dea45b5 tBcc is not a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37516 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 09:13:23 +00:00
Evan Cheng
9328c1ac66 Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37484 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-07 01:37:54 +00:00
Evan Cheng
2c614c5c69 Mark these instructions clobbersPred. They modify the condition code register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-06 10:17:05 +00:00
Evan Cheng
5e148a37d3 Print predicate of the second instruction of the two-piece constant MI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37437 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-05 18:55:18 +00:00
Evan Cheng
341dcccb4e PIC label asm printing cosmetic changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37434 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-05 07:36:38 +00:00
Chris Lattner
c621ae7bba update this entry, now that Anton implemented shift/and lowering for 
switches.  There is one really easy isel thing here with tst we are not
getting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37400 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-02 18:45:14 +00:00
Evan Cheng
c354334ac4 Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37388 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 20:51:29 +00:00
Evan Cheng
144fd1ff0f Set ARM ifcvt duplication limit to 3 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37385 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 08:28:59 +00:00
Evan Cheng
df4da14948 Make jumptable non-predicable for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37381 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 00:56:15 +00:00
Chris Lattner
3a4205367d Fix the asmprinter so that a globalvalue can specify an explicit alignment 
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37373 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-31 18:57:45 +00:00
Evan Cheng
c6f2f6fbb9 For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 23:34:19 +00:00
Evan Cheng
fd488edb1d For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37349 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 23:32:06 +00:00
Evan Cheng
62ccdbf0b3 Add missing const qualifiers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 18:42:18 +00:00
Evan Cheng
69d555611a Hooks for predication support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37308 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-23 07:22:05 +00:00
Evan Cheng
94679e66bb Fix some -march=thumb regressions. tBR_JTr is not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37272 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 23:17:32 +00:00
Dale Johannesen
f23b8cf239 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37271 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 22:42:04 +00:00
Dale Johannesen
86d4069666 Add some patterns for PIC PC-relative loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37269 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 22:14:33 +00:00
Evan Cheng
5a18ebc70c BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37268 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 18:56:31 +00:00
Evan Cheng
dcc50a4aee Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37199 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 01:53:54 +00:00
Evan Cheng
e5e7ce458a Silence some compilation warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37197 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 01:19:57 +00:00
Evan Cheng
9f8cbd147c Set ARM if-conversion block size threshold to 10 instructions for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:19:34 +00:00
Evan Cheng
6ae3626a4f RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:18:17 +00:00
Dale Johannesen
8dd86c14d4 More effective breakdown of memcpy into repeated load/store. These are now 
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37179 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 21:31:21 +00:00
Evan Cheng
3f8602cf20 ARM::tB is also predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37125 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:53:43 +00:00
Evan Cheng
02c602b333 PredicateInstruction returns true if the operation was successful. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:53:07 +00:00
Evan Cheng
75604f81b7 Move if-conversion after all passes that may use register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37120 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:52:46 +00:00
Evan Cheng
b5f8eff566 Removed isPredicable(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37119 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:50:23 +00:00
Evan Cheng
5ada199246 Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37118 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:50:01 +00:00
Evan Cheng
aeafca0a25 Conditional branch is not a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37103 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 07:45:54 +00:00
Evan Cheng
2706f9771d Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37098 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 05:14:06 +00:00
Evan Cheng
9307292ae2 Hooks for predication support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37093 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 02:01:49 +00:00
Evan Cheng
44bec52b1b Add PredicateOperand to all ARM instructions that have the condition field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:29:07 +00:00
Lauro Ramos Venancio
5d3d44a848 Fix previous patch. GOTOFF can be used only when the symbol has internal 
linkage or hidden visibility.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37055 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-14 23:20:21 +00:00
Lauro Ramos Venancio
930d161ba2 Optimize PIC implementation. GOTOFF can be used when the symbol is defined 
and used in the same module.


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 2007-05-14 18:46:23 +00:00
Lauro Ramos Venancio
69642f11ed Enable aliases on arm-linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37042 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-14 18:32:56 +00:00
Evan Cheng
42d712b306 Switch BCC, MOVCCr, etc. to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 21:08:43 +00:00
Lauro Ramos Venancio
356e72c4f1 Fix PR1390 in a better way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36916 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 23:15:16 +00:00
Evan Cheng
c4e600362e This is no longer needed after enabling the DAG combiner xform. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36909 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 21:29:41 +00:00
Lauro Ramos Venancio
8f57667a5d Fix PR1390. 
Don't spill extra register to align the stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36814 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-05 23:44:41 +00:00
Lauro Ramos Venancio
a8e9562906 Add a processor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36765 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-04 22:16:30 +00:00
Evan Cheng
97c9bb5cc6 On Mac OS X, GV requires an extra load only when relocation-model is non-static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36718 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-04 00:26:58 +00:00
Evan Cheng
bdc9869dbf Should never see an indexed load / store with zero offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36714 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 23:30:36 +00:00
Dale Johannesen
4ac075c859 Evan's patch to avoid FPreg->intreg copy for cvt; store to mem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 20:54:42 +00:00
Lauro Ramos Venancio
e8e5495474 Debug support for arm-linux. 
Patch by Raul Herbster.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36690 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 20:28:35 +00:00
Chris Lattner
388488d604 add support for printing offset from global 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36669 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 16:42:23 +00:00
Evan Cheng
0b0a9a90a4 Typo. It's checking if V is multiple of 4, not multiple of 3. :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36663 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 02:00:18 +00:00
Devang Patel
1997473cf7 Drop 'const' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 01:11:54 +00:00
Chris Lattner
72939126d4 match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 00:32:00 +00:00
Devang Patel
3e15bf33e0 Use 'static const char' instead of 'static const int'. 
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 21:39:20 +00:00
Dale Johannesen
67cf561b7f Add some support for (Darwin) code-generating directives in getInlineAsmLength. 
Support is incomplete, but more accurate than gcc's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36634 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 01:02:40 +00:00
Devang Patel
794fd75c67 Do not use typeinfo to identify pass in pass manager. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 21:15:47 +00:00
Evan Cheng
1b20168433 Doh. PC displacement is between the constantpool and the add instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36630 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 20:27:19 +00:00
Evan Cheng
97de913821 eliminateFrameIndex() change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 09:13:03 +00:00
Evan Cheng
5c3885ce8e Under normal circumstances, when a frame pointer is not required, we reserve 
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36607 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 00:52:08 +00:00
Dale Johannesen
9118dbc7bd Remove item: thumb padding in constant islands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36586 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-30 00:32:06 +00:00
Dale Johannesen
23c968478e remove unused variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36585 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-30 00:30:48 +00:00
Lauro Ramos Venancio
0a1817392d Enable protected visibility on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36583 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-30 00:23:51 +00:00
Dale Johannesen
8593e41855 Rewrite of Thumb constant islands handling (exact allowance for padding 
around islands and jump tables).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36573 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-29 19:19:30 +00:00
Dale Johannesen
8650199fbb Make ARM-specific version of getInlineAsmLength 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36572 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-29 19:17:45 +00:00
Dale Johannesen
caa8055cf5 change per review 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36519 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-28 00:36:37 +00:00
Dale Johannesen
25c1f9e125 Prevent Thumb code from generating ARM instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36518 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 22:17:18 +00:00