Jim Grosbach
f8dabac604
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
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in the MC lowering process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 21:05:55 +00:00
Evan Cheng
c4af4638df
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
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and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 20:13:28 +00:00
Jim Grosbach
89e14c7579
More ARM encoding bits. LDRH now encodes properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 18:11:11 +00:00
Bill Wendling
0f63075613
Proper encoding for VLDM and VSTM instructions. The register lists for these
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instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 04:32:08 +00:00
Bill Wendling
3380f6a4d0
Use the correct variable names so that the encodings will be correct.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119403 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16 23:44:49 +00:00
Jim Grosbach
7911916cf7
ARM conditional mov encoding fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16 18:13:42 +00:00
Bill Wendling
7b71878d9f
- Remove dead patterns.
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- Add encodings to the *LDMIA_RET instrs. Probably not needed...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16 02:08:45 +00:00
Bill Wendling
73fe34a3ee
Encode the multi-load/store instructions with their respective modes ('ia',
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'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16 01:16:36 +00:00
Jim Grosbach
99f53d13ef
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 20:47:07 +00:00
Jim Grosbach
17e967eac2
Nuke redundant encoding bit set.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 18:17:24 +00:00
Chris Lattner
2ac190238e
add fields to the .td files unconditionally, simplifying tblgen a bit.
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Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 05:19:05 +00:00
Bill Wendling
c93989a060
Comment out the defms until they're activated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 11:20:05 +00:00
Bill Wendling
ddc918b379
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:57:02 +00:00
Bill Wendling
1f4abcfa5c
Convert the modes to lower case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:43:34 +00:00
Bill Wendling
04863d06fb
Minor cleanups:
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- Get the opcode once.
- Add a ParserMatchClass to reglist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:40:19 +00:00
Bill Wendling
6c470b806f
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
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future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 09:09:38 +00:00
Evan Cheng
c47f7d643e
Conditional moves are slightly more expensive than moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 05:14:20 +00:00
Evan Cheng
63f3544a7f
Add conditional move of large immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 02:25:14 +00:00
Jim Grosbach
df7e0f8d5d
Swap multiclass operand order for consistency with other patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 01:28:30 +00:00
Jim Grosbach
0f6e33b0c8
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118963 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 01:07:20 +00:00
Jim Grosbach
9e0bfb5829
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
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flag for the LDRT/STRT family instructions as a side effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:35:48 +00:00
Evan Cheng
11c11f8ab0
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:46:13 +00:00
Evan Cheng
893d7fe209
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:03:38 +00:00
Evan Cheng
875a6ac09a
Add conditional mvn instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 22:42:47 +00:00
Jim Grosbach
e1634e9351
Zap a copy/paste-o bit of dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118926 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:29:10 +00:00
Jim Grosbach
2716e25c2c
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
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to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:28:15 +00:00
Jim Grosbach
d75c3f136b
Fill in the default predication bits for ARM unconditional branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 18:13:26 +00:00
Jim Grosbach
d1d5a39cad
ARM fixup encoding for direct call instructions (BL).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 20:05:40 +00:00
Jim Grosbach
c466b937db
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:04:49 +00:00
Jim Grosbach
7eab97f260
Encoding for ARM LDRSH_POST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 16:55:29 +00:00
Jim Grosbach
928f3325a7
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:55:59 +00:00
Jim Grosbach
d507d1f616
Fix encoding of Ra register for ARM smla* instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:27:41 +00:00
Jim Grosbach
570a922691
ARM STRH encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:09:40 +00:00
Jim Grosbach
954ffff79b
Move LDM predicate operand encoding into base clase. Add STM missing STM
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encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:44:32 +00:00
Jim Grosbach
5d5eb9e381
ARM LDM encoding for the mode (ia, ib, da, db) operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:38:36 +00:00
Jim Grosbach
c1235e2a4e
Fix ARM encoding of non-return LDM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:18:49 +00:00
Jim Grosbach
866aa394ca
Fix ARM encoding of LDM+Return instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:12:48 +00:00
Jim Grosbach
e0ee08e367
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 18:43:54 +00:00
Jim Grosbach
54fea632b1
Add encoder method for ARM load/store shifted register offset operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:20:53 +00:00
Bill Wendling
5e559a22c1
Revert r118457 and r118458. These won't hold for GPRs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 00:30:18 +00:00
Bill Wendling
3734ef3fb4
reglist has two operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:50:20 +00:00
Bill Wendling
5991487c10
Make RegList an ASM operand so that TableGen will generate code for it. This is
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an initial implementation and may change once reglists are fully fleshed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 00:39:58 +00:00
Evan Cheng
416941d50f
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 05:19:35 +00:00
Evan Cheng
dfed19fe2c
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 06:34:55 +00:00
Evan Cheng
bc7deb0f75
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 05:14:24 +00:00
Bill Wendling
92b5a2eb16
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
Jim Grosbach
e6913600c7
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:01:43 +00:00
Chris Lattner
a1ca91af4e
Completely reject instructions that have an operand in their
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ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:40:41 +00:00
Bill Wendling
5df0e0a61d
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
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with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
Owen Anderson
a2b50b300e
Rename encoder methods to match naming convention.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:28:01 +00:00