There were a few things wrong with the SD card write implementation:
1. The protocol change regarding the interpretation of offsets
introduced with SDHC cards was not taken into account in the write
path, unlike in the read path.
2. All SPI writes involved in the process were actually issued as reads
due to the use of the SPI_RW() function, the implementation of which
seems to have gone through some churn. Likely just an instance of
bit-rot.
From the Cyclone IV device handbook:
> When you use the VREF pin as a regular input or output, you can expect
> a reduced performance of toggle rate and tCO because of higher pin
> capacitance.
Previously, we had set all HDMI_TX pins to fast output, but doing so
produces some worrying timing violations which were masked over by
relaxation of the SDC constraints. With fast output enabled, actually
fixing the timing constraints would require substantial RTL
optimization.
Instead, by only setting fast output on the VREF pins, I'm able to avoid
the glitching that would occur without any fast output pins when
displaying high clock rate line3x output, while also allowing fitter
enough flexibility to avoid timing violations.
In addition, this commit restores the previously relaxed HDMI_TX timing
constraints to those documented in the IT6613 datasheet.
This commit adds both a 480p input sampling mode and line2x optimized
mode for the PSP's 480x272 picture. The line2x optimized mode is enabled
automatically when the sampling mode is selected.
When in-game, the PSP outputs a letterboxed 480p picture. The active
portion of the screen is 480x272, but is treated as 480p (480x720).
In addition, a line2x optimized mode is added which produces a 960x544
output picture, which if desired the top + bottom pixels can be dropped
producing a 960x540 (qHD) picture.
To generate a qHD picture, use the following settings:
V. Active: 270
V. Backporch: 135
Quartus calculates fmax (the theoretical maximum clock rate) based on
the entirety of the logic between registers. In the case of the pclk_*
lines, this includes some invalid paths which cross between the
3x <-> 2x and 5x <-> 4x clock domains. This is because these clocks
share output pins from the PLL, but the PLL is configured to output only
one of these clocks at a time, and the correct output from the logic is
selected via a multiplexer. Therefore these paths cannot co-occur.
This has the effect of increasing the calculated fmax of these paths to:
pclk_3x: 107.98 MHz -> 132.52 MHz
pclk_5x: 162.23 MHz -> 170.33 MHz
This change allows highly letterboxed content (e.g. the PSP's 480x272
picture in a 720x480 frame) to be "zoomed" to a full screen picture by
treating the letterbox as horizontal and vertical backporch.
Co-authored-by: Chris Lockfort <clockfort@gmail.com>
* fix clock selection function implementation
* add support for ALC filter configuration
* add coarse clamp LPF selection
* add support for clamp/ALC offset
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
