Russell Harmon
c2b0687e7b
Set fast output on HDMI_TX pins.
...
Also adjust timing constraits to reflect working state with line3x at
162 MHz.
2020-06-14 09:54:06 +00:00
Russell Harmon
d80a9fbb0c
Ignore paths which use shared clock lines.
...
Quartus calculates fmax (the theoretical maximum clock rate) based on
the entirety of the logic between registers. In the case of the pclk_*
lines, this includes some invalid paths which cross between the
3x <-> 2x and 5x <-> 4x clock domains. This is because these clocks
share output pins from the PLL, but the PLL is configured to output only
one of these clocks at a time, and the correct output from the logic is
selected via a multiplexer. Therefore these paths cannot co-occur.
This has the effect of increasing the calculated fmax of these paths to:
pclk_3x: 107.98 MHz -> 132.52 MHz
pclk_5x: 162.23 MHz -> 170.33 MHz
2020-06-01 00:31:44 +00:00
marqs
9d496383c3
optimize clock network
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* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
marqs
9e81fb5922
Scanline updates and fixes
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* Enable overlay pattern customization
* Fix non-alternating mode with line4x interlace sources
* Add alternate interval option for pre-linedoubled sources
2019-03-23 00:09:46 +02:00
marqs
9ad696dbc3
optimize away one pp stage and unify code formatting
2018-03-12 01:25:23 +02:00
marqs
ba648dd5fe
additional timing constraint fixes
2018-03-11 22:22:04 +02:00
marqs
0ab31b30b4
simplify timing constraints
2018-03-07 09:21:19 +02:00
marqs
a24d6b0e3a
Update latency tester
...
* Enable operation with all sources
* Measure strobe length on low-persistence displays
2017-10-28 12:10:54 +03:00
marqs
a8d1fad24a
sdc: update input pclk parameters
...
-rename to pclk_direct/pclk_indirect for clarity
-raise pclk_indirect from 27MHz to 33MHz to match actual line5x:ed input
2017-10-22 22:39:15 +03:00
marqs
75e072d622
Revert some drive strength adjustments to meet timing requirements
2017-10-13 21:03:48 +03:00
marqs
4b21a354b4
Fix and optimize reverse lpf activation
2017-10-12 02:31:19 +03:00
paulb-nl
ac16008076
Add reverse LPF feature
...
reverse LPF can be used to mostly reverse the blur on pre 1-CHIP SNES.
For best results use 256x240 optimized mode.
2017-09-27 22:43:26 +02:00
marqs
2aee3294e3
Fix HDTV mode parameters
2017-05-30 21:16:03 +03:00
marqs
2577470abe
Clean up TX setup code and add compatibility options
2017-05-29 20:43:24 +03:00
marqs
4f36278cb7
Sync processing rewritten and some issues fixed
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* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option
2017-05-18 23:36:37 +03:00
marqs
6e043ef577
Improve input mode handling
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* New options and better compatibility for Line5x
* Add support for 960i and 1080i
* Make TVP HPLL2x option user-selectable
2017-02-07 23:04:30 +02:00
marqs
3b19b2843c
Preliminary Line5x implementation
2017-01-29 13:02:12 +02:00
marqs
d41c7522a0
Misc updates
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* Fix mask placement and make its brightness adjustable
* Line4x
2017-01-24 00:18:15 +02:00
marqs
d77c293b70
* Clean up some FPGA code
...
* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
2016-12-31 14:18:21 +02:00
marqs
2dee0a2eb5
* R/G/B gain/offset controls added
...
* misc optimizations
2016-08-20 15:54:28 +03:00
marqs
827df7930f
* L3 optimized mode scanlines fixed
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* Advanced timing tweaker implemented
2016-08-16 22:45:23 +03:00
marqs
388c464f63
Initial public release (FW 0.64)
2016-02-23 01:03:50 +02:00
