Alan Garfield
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e9ff2b294e
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more project file fiddles by the tool. :/
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2018-01-28 00:23:43 +11:00 |
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Alan Garfield
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0fc84e0b37
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added reset logic to uart and CPU
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2018-01-28 00:23:09 +11:00 |
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Alan Garfield
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f081eb674f
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added pretend UART RX waveform
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2018-01-28 00:21:48 +11:00 |
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Alan Garfield
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b42567e759
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fiddled project files from icecube
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2018-01-28 00:19:59 +11:00 |
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Alan Garfield
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abba4eeee6
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added reset to cpu registers and made uart ignore first tx
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2018-01-27 22:56:28 +11:00 |
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Alan Garfield
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bcaf9e6962
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Yay got iverilog sim working!
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2018-01-27 22:13:52 +11:00 |
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Alan Garfield
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c4d42fae3c
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fixed testbench and split CPU cores
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2018-01-27 17:00:33 +11:00 |
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Alan Garfield
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04323a6256
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more moving around, added params for hex files
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2018-01-27 14:27:10 +11:00 |
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Alan Garfield
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0ca73c561a
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fixed project path for HX8K
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2018-01-27 13:58:03 +11:00 |
Alan Garfield
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401e987548
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Merge pull request #5 from alangarf/boards
Implement support for boards
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2018-01-27 13:52:04 +11:00 |
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Alan Garfield
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149334259d
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Cleaned up mess, and added HX8K board top file
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2018-01-27 13:40:59 +11:00 |
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Alan Garfield
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305d9b614b
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Merge pull request #3 from trcwm/boards
Disabled ice40 specific define and clock generation. Added Terasic DE…
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2018-01-27 12:54:38 +11:00 |
Niels Moseley
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5e3f065223
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Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined
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2018-01-27 01:21:47 +01:00 |
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Niels Moseley
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f19344cf58
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Editted CPU and testbench for better simulation
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2018-01-27 00:48:05 +01:00 |
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Niels Moseley
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9465e0c14d
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Added synchronous reset to clk enable divider to avoid undefined logic state in simulation
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2018-01-26 23:41:58 +01:00 |
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Niels Moseley
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cca11b7925
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Added iverilog simulation support
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2018-01-26 23:32:31 +01:00 |
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Niels Moseley
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34078e13ae
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Fixed cpu_clken wire -> reg
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2018-01-26 22:59:43 +01:00 |
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Niels Moseley
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f067774293
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Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.
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2018-01-26 22:38:46 +01:00 |
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Niels Moseley
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9beb3e5f5e
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Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files.
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2018-01-26 21:29:12 +01:00 |
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Alan Garfield
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7bdccf3d1a
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move things around.
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2018-01-27 00:21:05 +11:00 |
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Alan Garfield
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2b91bb3841
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moved some files around to clean things up a bit
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2018-01-12 15:17:35 +11:00 |
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Alan Garfield
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50d80bedcd
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Merge pull request #1 from alangarf/alangarf-readme
Updated readme
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2018-01-12 14:42:57 +11:00 |
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Alan Garfield
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83786cc594
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Update README.md
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2018-01-12 14:42:42 +11:00 |
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Alan Garfield
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ed76bfaa0a
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Added HX8K board image
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2018-01-12 14:39:58 +11:00 |
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Alan Garfield
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51fc482c08
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Update README.md
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2018-01-12 14:36:55 +11:00 |
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Alan Garfield
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c6a1c6b869
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Update README.md
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2018-01-12 14:34:36 +11:00 |
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Alan Garfield
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b70f32937c
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Update README.md
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2018-01-12 14:32:42 +11:00 |
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Alan Garfield
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080e3e5cef
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Update README with new logo
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2018-01-12 14:17:39 +11:00 |
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Alan Garfield
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92dd0d2e71
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moved sources into rtl to clean up root
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2018-01-12 13:40:44 +11:00 |
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Alan Garfield
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697bd34798
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Fixed issue with basic ROM
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2018-01-12 01:01:34 +11:00 |
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Alan Garfield
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158510c299
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Added basic ROM and fiddled things
Clock now runs at 6MHz while I try to simplify things to figure out a
CPU bug
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2018-01-10 16:39:18 +11:00 |
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Alan Garfield
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ae1d371e37
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Added small images
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2018-01-02 01:33:47 +11:00 |
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Alan Garfield
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3f9d786769
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Added basic images of breakout board
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2018-01-02 01:28:31 +11:00 |
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Alan Garfield
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6b48bdbb05
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Update README.md
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2018-01-02 01:18:19 +11:00 |
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Alan Garfield
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3a69b0eda0
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Update README.md
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2018-01-02 01:15:44 +11:00 |
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Alan Garfield
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5ff6a2ecf3
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Update README.md
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2018-01-02 01:05:27 +11:00 |
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Alan Garfield
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117d18ea54
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Update README.md
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2018-01-02 01:05:01 +11:00 |
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Alan Garfield
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b841685a9a
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Update README.md
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2018-01-02 01:04:35 +11:00 |
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Alan Garfield
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197d6a145e
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Update README.md
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2018-01-02 00:57:46 +11:00 |
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Alan Garfield
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31f20d49b4
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Update README.md
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2018-01-02 00:56:57 +11:00 |
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Alan Garfield
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8aad887a5e
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Initial commit
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2018-01-02 00:33:20 +11:00 |
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Alan Garfield
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e2b390bbd6
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Initial commit
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2018-01-02 00:23:13 +11:00 |