2005-10-14 23:40:39 +00:00
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//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
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2004-06-21 16:55:25 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2004-08-09 17:24:04 +00:00
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// This file describes the subset of the 32-bit PowerPC instruction set, as used
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// by the PowerPC instruction selector.
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2004-06-21 16:55:25 +00:00
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//
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//===----------------------------------------------------------------------===//
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2005-10-14 23:40:39 +00:00
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include "PPCInstrFormats.td"
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2004-06-21 16:55:25 +00:00
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2006-03-01 05:50:56 +00:00
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//===----------------------------------------------------------------------===//
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// PowerPC specific type constraints.
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//
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def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
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SDTCisVT<0, f64>, SDTCisPtrTy<1>
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]>;
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def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
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SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
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]>;
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def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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2006-03-20 01:53:53 +00:00
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def SDT_PPCvperm : SDTypeProfile<1, 3, [
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SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
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]>;
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2006-03-31 05:13:27 +00:00
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def SDT_PPCvcmp : SDTypeProfile<1, 3, [
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2006-03-26 10:06:40 +00:00
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
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]>;
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Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
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def SDT_PPCcondbr : SDTypeProfile<0, 3, [
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SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
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]>;
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2006-07-10 20:56:58 +00:00
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def SDT_PPClbrx : SDTypeProfile<1, 3, [
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SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
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]>;
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def SDT_PPCstbrx : SDTypeProfile<0, 4, [
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SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
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]>;
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2005-10-25 20:41:46 +00:00
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//===----------------------------------------------------------------------===//
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// PowerPC specific DAG Nodes.
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//
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def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
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def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
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def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
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2006-03-01 05:50:56 +00:00
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def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
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2005-10-25 20:41:46 +00:00
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2005-10-25 20:55:47 +00:00
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def PPCfsel : SDNode<"PPCISD::FSEL",
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// Type constraint for fsel.
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SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
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SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
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2005-09-08 19:50:41 +00:00
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2005-12-13 22:55:22 +00:00
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def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
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def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
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def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
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def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
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2005-11-17 07:30:41 +00:00
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2006-03-20 01:53:53 +00:00
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def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
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2006-03-19 06:55:52 +00:00
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2005-12-06 02:10:38 +00:00
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// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
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// amounts. These nodes are generated by the multi-precision shift code.
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def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
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def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
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def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
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When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
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def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
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def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
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2005-12-04 19:01:59 +00:00
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// These are target-independent nodes, but have target-specific formats.
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2006-08-11 09:03:33 +00:00
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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2005-12-04 19:01:59 +00:00
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2006-06-27 18:36:44 +00:00
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def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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2006-05-17 19:00:46 +00:00
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def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
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2006-05-17 06:01:33 +00:00
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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2006-05-17 19:00:46 +00:00
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def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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2006-05-17 06:01:33 +00:00
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2006-05-17 19:00:46 +00:00
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def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
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2006-01-09 18:28:21 +00:00
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[SDNPHasChain, SDNPOptInFlag]>;
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2005-12-20 00:26:01 +00:00
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2006-03-31 05:13:27 +00:00
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def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
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def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
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2006-03-26 10:06:40 +00:00
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Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
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def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
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[SDNPHasChain, SDNPOptInFlag]>;
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2006-07-10 20:56:58 +00:00
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def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
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def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
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2005-09-08 19:50:41 +00:00
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//===----------------------------------------------------------------------===//
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2005-09-09 00:39:56 +00:00
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// PowerPC specific transformation functions and pattern fragments.
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//
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Woo, it kinda works. We now generate this atrociously bad, but correct,
code for long long foo(long long a, long long b) { return a + b; }
_foo:
or r2, r3, r3
or r3, r4, r4
or r4, r5, r5
or r5, r6, r6
rldicr r2, r2, 32, 31
rldicl r3, r3, 0, 32
rldicr r4, r4, 32, 31
rldicl r5, r5, 0, 32
or r2, r3, r2
or r3, r5, r4
add r4, r3, r2
rldicl r2, r4, 32, 32
or r4, r4, r4
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23809 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 01:12:32 +00:00
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2005-10-19 18:42:01 +00:00
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def SHL32 : SDNodeXForm<imm, [{
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// Transformation function: 31 - imm
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return getI32Imm(31 - N->getValue());
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}]>;
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def SRL32 : SDNodeXForm<imm, [{
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// Transformation function: 32 - imm
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return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
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}]>;
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2005-09-09 00:39:56 +00:00
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def LO16 : SDNodeXForm<imm, [{
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// Transformation function: get the low 16 bits.
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return getI32Imm((unsigned short)N->getValue());
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}]>;
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def HI16 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned)N->getValue() >> 16);
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}]>;
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2005-09-08 17:33:10 +00:00
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2005-09-28 23:07:13 +00:00
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def HA16 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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signed int Val = N->getValue();
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return getI32Imm((Val - (signed short)Val) >> 16);
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}]>;
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2006-09-22 05:01:56 +00:00
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def MB : SDNodeXForm<imm, [{
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// Transformation function: get the start bit of a mask
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unsigned mb, me;
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(void)isRunOfOnes((unsigned)N->getValue(), mb, me);
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return getI32Imm(mb);
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}]>;
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2005-09-28 23:07:13 +00:00
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2006-09-22 05:01:56 +00:00
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def ME : SDNodeXForm<imm, [{
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// Transformation function: get the end bit of a mask
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unsigned mb, me;
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(void)isRunOfOnes((unsigned)N->getValue(), mb, me);
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return getI32Imm(me);
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}]>;
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def maskimm32 : PatLeaf<(imm), [{
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// maskImm predicate - True if immediate is a run of ones.
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unsigned mb, me;
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if (N->getValueType(0) == MVT::i32)
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return isRunOfOnes((unsigned)N->getValue(), mb, me);
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else
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return false;
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}]>;
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2005-09-28 23:07:13 +00:00
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2005-09-08 17:33:10 +00:00
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def immSExt16 : PatLeaf<(imm), [{
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// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
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// field. Used by instructions like 'addi'.
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2006-06-20 23:21:20 +00:00
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if (N->getValueType(0) == MVT::i32)
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return (int32_t)N->getValue() == (short)N->getValue();
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else
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return (int64_t)N->getValue() == (short)N->getValue();
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2005-09-08 17:33:10 +00:00
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}]>;
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2005-09-08 17:40:49 +00:00
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def immZExt16 : PatLeaf<(imm), [{
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// immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
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// field. Used by instructions like 'ori'.
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2006-06-20 23:21:20 +00:00
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return (uint64_t)N->getValue() == (unsigned short)N->getValue();
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2005-09-09 00:39:56 +00:00
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}], LO16>;
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Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
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// imm16Shifted* - These match immediates where the low 16-bits are zero. There
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// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
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// identical in 32-bit mode, but in 64-bit mode, they return true if the
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// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
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// clear).
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def imm16ShiftedZExt : PatLeaf<(imm), [{
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// imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
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// immediate are set. Used by instructions like 'xoris'.
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return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
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}], HI16>;
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def imm16ShiftedSExt : PatLeaf<(imm), [{
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// imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
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// immediate are set. Used by instructions like 'addis'. Identical to
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// imm16ShiftedZExt in 32-bit mode.
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2006-06-20 21:39:30 +00:00
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if (N->getValue() & 0xFFFF) return false;
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if (N->getValueType(0) == MVT::i32)
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return true;
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// For 64-bit, make sure it is sext right.
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return N->getValue() == (uint64_t)(int)N->getValue();
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2005-09-09 00:39:56 +00:00
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}], HI16>;
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2005-09-08 17:33:10 +00:00
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2006-03-25 06:12:06 +00:00
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2005-09-08 19:50:41 +00:00
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//===----------------------------------------------------------------------===//
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// PowerPC Flag Definitions.
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2005-04-19 04:32:54 +00:00
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class isPPC64 { bit PPC64 = 1; }
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2005-04-19 05:15:18 +00:00
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class isDOT {
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list<Register> Defs = [CR0];
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bit RC = 1;
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}
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2005-04-19 04:32:54 +00:00
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2006-11-08 02:13:12 +00:00
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class RegConstraint<string C> {
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string Constraints = C;
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}
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2005-09-08 19:50:41 +00:00
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//===----------------------------------------------------------------------===//
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// PowerPC Operand Definitions.
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2004-08-14 23:27:29 +00:00
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2006-03-25 06:12:06 +00:00
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def s5imm : Operand<i32> {
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let PrintMethod = "printS5ImmOperand";
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}
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2005-09-14 20:53:05 +00:00
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def u5imm : Operand<i32> {
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2004-08-21 05:56:39 +00:00
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let PrintMethod = "printU5ImmOperand";
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}
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2005-09-14 20:53:05 +00:00
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def u6imm : Operand<i32> {
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2004-08-30 02:28:06 +00:00
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let PrintMethod = "printU6ImmOperand";
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}
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2005-09-14 20:53:05 +00:00
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def s16imm : Operand<i32> {
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2004-09-04 05:00:00 +00:00
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let PrintMethod = "printS16ImmOperand";
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}
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2005-09-14 20:53:05 +00:00
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def u16imm : Operand<i32> {
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2004-08-15 05:20:16 +00:00
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let PrintMethod = "printU16ImmOperand";
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}
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2005-10-18 16:51:22 +00:00
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def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
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let PrintMethod = "printS16X4ImmOperand";
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}
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2005-12-04 18:42:54 +00:00
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def target : Operand<OtherVT> {
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2004-09-02 08:13:00 +00:00
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let PrintMethod = "printBranchOperand";
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}
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2006-06-16 21:01:35 +00:00
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def calltarget : Operand<iPTR> {
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2005-11-17 19:16:08 +00:00
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let PrintMethod = "printCallOperand";
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}
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2006-06-16 21:01:35 +00:00
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def aaddr : Operand<iPTR> {
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2005-11-16 00:48:01 +00:00
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let PrintMethod = "printAbsAddrOperand";
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}
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2006-06-16 21:01:35 +00:00
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def piclabel: Operand<iPTR> {
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2004-09-02 08:13:00 +00:00
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let PrintMethod = "printPICLabel";
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}
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2004-09-04 05:00:00 +00:00
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def symbolHi: Operand<i32> {
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let PrintMethod = "printSymbolHi";
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}
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def symbolLo: Operand<i32> {
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let PrintMethod = "printSymbolLo";
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}
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2005-07-20 22:42:00 +00:00
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def crbitm: Operand<i8> {
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let PrintMethod = "printcrbitm";
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}
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2005-12-19 23:25:09 +00:00
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// Address operands
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2006-06-16 21:01:35 +00:00
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def memri : Operand<iPTR> {
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2005-12-19 23:25:09 +00:00
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let PrintMethod = "printMemRegImm";
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2006-06-16 21:29:03 +00:00
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let MIOperandInfo = (ops i32imm, ptr_rc);
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2005-12-19 23:25:09 +00:00
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}
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2006-06-16 21:01:35 +00:00
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def memrr : Operand<iPTR> {
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2005-12-19 23:25:09 +00:00
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let PrintMethod = "printMemRegReg";
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2006-06-16 21:29:03 +00:00
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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2005-12-19 23:25:09 +00:00
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}
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2006-06-16 21:01:35 +00:00
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def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
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When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
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let PrintMethod = "printMemRegImmShifted";
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2006-06-16 21:29:03 +00:00
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let MIOperandInfo = (ops i32imm, ptr_rc);
|
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
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}
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2005-12-19 23:25:09 +00:00
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2006-11-04 05:42:48 +00:00
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// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
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2006-11-04 05:27:39 +00:00
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// that doesn't matter.
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2006-11-04 05:42:48 +00:00
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def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> {
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2006-11-04 05:27:39 +00:00
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let PrintMethod = "printPredicateOperand";
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}
|
2006-11-03 23:53:25 +00:00
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2006-01-12 02:05:36 +00:00
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// Define PowerPC specific addressing mode.
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2006-10-11 21:03:53 +00:00
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def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
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def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
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def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
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def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
|
2004-08-15 05:20:16 +00:00
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2005-12-14 22:07:12 +00:00
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Predicate Definitions.
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2005-12-20 20:08:53 +00:00
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def FPContractions : Predicate<"!NoExcessFPPrecision">;
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2005-09-08 19:50:41 +00:00
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Definitions.
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|
2004-06-21 16:55:25 +00:00
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// Pseudo-instructions:
|
2005-09-08 19:50:41 +00:00
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|
2006-03-12 09:13:49 +00:00
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|
let hasCtrlDep = 1 in {
|
2005-12-04 19:01:59 +00:00
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|
def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
|
2006-09-27 02:55:21 +00:00
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"${:comment} ADJCALLSTACKDOWN",
|
2006-10-12 17:56:34 +00:00
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[(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
|
2005-12-04 19:01:59 +00:00
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|
def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
|
2006-09-27 02:55:21 +00:00
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"${:comment} ADJCALLSTACKUP",
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2006-10-12 17:56:34 +00:00
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[(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
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|
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|
|
def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
|
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|
"UPDATE_VRSAVE $rD, $rS", []>;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2006-09-27 02:55:21 +00:00
|
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|
def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD",
|
2005-10-25 21:03:41 +00:00
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[(set GPRC:$rD, (undef))]>;
|
2006-09-27 02:55:21 +00:00
|
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|
def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD",
|
2005-10-25 21:03:41 +00:00
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[(set F8RC:$rD, (undef))]>;
|
2006-09-27 02:55:21 +00:00
|
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|
def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD",
|
2005-10-25 21:03:41 +00:00
|
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|
[(set F4RC:$rD, (undef))]>;
|
2005-02-15 20:26:49 +00:00
|
|
|
|
2005-08-26 21:23:58 +00:00
|
|
|
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
|
|
|
|
// scheduler into a branch sequence.
|
2006-03-12 09:13:49 +00:00
|
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|
let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
|
|
|
|
PPC970_Single = 1 in {
|
2006-06-27 00:04:13 +00:00
|
|
|
def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
|
2006-09-27 02:55:21 +00:00
|
|
|
i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
|
|
|
|
[]>;
|
2006-06-27 00:04:13 +00:00
|
|
|
def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
|
2006-09-27 02:55:21 +00:00
|
|
|
i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
|
|
|
|
[]>;
|
2005-10-01 01:35:02 +00:00
|
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|
def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
|
2006-09-27 02:55:21 +00:00
|
|
|
i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
|
|
|
|
[]>;
|
2005-10-01 01:35:02 +00:00
|
|
|
def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
|
2006-09-27 02:55:21 +00:00
|
|
|
i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
|
|
|
|
[]>;
|
2006-04-08 22:45:08 +00:00
|
|
|
def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
|
2006-09-27 02:55:21 +00:00
|
|
|
i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
|
|
|
|
[]>;
|
2005-08-26 21:23:58 +00:00
|
|
|
}
|
|
|
|
|
2006-10-13 19:10:34 +00:00
|
|
|
let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
|
2006-01-09 18:28:21 +00:00
|
|
|
let isReturn = 1 in
|
2006-11-04 05:42:48 +00:00
|
|
|
def BLR : XLForm_2_br<19, 16, 0,
|
|
|
|
(ops pred:$p),
|
|
|
|
"b${p:cc}lr ${p:reg}", BrB,
|
|
|
|
[(retflag)]>;
|
2005-12-20 00:26:01 +00:00
|
|
|
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
|
2005-09-08 19:50:41 +00:00
|
|
|
}
|
|
|
|
|
2006-11-04 05:27:39 +00:00
|
|
|
|
2005-02-15 20:26:49 +00:00
|
|
|
let Defs = [LR] in
|
2006-03-12 09:13:49 +00:00
|
|
|
def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
|
|
|
|
PPC970_Unit_BRU;
|
2004-06-21 16:55:25 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
|
|
|
|
noResults = 1, PPC970_Unit = 7 in {
|
2006-10-13 19:10:34 +00:00
|
|
|
// COND_BRANCH is formed before branch selection, it is turned into Bcc below.
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
|
2006-09-27 02:55:21 +00:00
|
|
|
"${:comment} COND_BRANCH $crS, $opc, $dst",
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
|
2006-10-13 19:10:34 +00:00
|
|
|
let isBarrier = 1 in {
|
2005-12-04 18:42:54 +00:00
|
|
|
def B : IForm<18, 0, 0, (ops target:$dst),
|
|
|
|
"b $dst", BrB,
|
|
|
|
[(br bb:$dst)]>;
|
2006-10-13 19:10:34 +00:00
|
|
|
}
|
2004-11-22 23:07:01 +00:00
|
|
|
|
2005-08-26 04:11:42 +00:00
|
|
|
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
|
2005-10-19 19:51:16 +00:00
|
|
|
"blt $crS, $block", BrB>;
|
2005-08-26 04:11:42 +00:00
|
|
|
def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
|
2005-10-19 19:51:16 +00:00
|
|
|
"ble $crS, $block", BrB>;
|
2005-08-26 04:11:42 +00:00
|
|
|
def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
|
2005-10-19 19:51:16 +00:00
|
|
|
"beq $crS, $block", BrB>;
|
2005-08-26 04:11:42 +00:00
|
|
|
def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
|
2005-10-19 19:51:16 +00:00
|
|
|
"bge $crS, $block", BrB>;
|
2005-08-26 04:11:42 +00:00
|
|
|
def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
|
2005-10-19 19:51:16 +00:00
|
|
|
"bgt $crS, $block", BrB>;
|
2005-08-26 04:11:42 +00:00
|
|
|
def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
|
2005-10-19 19:51:16 +00:00
|
|
|
"bne $crS, $block", BrB>;
|
2005-10-28 20:32:44 +00:00
|
|
|
def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
|
|
|
|
"bun $crS, $block", BrB>;
|
|
|
|
def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
|
|
|
|
"bnu $crS, $block", BrB>;
|
2004-06-28 18:23:35 +00:00
|
|
|
}
|
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let isCall = 1, noResults = 1, PPC970_Unit = 7,
|
2004-06-29 23:37:36 +00:00
|
|
|
// All calls clobber the non-callee saved registers...
|
2004-06-30 22:00:45 +00:00
|
|
|
Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
|
|
|
|
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
|
2006-03-16 22:35:59 +00:00
|
|
|
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
|
2005-08-22 22:32:13 +00:00
|
|
|
LR,CTR,
|
2004-06-30 22:00:45 +00:00
|
|
|
CR0,CR1,CR5,CR6,CR7] in {
|
|
|
|
// Convenient aliases for call instructions
|
2006-06-10 01:14:28 +00:00
|
|
|
def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
|
2006-05-17 19:00:46 +00:00
|
|
|
"bl $func", BrB, []>; // See Pat patterns below.
|
2006-06-10 01:14:28 +00:00
|
|
|
def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
|
2006-06-27 18:36:44 +00:00
|
|
|
"bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
|
2006-06-10 01:14:28 +00:00
|
|
|
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
|
2006-05-17 19:00:46 +00:00
|
|
|
[(PPCbctrl)]>;
|
2004-06-29 23:37:36 +00:00
|
|
|
}
|
|
|
|
|
2006-06-06 21:29:23 +00:00
|
|
|
// DCB* instructions.
|
2006-10-24 01:08:42 +00:00
|
|
|
def DCBA : DCB_Form<758, 0, (ops memrr:$dst),
|
|
|
|
"dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Single;
|
|
|
|
def DCBF : DCB_Form<86, 0, (ops memrr:$dst),
|
|
|
|
"dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Single;
|
|
|
|
def DCBI : DCB_Form<470, 0, (ops memrr:$dst),
|
|
|
|
"dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Single;
|
|
|
|
def DCBST : DCB_Form<54, 0, (ops memrr:$dst),
|
|
|
|
"dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Single;
|
|
|
|
def DCBT : DCB_Form<278, 0, (ops memrr:$dst),
|
|
|
|
"dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Single;
|
|
|
|
def DCBTST : DCB_Form<246, 0, (ops memrr:$dst),
|
|
|
|
"dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Single;
|
|
|
|
def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
|
|
|
|
"dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Single;
|
|
|
|
def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
|
|
|
|
"dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Single;
|
2006-06-06 21:29:23 +00:00
|
|
|
|
2004-08-30 02:28:06 +00:00
|
|
|
// D-Form instructions. Most instructions that perform an operation on a
|
|
|
|
// register and an immediate are of this type.
|
|
|
|
//
|
2006-03-12 09:13:49 +00:00
|
|
|
let isLoad = 1, PPC970_Unit = 2 in {
|
2005-12-19 23:25:09 +00:00
|
|
|
def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
|
|
|
|
"lbz $rD, $src", LdStGeneral,
|
2006-10-09 20:57:25 +00:00
|
|
|
[(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
|
2005-12-19 23:25:09 +00:00
|
|
|
def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
|
|
|
|
"lha $rD, $src", LdStLHA,
|
2006-10-09 20:57:25 +00:00
|
|
|
[(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
|
2006-03-13 05:15:10 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2005-12-19 23:25:09 +00:00
|
|
|
def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
|
|
|
|
"lhz $rD, $src", LdStGeneral,
|
2006-10-09 20:57:25 +00:00
|
|
|
[(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
|
2005-12-19 23:25:09 +00:00
|
|
|
def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
|
|
|
|
"lwz $rD, $src", LdStGeneral,
|
|
|
|
[(set GPRC:$rD, (load iaddr:$src))]>;
|
2006-11-08 02:13:12 +00:00
|
|
|
|
2006-11-10 17:51:02 +00:00
|
|
|
def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src),
|
2006-11-10 02:08:47 +00:00
|
|
|
"lfs $rD, $src", LdStLFDU,
|
|
|
|
[(set F4RC:$rD, (load iaddr:$src))]>;
|
2006-11-10 17:51:02 +00:00
|
|
|
def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
|
2006-11-10 02:08:47 +00:00
|
|
|
"lfd $rD, $src", LdStLFD,
|
|
|
|
[(set F8RC:$rD, (load iaddr:$src))]>;
|
|
|
|
|
|
|
|
// FIXME: PTRRC for Pointer regs for ppc64.
|
|
|
|
|
|
|
|
// 'Update' load forms.
|
|
|
|
def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp,
|
|
|
|
ptr_rc:$rA),
|
|
|
|
"lbzu $rD, $disp($rA)", LdStGeneral,
|
|
|
|
[]>, RegConstraint<"$rA = $rA_result">;
|
|
|
|
|
|
|
|
def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp,
|
|
|
|
ptr_rc:$rA),
|
|
|
|
"lhau $rD, $disp($rA)", LdStGeneral,
|
|
|
|
[]>, RegConstraint<"$rA = $rA_result">;
|
|
|
|
|
|
|
|
def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp,
|
|
|
|
ptr_rc:$rA),
|
|
|
|
"lhzu $rD, $disp($rA)", LdStGeneral,
|
|
|
|
[]>, RegConstraint<"$rA = $rA_result">;
|
|
|
|
|
|
|
|
def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp,
|
|
|
|
ptr_rc:$rA),
|
2005-12-09 23:54:18 +00:00
|
|
|
"lwzu $rD, $disp($rA)", LdStGeneral,
|
2006-11-08 02:13:12 +00:00
|
|
|
[]>, RegConstraint<"$rA = $rA_result">;
|
2006-11-10 02:08:47 +00:00
|
|
|
|
2006-11-10 17:51:02 +00:00
|
|
|
def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
|
2006-11-10 02:08:47 +00:00
|
|
|
ptr_rc:$rA),
|
|
|
|
"lfs $rD, $disp($rA)", LdStLFDU,
|
|
|
|
[]>, RegConstraint<"$rA = $rA_result">;
|
2006-11-10 17:51:02 +00:00
|
|
|
def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
|
2006-11-10 02:08:47 +00:00
|
|
|
ptr_rc:$rA),
|
|
|
|
"lfd $rD, $disp($rA)", LdStLFD,
|
|
|
|
[]>, RegConstraint<"$rA = $rA_result">;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2006-11-08 02:13:12 +00:00
|
|
|
|
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2005-04-19 04:59:28 +00:00
|
|
|
def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"addi $rD, $rA, $imm", IntGeneral,
|
2005-09-08 17:33:10 +00:00
|
|
|
[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"addic $rD, $rA, $imm", IntGeneral,
|
2006-03-13 05:15:10 +00:00
|
|
|
[(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
|
|
|
|
PPC970_DGroup_Cracked;
|
2005-04-19 04:59:28 +00:00
|
|
|
def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"addic. $rD, $rA, $imm", IntGeneral,
|
2005-09-08 17:33:10 +00:00
|
|
|
[]>;
|
2005-07-21 20:44:43 +00:00
|
|
|
def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"addis $rD, $rA, $imm", IntGeneral,
|
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
|
|
|
[(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
|
2005-10-19 19:51:16 +00:00
|
|
|
"la $rD, $sym($rA)", IntGeneral,
|
2005-11-17 17:52:01 +00:00
|
|
|
[(set GPRC:$rD, (add GPRC:$rA,
|
|
|
|
(PPClo tglobaladdr:$sym, 0)))]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"mulli $rD, $rA, $imm", IntMulLI,
|
2005-09-08 17:33:10 +00:00
|
|
|
[(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"subfic $rD, $rA, $imm", IntGeneral,
|
2006-03-17 22:41:37 +00:00
|
|
|
[(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
|
2005-11-17 07:04:43 +00:00
|
|
|
def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"li $rD, $imm", IntGeneral,
|
2005-09-08 17:33:10 +00:00
|
|
|
[(set GPRC:$rD, immSExt16:$imm)]>;
|
2005-07-21 20:44:43 +00:00
|
|
|
def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"lis $rD, $imm", IntGeneral,
|
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
|
|
|
[(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
|
|
|
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
|
2005-12-19 23:25:09 +00:00
|
|
|
def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
|
|
|
|
"stb $rS, $src", LdStGeneral,
|
2006-10-13 21:14:26 +00:00
|
|
|
[(truncstorei8 GPRC:$rS, iaddr:$src)]>;
|
2005-12-19 23:25:09 +00:00
|
|
|
def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
|
|
|
|
"sth $rS, $src", LdStGeneral,
|
2006-10-13 21:14:26 +00:00
|
|
|
[(truncstorei16 GPRC:$rS, iaddr:$src)]>;
|
2005-12-19 23:25:09 +00:00
|
|
|
def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
|
|
|
|
"stw $rS, $src", LdStGeneral,
|
|
|
|
[(store GPRC:$rS, iaddr:$src)]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
2005-12-09 23:54:18 +00:00
|
|
|
"stwu $rS, $disp($rA)", LdStGeneral,
|
|
|
|
[]>;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2005-04-19 04:59:28 +00:00
|
|
|
def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
2005-10-19 19:51:16 +00:00
|
|
|
"andi. $dst, $src1, $src2", IntGeneral,
|
2006-02-12 09:09:52 +00:00
|
|
|
[(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
|
|
|
|
isDOT;
|
2005-04-19 04:59:28 +00:00
|
|
|
def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
2005-10-19 19:51:16 +00:00
|
|
|
"andis. $dst, $src1, $src2", IntGeneral,
|
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
|
|
|
[(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
|
2006-02-12 09:09:52 +00:00
|
|
|
isDOT;
|
2005-04-19 04:59:28 +00:00
|
|
|
def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
2005-10-19 19:51:16 +00:00
|
|
|
"ori $dst, $src1, $src2", IntGeneral,
|
2005-09-14 18:18:39 +00:00
|
|
|
[(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
2005-10-19 19:51:16 +00:00
|
|
|
"oris $dst, $src1, $src2", IntGeneral,
|
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
|
|
|
[(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
2005-10-19 19:51:16 +00:00
|
|
|
"xori $dst, $src1, $src2", IntGeneral,
|
2005-09-14 18:18:39 +00:00
|
|
|
[(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
2005-10-19 19:51:16 +00:00
|
|
|
"xoris $dst, $src1, $src2", IntGeneral,
|
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
|
|
|
[(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
|
2005-12-09 23:54:18 +00:00
|
|
|
def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
|
|
|
|
[]>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
|
2005-10-19 19:51:16 +00:00
|
|
|
"cmpwi $crD, $rA, $imm", IntCompare>;
|
2005-04-19 04:59:28 +00:00
|
|
|
def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
|
2005-10-19 19:51:16 +00:00
|
|
|
"cmplwi $dst, $src1, $src2", IntCompare>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
|
|
|
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
|
2006-11-10 17:51:02 +00:00
|
|
|
def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
|
2005-12-19 23:25:09 +00:00
|
|
|
"stfs $rS, $dst", LdStUX,
|
|
|
|
[(store F4RC:$rS, iaddr:$dst)]>;
|
2006-11-10 17:51:02 +00:00
|
|
|
def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
|
2005-12-19 23:25:09 +00:00
|
|
|
"stfd $rS, $dst", LdStUX,
|
|
|
|
[(store F8RC:$rS, iaddr:$dst)]>;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2004-09-04 05:00:00 +00:00
|
|
|
|
2004-08-30 02:28:06 +00:00
|
|
|
// X-Form instructions. Most instructions that perform an operation on a
|
|
|
|
// register and another register are of this type.
|
|
|
|
//
|
2006-03-12 09:13:49 +00:00
|
|
|
let isLoad = 1, PPC970_Unit = 2 in {
|
2005-12-19 23:25:09 +00:00
|
|
|
def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
|
|
|
|
"lbzx $rD, $src", LdStGeneral,
|
2006-10-09 20:57:25 +00:00
|
|
|
[(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
|
2005-12-19 23:25:09 +00:00
|
|
|
def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
|
|
|
|
"lhax $rD, $src", LdStLHA,
|
2006-10-09 20:57:25 +00:00
|
|
|
[(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
|
2006-03-13 05:15:10 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2005-12-19 23:25:09 +00:00
|
|
|
def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
|
|
|
|
"lhzx $rD, $src", LdStGeneral,
|
2006-10-09 20:57:25 +00:00
|
|
|
[(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
|
2005-12-19 23:25:09 +00:00
|
|
|
def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
|
|
|
|
"lwzx $rD, $src", LdStGeneral,
|
|
|
|
[(set GPRC:$rD, (load xaddr:$src))]>;
|
2006-07-10 20:56:58 +00:00
|
|
|
|
|
|
|
|
|
|
|
def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
|
|
|
|
"lhbrx $rD, $src", LdStGeneral,
|
2006-07-19 17:15:36 +00:00
|
|
|
[(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
|
2006-07-10 20:56:58 +00:00
|
|
|
def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
|
|
|
|
"lwbrx $rD, $src", LdStGeneral,
|
2006-07-19 17:15:36 +00:00
|
|
|
[(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
|
2006-07-10 20:56:58 +00:00
|
|
|
|
2005-12-09 23:54:18 +00:00
|
|
|
}
|
2006-03-25 07:51:43 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2005-09-03 00:21:51 +00:00
|
|
|
def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"nand $rA, $rS, $rB", IntGeneral,
|
2005-09-03 00:21:51 +00:00
|
|
|
[(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"and $rA, $rS, $rB", IntGeneral,
|
2005-09-14 18:18:39 +00:00
|
|
|
[(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"andc $rA, $rS, $rB", IntGeneral,
|
2005-09-03 00:21:51 +00:00
|
|
|
[(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
|
2006-06-20 23:18:58 +00:00
|
|
|
def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"or $rA, $rS, $rB", IntGeneral,
|
2005-09-14 18:18:39 +00:00
|
|
|
[(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
|
2005-09-03 00:21:51 +00:00
|
|
|
def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"nor $rA, $rS, $rB", IntGeneral,
|
2005-09-03 00:21:51 +00:00
|
|
|
[(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"orc $rA, $rS, $rB", IntGeneral,
|
2005-09-03 00:21:51 +00:00
|
|
|
[(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
|
|
|
|
def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"eqv $rA, $rS, $rB", IntGeneral,
|
2005-09-14 18:18:39 +00:00
|
|
|
[(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
|
2005-09-03 00:21:51 +00:00
|
|
|
def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"xor $rA, $rS, $rB", IntGeneral,
|
2006-06-20 00:39:56 +00:00
|
|
|
[(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"slw $rA, $rS, $rB", IntGeneral,
|
2005-12-06 02:10:38 +00:00
|
|
|
[(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"srw $rA, $rS, $rB", IntGeneral,
|
2005-12-06 02:10:38 +00:00
|
|
|
[(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"sraw $rA, $rS, $rB", IntShift,
|
2005-12-06 02:10:38 +00:00
|
|
|
[(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
|
|
|
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
|
2005-12-19 23:25:09 +00:00
|
|
|
def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
|
|
|
|
"stbx $rS, $dst", LdStGeneral,
|
2006-10-13 21:14:26 +00:00
|
|
|
[(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
|
2006-03-13 05:15:10 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2005-12-19 23:25:09 +00:00
|
|
|
def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
|
|
|
|
"sthx $rS, $dst", LdStGeneral,
|
2006-10-13 21:14:26 +00:00
|
|
|
[(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
|
2006-03-13 05:15:10 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2005-12-19 23:25:09 +00:00
|
|
|
def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
|
|
|
|
"stwx $rS, $dst", LdStGeneral,
|
2006-03-13 05:15:10 +00:00
|
|
|
[(store GPRC:$rS, xaddr:$dst)]>,
|
|
|
|
PPC970_DGroup_Cracked;
|
2005-04-19 04:51:30 +00:00
|
|
|
def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
2005-12-09 23:54:18 +00:00
|
|
|
"stwux $rS, $rA, $rB", LdStGeneral,
|
|
|
|
[]>;
|
2006-07-10 20:56:58 +00:00
|
|
|
def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst),
|
|
|
|
"sthbrx $rS, $dst", LdStGeneral,
|
2006-07-19 17:15:36 +00:00
|
|
|
[(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
|
2006-07-10 20:56:58 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
|
|
|
def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst),
|
|
|
|
"stwbrx $rS, $dst", LdStGeneral,
|
2006-07-19 17:15:36 +00:00
|
|
|
[(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
|
2006-07-10 20:56:58 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2005-04-19 05:15:18 +00:00
|
|
|
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
|
2005-10-19 19:51:16 +00:00
|
|
|
"srawi $rA, $rS, $SH", IntShift,
|
2005-12-05 02:34:05 +00:00
|
|
|
[(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
|
2005-10-19 19:51:16 +00:00
|
|
|
"cntlzw $rA, $rS", IntGeneral,
|
2005-09-02 22:35:53 +00:00
|
|
|
[(set GPRC:$rA, (ctlz GPRC:$rS))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
|
2005-10-19 19:51:16 +00:00
|
|
|
"extsb $rA, $rS", IntGeneral,
|
2005-09-02 22:35:53 +00:00
|
|
|
[(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
|
2005-04-19 05:15:18 +00:00
|
|
|
def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
|
2005-10-19 19:51:16 +00:00
|
|
|
"extsh $rA, $rS", IntGeneral,
|
2005-09-02 22:35:53 +00:00
|
|
|
[(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
|
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
|
|
|
|
2005-04-19 04:51:30 +00:00
|
|
|
def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"cmpw $crD, $rA, $rB", IntCompare>;
|
2005-04-19 04:51:30 +00:00
|
|
|
def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"cmplw $crD, $rA, $rB", IntCompare>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
|
|
|
let PPC970_Unit = 3 in { // FPU Operations.
|
2005-10-01 01:35:02 +00:00
|
|
|
//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
|
2005-10-19 19:51:16 +00:00
|
|
|
// "fcmpo $crD, $fA, $fB", FPCompare>;
|
2005-10-01 01:35:02 +00:00
|
|
|
def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fcmpu $crD, $fA, $fB", FPCompare>;
|
2005-10-01 01:35:02 +00:00
|
|
|
def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fcmpu $crD, $fA, $fB", FPCompare>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
|
|
|
let isLoad = 1, PPC970_Unit = 2 in {
|
2005-12-19 23:25:09 +00:00
|
|
|
def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
|
|
|
|
"lfsx $frD, $src", LdStLFDU,
|
|
|
|
[(set F4RC:$frD, (load xaddr:$src))]>;
|
|
|
|
def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
|
|
|
|
"lfdx $frD, $src", LdStLFDU,
|
|
|
|
[(set F8RC:$frD, (load xaddr:$src))]>;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 3 in { // FPU Operations.
|
2005-10-01 01:35:02 +00:00
|
|
|
def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fctiwz $frD, $frB", FPGeneral,
|
2005-10-25 20:41:46 +00:00
|
|
|
[(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
|
2005-10-01 01:35:02 +00:00
|
|
|
def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"frsp $frD, $frB", FPGeneral,
|
2005-10-14 04:55:50 +00:00
|
|
|
[(set F4RC:$frD, (fround F8RC:$frB))]>;
|
2005-10-01 01:35:02 +00:00
|
|
|
def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fsqrt $frD, $frB", FPSqrt,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
|
|
|
|
def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fsqrts $frD, $frB", FPSqrt,
|
2005-10-15 21:44:15 +00:00
|
|
|
[(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2005-10-01 01:35:02 +00:00
|
|
|
|
|
|
|
/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
|
2006-03-12 09:13:49 +00:00
|
|
|
///
|
|
|
|
/// Note that these are defined as pseudo-ops on the PPC970 because they are
|
2006-03-24 07:12:19 +00:00
|
|
|
/// often coalesced away and we don't want the dispatch group builder to think
|
2006-03-12 09:13:49 +00:00
|
|
|
/// that they will fill slots (which could cause the load of a LSU reject to
|
|
|
|
/// sneak into a d-group with a store).
|
2005-10-01 01:35:02 +00:00
|
|
|
def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmr $frD, $frB", FPGeneral,
|
2006-03-12 09:13:49 +00:00
|
|
|
[]>, // (set F4RC:$frD, F4RC:$frB)
|
|
|
|
PPC970_Unit_Pseudo;
|
2005-10-01 01:35:02 +00:00
|
|
|
def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmr $frD, $frB", FPGeneral,
|
2006-03-12 09:13:49 +00:00
|
|
|
[]>, // (set F8RC:$frD, F8RC:$frB)
|
|
|
|
PPC970_Unit_Pseudo;
|
2005-10-01 01:35:02 +00:00
|
|
|
def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmr $frD, $frB", FPGeneral,
|
2006-03-12 09:13:49 +00:00
|
|
|
[(set F8RC:$frD, (fextend F4RC:$frB))]>,
|
|
|
|
PPC970_Unit_Pseudo;
|
2005-10-01 01:35:02 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 3 in { // FPU Operations.
|
2005-10-01 01:35:02 +00:00
|
|
|
// These are artificially split into two different forms, for 4/8 byte FP.
|
|
|
|
def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fabs $frD, $frB", FPGeneral,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F4RC:$frD, (fabs F4RC:$frB))]>;
|
|
|
|
def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fabs $frD, $frB", FPGeneral,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$frD, (fabs F8RC:$frB))]>;
|
|
|
|
def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fnabs $frD, $frB", FPGeneral,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
|
|
|
|
def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fnabs $frD, $frB", FPGeneral,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
|
|
|
|
def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fneg $frD, $frB", FPGeneral,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F4RC:$frD, (fneg F4RC:$frB))]>;
|
|
|
|
def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fneg $frD, $frB", FPGeneral,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$frD, (fneg F8RC:$frB))]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2005-10-01 01:35:02 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
|
2006-03-01 05:50:56 +00:00
|
|
|
def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
|
2005-12-19 23:25:09 +00:00
|
|
|
"stfiwx $frS, $dst", LdStUX,
|
2006-03-01 05:50:56 +00:00
|
|
|
[(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
|
2005-12-19 23:25:09 +00:00
|
|
|
def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
|
|
|
|
"stfsx $frS, $dst", LdStUX,
|
|
|
|
[(store F4RC:$frS, xaddr:$dst)]>;
|
|
|
|
def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
|
|
|
|
"stfdx $frS, $dst", LdStUX,
|
|
|
|
[(store F8RC:$frS, xaddr:$dst)]>;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2004-08-29 22:45:13 +00:00
|
|
|
|
2004-08-30 02:28:06 +00:00
|
|
|
// XL-Form instructions. condition register logical ops.
|
|
|
|
//
|
2005-04-19 04:51:30 +00:00
|
|
|
def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
|
2006-03-12 09:13:49 +00:00
|
|
|
"mcrf $BF, $BFA", BrMCR>,
|
|
|
|
PPC970_DGroup_First, PPC970_Unit_CRU;
|
2004-08-30 02:28:06 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
// XFX-Form instructions. Instructions that deal with SPRs.
|
2004-08-30 02:28:06 +00:00
|
|
|
//
|
2006-03-12 09:13:49 +00:00
|
|
|
def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
|
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
2006-05-17 19:00:46 +00:00
|
|
|
let Pattern = [(PPCmtctr GPRC:$rS)] in {
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
|
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
2006-05-17 19:00:46 +00:00
|
|
|
}
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
|
|
|
|
def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
|
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
2006-04-22 18:53:45 +00:00
|
|
|
def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
|
2006-03-12 09:13:49 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
|
|
|
|
// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
|
|
|
|
// a GPR on the PPC970. As such, copies in and out have the same performance
|
|
|
|
// characteristics as an OR instruction.
|
|
|
|
def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
|
|
|
|
"mtspr 256, $rS", IntGeneral>,
|
2006-03-15 05:25:05 +00:00
|
|
|
PPC970_DGroup_Single, PPC970_Unit_FXU;
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
|
|
|
|
"mfspr $rT, 256", IntGeneral>,
|
2006-03-15 05:25:05 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
|
2005-08-26 22:05:54 +00:00
|
|
|
def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
|
2006-03-12 09:13:49 +00:00
|
|
|
"mtcrf $FXM, $rS", BrMCRX>,
|
|
|
|
PPC970_MicroCode, PPC970_Unit_CRU;
|
2006-03-26 10:06:40 +00:00
|
|
|
def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
|
|
|
|
PPC970_MicroCode, PPC970_Unit_CRU;
|
2005-11-29 22:42:50 +00:00
|
|
|
def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
|
2006-03-12 09:13:49 +00:00
|
|
|
"mfcr $rT, $FXM", SprMFCR>,
|
|
|
|
PPC970_DGroup_First, PPC970_Unit_CRU;
|
2004-08-30 02:28:06 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2004-08-30 02:28:06 +00:00
|
|
|
|
|
|
|
// XO-Form instructions. Arithmetic instructions that can set overflow bit
|
|
|
|
//
|
2005-10-18 00:28:58 +00:00
|
|
|
def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"add $rT, $rA, $rB", IntGeneral,
|
2005-09-02 21:18:00 +00:00
|
|
|
[(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"addc $rT, $rA, $rB", IntGeneral,
|
2006-03-13 05:15:10 +00:00
|
|
|
[(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
|
|
|
|
PPC970_DGroup_Cracked;
|
2005-04-19 05:21:30 +00:00
|
|
|
def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"adde $rT, $rA, $rB", IntGeneral,
|
2006-02-17 05:43:56 +00:00
|
|
|
[(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"divw $rT, $rA, $rB", IntDivW,
|
2006-03-12 09:13:49 +00:00
|
|
|
[(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
|
2006-03-13 05:15:10 +00:00
|
|
|
PPC970_DGroup_First, PPC970_DGroup_Cracked;
|
2005-04-19 05:21:30 +00:00
|
|
|
def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"divwu $rT, $rA, $rB", IntDivW,
|
2006-03-12 09:13:49 +00:00
|
|
|
[(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
|
2006-03-13 05:15:10 +00:00
|
|
|
PPC970_DGroup_First, PPC970_DGroup_Cracked;
|
2005-04-19 05:21:30 +00:00
|
|
|
def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"mulhw $rT, $rA, $rB", IntMulHW,
|
2005-09-02 21:18:00 +00:00
|
|
|
[(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"mulhwu $rT, $rA, $rB", IntMulHWU,
|
2005-09-02 21:18:00 +00:00
|
|
|
[(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"mullw $rT, $rA, $rB", IntMulHW,
|
2005-09-02 21:18:00 +00:00
|
|
|
[(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"subf $rT, $rA, $rB", IntGeneral,
|
2005-09-02 21:18:00 +00:00
|
|
|
[(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"subfc $rT, $rA, $rB", IntGeneral,
|
2006-03-13 05:15:10 +00:00
|
|
|
[(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
|
|
|
|
PPC970_DGroup_Cracked;
|
2005-04-19 05:21:30 +00:00
|
|
|
def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"subfe $rT, $rA, $rB", IntGeneral,
|
2006-02-17 05:43:56 +00:00
|
|
|
[(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
|
2005-10-19 19:51:16 +00:00
|
|
|
"addme $rT, $rA", IntGeneral,
|
2006-02-17 05:43:56 +00:00
|
|
|
[(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
|
2005-10-19 19:51:16 +00:00
|
|
|
"addze $rT, $rA", IntGeneral,
|
2006-02-17 05:43:56 +00:00
|
|
|
[(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
|
2005-10-19 19:51:16 +00:00
|
|
|
"neg $rT, $rA", IntGeneral,
|
2005-09-08 17:01:54 +00:00
|
|
|
[(set GPRC:$rT, (ineg GPRC:$rA))]>;
|
2006-02-17 05:43:56 +00:00
|
|
|
def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
|
|
|
|
"subfme $rT, $rA", IntGeneral,
|
|
|
|
[(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
|
2005-10-19 19:51:16 +00:00
|
|
|
"subfze $rT, $rA", IntGeneral,
|
2006-02-17 05:43:56 +00:00
|
|
|
[(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2004-08-30 02:28:06 +00:00
|
|
|
|
|
|
|
// A-Form instructions. Most of the instructions executed in the FPU are of
|
|
|
|
// this type.
|
|
|
|
//
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 3 in { // FPU Operations.
|
2005-04-19 05:21:30 +00:00
|
|
|
def FMADD : AForm_1<63, 29,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
|
2005-12-14 22:07:12 +00:00
|
|
|
F8RC:$FRB))]>,
|
|
|
|
Requires<[FPContractions]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FMADDS : AForm_1<59, 29,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
|
2005-10-02 07:46:28 +00:00
|
|
|
[(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
|
2005-12-14 22:07:12 +00:00
|
|
|
F4RC:$FRB))]>,
|
|
|
|
Requires<[FPContractions]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FMSUB : AForm_1<63, 28,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
|
2005-12-14 22:07:12 +00:00
|
|
|
F8RC:$FRB))]>,
|
|
|
|
Requires<[FPContractions]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FMSUBS : AForm_1<59, 28,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
|
2005-10-02 07:46:28 +00:00
|
|
|
[(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
|
2005-12-14 22:07:12 +00:00
|
|
|
F4RC:$FRB))]>,
|
|
|
|
Requires<[FPContractions]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FNMADD : AForm_1<63, 31,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
|
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:54:33 +00:00
|
|
|
F8RC:$FRB)))]>,
|
|
|
|
Requires<[FPContractions]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FNMADDS : AForm_1<59, 31,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
|
2005-10-02 07:46:28 +00:00
|
|
|
[(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
|
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:54:33 +00:00
|
|
|
F4RC:$FRB)))]>,
|
|
|
|
Requires<[FPContractions]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FNMSUB : AForm_1<63, 30,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
|
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:54:33 +00:00
|
|
|
F8RC:$FRB)))]>,
|
|
|
|
Requires<[FPContractions]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FNMSUBS : AForm_1<59, 30,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
|
2005-10-02 07:46:28 +00:00
|
|
|
[(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
|
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:54:33 +00:00
|
|
|
F4RC:$FRB)))]>,
|
|
|
|
Requires<[FPContractions]>;
|
2005-10-02 07:07:49 +00:00
|
|
|
// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
|
|
|
|
// having 4 of these, force the comparison to always be an 8-byte double (code
|
|
|
|
// should use an FMRSD if the input comparison value really wants to be a float)
|
2005-10-02 06:58:23 +00:00
|
|
|
// and 4/8 byte forms for the result and operand type..
|
2005-10-02 07:07:49 +00:00
|
|
|
def FSELD : AForm_1<63, 23,
|
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
|
2005-10-25 20:55:47 +00:00
|
|
|
[(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
|
2005-10-02 07:07:49 +00:00
|
|
|
def FSELS : AForm_1<63, 23,
|
2005-10-02 06:58:23 +00:00
|
|
|
(ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
|
2005-10-25 20:55:47 +00:00
|
|
|
[(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FADD : AForm_2<63, 21,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fadd $FRT, $FRA, $FRB", FPGeneral,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FADDS : AForm_2<59, 21,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fadds $FRT, $FRA, $FRB", FPGeneral,
|
2005-10-02 07:46:28 +00:00
|
|
|
[(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FDIV : AForm_2<63, 18,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fdiv $FRT, $FRA, $FRB", FPDivD,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FDIVS : AForm_2<59, 18,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fdivs $FRT, $FRA, $FRB", FPDivS,
|
2005-10-02 07:46:28 +00:00
|
|
|
[(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FMUL : AForm_3<63, 25,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmul $FRT, $FRA, $FRB", FPFused,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FMULS : AForm_3<59, 25,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fmuls $FRT, $FRA, $FRB", FPGeneral,
|
2005-10-02 07:46:28 +00:00
|
|
|
[(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FSUB : AForm_2<63, 20,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fsub $FRT, $FRA, $FRB", FPGeneral,
|
2005-10-01 01:35:02 +00:00
|
|
|
[(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def FSUBS : AForm_2<59, 20,
|
2005-10-01 01:35:02 +00:00
|
|
|
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
|
2005-10-19 19:51:16 +00:00
|
|
|
"fsubs $FRT, $FRA, $FRB", FPGeneral,
|
2005-10-02 07:46:28 +00:00
|
|
|
[(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2004-08-30 02:28:06 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2004-08-31 02:28:08 +00:00
|
|
|
// M-Form instructions. rotate and mask instructions.
|
|
|
|
//
|
2005-09-09 18:17:41 +00:00
|
|
|
let isTwoAddress = 1, isCommutable = 1 in {
|
|
|
|
// RLWIMI can be commuted if the rotate amount is zero.
|
2005-04-19 05:21:30 +00:00
|
|
|
def RLWIMI : MForm_2<20,
|
2004-10-16 20:43:38 +00:00
|
|
|
(ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
|
2005-10-19 19:51:16 +00:00
|
|
|
u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
|
2006-03-13 05:15:10 +00:00
|
|
|
[]>, PPC970_DGroup_Cracked;
|
2004-10-16 20:43:38 +00:00
|
|
|
}
|
2005-04-19 05:21:30 +00:00
|
|
|
def RLWINM : MForm_2<21,
|
2004-08-31 02:28:08 +00:00
|
|
|
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
2005-10-19 19:51:16 +00:00
|
|
|
"rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
|
2005-10-19 18:42:01 +00:00
|
|
|
[]>;
|
2005-04-19 05:21:30 +00:00
|
|
|
def RLWINMo : MForm_2<21,
|
2005-04-12 00:10:02 +00:00
|
|
|
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
2005-10-19 19:51:16 +00:00
|
|
|
"rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
|
2006-03-13 05:15:10 +00:00
|
|
|
[]>, isDOT, PPC970_DGroup_Cracked;
|
2005-04-19 05:21:30 +00:00
|
|
|
def RLWNM : MForm_2<23,
|
2005-04-09 20:09:12 +00:00
|
|
|
(ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
|
2005-10-19 19:51:16 +00:00
|
|
|
"rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
|
2005-10-19 18:42:01 +00:00
|
|
|
[]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2004-08-31 02:28:08 +00:00
|
|
|
|
2006-03-20 06:15:45 +00:00
|
|
|
|
2005-12-16 22:45:29 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// DWARF Pseudo Instructions
|
|
|
|
//
|
|
|
|
|
2006-01-05 01:25:28 +00:00
|
|
|
def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
|
2006-09-27 02:55:21 +00:00
|
|
|
"${:comment} .loc $file, $line, $col",
|
2005-12-16 22:45:29 +00:00
|
|
|
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
|
2006-01-05 01:25:28 +00:00
|
|
|
(i32 imm:$file))]>;
|
|
|
|
|
|
|
|
def DWARF_LABEL : Pseudo<(ops i32imm:$id),
|
2006-09-27 02:55:21 +00:00
|
|
|
"\n${:private}debug_loc$id:",
|
2006-01-05 01:25:28 +00:00
|
|
|
[(dwarf_label (i32 imm:$id))]>;
|
2005-12-16 22:45:29 +00:00
|
|
|
|
2005-09-09 00:39:56 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Instruction Patterns
|
|
|
|
//
|
|
|
|
|
2005-09-26 22:20:16 +00:00
|
|
|
// Arbitrary immediate support. Implement in terms of LIS/ORI.
|
|
|
|
def : Pat<(i32 imm:$imm),
|
|
|
|
(ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
2005-09-28 17:13:15 +00:00
|
|
|
|
|
|
|
// Implement the 'not' operation with the NOR instruction.
|
|
|
|
def NOT : Pat<(not GPRC:$in),
|
|
|
|
(NOR GPRC:$in, GPRC:$in)>;
|
|
|
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2005-09-28 23:07:13 +00:00
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// ADD an arbitrary immediate.
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def : Pat<(add GPRC:$in, imm:$imm),
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(ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
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// OR an arbitrary immediate.
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2005-09-09 00:39:56 +00:00
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def : Pat<(or GPRC:$in, imm:$imm),
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(ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
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2005-09-28 23:07:13 +00:00
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// XOR an arbitrary immediate.
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2005-09-09 00:39:56 +00:00
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def : Pat<(xor GPRC:$in, imm:$imm),
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(XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
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2006-02-17 05:43:56 +00:00
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// SUBFIC
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2006-03-17 22:41:37 +00:00
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def : Pat<(sub immSExt16:$imm, GPRC:$in),
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2006-02-17 05:43:56 +00:00
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(SUBFIC GPRC:$in, imm:$imm)>;
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2005-10-19 01:38:02 +00:00
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2006-01-09 23:20:37 +00:00
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// Return void support.
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def : Pat<(ret), (BLR)>;
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2006-06-16 20:22:01 +00:00
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// SHL/SRL
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2005-12-05 02:34:05 +00:00
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def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
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2005-10-19 18:42:01 +00:00
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(RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
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2005-12-05 02:34:05 +00:00
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def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
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2005-10-19 18:42:01 +00:00
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(RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
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2006-01-11 21:21:00 +00:00
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// ROTL
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def : Pat<(rotl GPRC:$in, GPRC:$sh),
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(RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
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def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
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(RLWINM GPRC:$in, imm:$imm, 0, 31)>;
|
2006-05-17 19:00:46 +00:00
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2006-09-22 05:01:56 +00:00
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// RLWNM
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def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
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(RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
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2006-05-17 19:00:46 +00:00
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// Calls
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def : Pat<(PPCcall tglobaladdr:$dst),
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(BL tglobaladdr:$dst)>;
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def : Pat<(PPCcall texternalsym:$dst),
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(BL texternalsym:$dst)>;
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|
2005-11-17 07:30:41 +00:00
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// Hi and Lo for Darwin Global Addresses.
|
2005-12-11 07:45:47 +00:00
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|
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def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
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def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
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|
def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
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def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
|
2006-04-22 18:53:45 +00:00
|
|
|
def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
|
|
|
|
def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
|
2005-11-17 17:52:01 +00:00
|
|
|
def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
|
|
|
|
(ADDIS GPRC:$in, tglobaladdr:$g)>;
|
2005-12-10 02:36:00 +00:00
|
|
|
def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
|
|
|
|
(ADDIS GPRC:$in, tconstpool:$g)>;
|
2006-04-22 18:53:45 +00:00
|
|
|
def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
|
|
|
|
(ADDIS GPRC:$in, tjumptable:$g)>;
|
2005-11-17 07:30:41 +00:00
|
|
|
|
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:54:33 +00:00
|
|
|
// Fused negative multiply subtract, alternate pattern
|
|
|
|
def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
|
|
|
|
(FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
|
|
|
|
Requires<[FPContractions]>;
|
|
|
|
def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
|
|
|
|
(FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
|
|
|
|
Requires<[FPContractions]>;
|
|
|
|
|
2005-12-06 02:10:38 +00:00
|
|
|
// Standard shifts. These are represented separately from the real shifts above
|
|
|
|
// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
|
|
|
|
// amounts.
|
|
|
|
def : Pat<(sra GPRC:$rS, GPRC:$rB),
|
|
|
|
(SRAW GPRC:$rS, GPRC:$rB)>;
|
|
|
|
def : Pat<(srl GPRC:$rS, GPRC:$rB),
|
|
|
|
(SRW GPRC:$rS, GPRC:$rB)>;
|
|
|
|
def : Pat<(shl GPRC:$rS, GPRC:$rB),
|
|
|
|
(SLW GPRC:$rS, GPRC:$rB)>;
|
|
|
|
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(zextloadi1 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZ iaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(zextloadi1 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZX xaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi1 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZ iaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi1 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZX xaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi8 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZ iaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi8 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZX xaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi16 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LHZ iaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi16 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LHZX xaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadf32 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(FMRSD (LFS iaddr:$src))>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadf32 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(FMRSD (LFSX xaddr:$src))>;
|
|
|
|
|
2006-03-25 07:51:43 +00:00
|
|
|
include "PPCInstrAltivec.td"
|
2006-06-16 20:22:01 +00:00
|
|
|
include "PPCInstr64Bit.td"
|