2012-02-18 12:03:15 +00:00
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//===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
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2007-01-19 07:51:42 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-01-19 07:51:42 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that performs load / store related peephole
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// optimizations. This pass should be run after register allocation.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-ldst-opt"
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#include "ARM.h"
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2009-08-08 03:20:32 +00:00
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#include "ARMBaseInstrInfo.h"
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2012-03-26 00:45:15 +00:00
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#include "ARMBaseRegisterInfo.h"
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2007-03-07 20:30:36 +00:00
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#include "ARMMachineFunctionInfo.h"
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2011-07-20 23:34:39 +00:00
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#include "MCTargetDesc/ARMAddressingModes.h"
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2009-06-15 08:28:29 +00:00
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#include "llvm/DerivedTypes.h"
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2009-08-13 21:58:54 +00:00
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#include "llvm/Function.h"
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2007-01-19 07:51:42 +00:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2009-06-13 09:12:55 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2007-03-06 18:02:41 +00:00
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#include "llvm/CodeGen/RegisterScavenging.h"
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2011-07-20 23:34:39 +00:00
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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2009-06-15 08:28:29 +00:00
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#include "llvm/Target/TargetData.h"
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2007-01-19 07:51:42 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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2009-06-15 08:28:29 +00:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2009-07-08 18:01:40 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2011-11-11 22:18:09 +00:00
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#include "llvm/Support/Debug.h"
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2011-11-25 09:19:57 +00:00
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#include "llvm/Support/raw_ostream.h"
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2009-06-13 09:12:55 +00:00
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallPtrSet.h"
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2009-06-19 23:17:27 +00:00
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#include "llvm/ADT/SmallSet.h"
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2009-06-13 09:12:55 +00:00
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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2007-01-19 07:51:42 +00:00
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using namespace llvm;
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STATISTIC(NumLDMGened , "Number of ldm instructions generated");
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STATISTIC(NumSTMGened , "Number of stm instructions generated");
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2009-11-09 00:11:35 +00:00
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STATISTIC(NumVLDMGened, "Number of vldm instructions generated");
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STATISTIC(NumVSTMGened, "Number of vstm instructions generated");
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2009-06-13 09:12:55 +00:00
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STATISTIC(NumLdStMoved, "Number of load / store instructions moved");
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2009-06-18 02:04:01 +00:00
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STATISTIC(NumLDRDFormed,"Number of ldrd created before allocation");
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STATISTIC(NumSTRDFormed,"Number of strd created before allocation");
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STATISTIC(NumLDRD2LDM, "Number of ldrd instructions turned back into ldm");
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STATISTIC(NumSTRD2STM, "Number of strd instructions turned back into stm");
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STATISTIC(NumLDRD2LDR, "Number of ldrd instructions turned back into ldr's");
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STATISTIC(NumSTRD2STR, "Number of strd instructions turned back into str's");
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2009-06-13 09:12:55 +00:00
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/// ARMAllocLoadStoreOpt - Post- register allocation pass the combine
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/// load / store instructions to form ldm / stm instructions.
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2007-01-19 07:51:42 +00:00
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namespace {
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2009-10-25 06:33:48 +00:00
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struct ARMLoadStoreOpt : public MachineFunctionPass {
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2007-05-03 01:11:54 +00:00
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static char ID;
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2010-08-06 18:33:48 +00:00
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ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
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2007-05-01 21:15:47 +00:00
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2007-01-19 07:51:42 +00:00
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const TargetInstrInfo *TII;
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2008-02-10 18:45:23 +00:00
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const TargetRegisterInfo *TRI;
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2011-11-08 21:21:09 +00:00
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const ARMSubtarget *STI;
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2007-03-07 20:30:36 +00:00
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ARMFunctionInfo *AFI;
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2007-03-06 18:02:41 +00:00
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RegScavenger *RS;
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2009-07-09 23:11:34 +00:00
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bool isThumb2;
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2007-01-19 07:51:42 +00:00
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "ARM load / store optimization pass";
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}
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private:
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struct MemOpQueueEntry {
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int Offset;
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2010-06-21 21:21:14 +00:00
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unsigned Reg;
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bool isKill;
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2007-01-19 07:51:42 +00:00
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unsigned Position;
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MachineBasicBlock::iterator MBBI;
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bool Merged;
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2011-03-29 16:45:53 +00:00
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MemOpQueueEntry(int o, unsigned r, bool k, unsigned p,
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2010-06-21 21:21:14 +00:00
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MachineBasicBlock::iterator i)
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: Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
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2007-01-19 07:51:42 +00:00
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};
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typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
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typedef MemOpQueue::iterator MemOpQueueIter;
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2009-06-05 19:08:58 +00:00
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bool MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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2009-06-05 18:19:23 +00:00
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int Offset, unsigned Base, bool BaseKill, int Opcode,
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ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
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DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs);
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2009-12-23 21:28:23 +00:00
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void MergeOpsUpdate(MachineBasicBlock &MBB,
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2009-12-23 21:28:37 +00:00
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MemOpQueue &MemOps,
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unsigned memOpsBegin,
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unsigned memOpsEnd,
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unsigned insertAfter,
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2009-12-23 21:28:23 +00:00
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int Offset,
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unsigned Base,
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bool BaseKill,
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int Opcode,
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ARMCC::CondCodes Pred,
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unsigned PredReg,
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unsigned Scratch,
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DebugLoc dl,
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SmallVector<MachineBasicBlock::iterator, 4> &Merges);
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2009-06-05 17:56:14 +00:00
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void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
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int Opcode, unsigned Size,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned Scratch, MemOpQueue &MemOps,
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SmallVector<MachineBasicBlock::iterator, 4> &Merges);
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2007-01-19 07:51:42 +00:00
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2007-03-08 02:55:08 +00:00
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void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
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2009-06-15 08:28:29 +00:00
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bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI);
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2009-07-09 23:11:34 +00:00
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bool MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const TargetInstrInfo *TII,
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bool &Advance,
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MachineBasicBlock::iterator &I);
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bool MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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bool &Advance,
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MachineBasicBlock::iterator &I);
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2007-01-19 07:51:42 +00:00
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bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
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bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
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};
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2007-05-03 01:11:54 +00:00
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char ARMLoadStoreOpt::ID = 0;
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2007-01-19 07:51:42 +00:00
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}
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2010-11-16 01:16:36 +00:00
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static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
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2007-01-19 07:51:42 +00:00
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switch (Opcode) {
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2010-11-16 01:16:36 +00:00
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default: llvm_unreachable("Unhandled opcode!");
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2010-10-26 22:37:02 +00:00
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case ARM::LDRi12:
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2010-06-22 15:08:57 +00:00
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++NumLDMGened;
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2010-11-16 01:16:36 +00:00
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switch (Mode) {
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default: llvm_unreachable("Unhandled submode!");
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case ARM_AM::ia: return ARM::LDMIA;
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case ARM_AM::da: return ARM::LDMDA;
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case ARM_AM::db: return ARM::LDMDB;
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case ARM_AM::ib: return ARM::LDMIB;
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}
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2010-10-27 23:12:14 +00:00
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case ARM::STRi12:
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2010-06-22 15:08:57 +00:00
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++NumSTMGened;
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2010-11-16 01:16:36 +00:00
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switch (Mode) {
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default: llvm_unreachable("Unhandled submode!");
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case ARM_AM::ia: return ARM::STMIA;
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case ARM_AM::da: return ARM::STMDA;
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case ARM_AM::db: return ARM::STMDB;
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case ARM_AM::ib: return ARM::STMIB;
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}
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2009-07-09 23:11:34 +00:00
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case ARM::t2LDRi8:
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case ARM::t2LDRi12:
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2010-06-22 15:08:57 +00:00
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++NumLDMGened;
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2010-11-16 01:16:36 +00:00
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switch (Mode) {
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default: llvm_unreachable("Unhandled submode!");
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case ARM_AM::ia: return ARM::t2LDMIA;
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case ARM_AM::db: return ARM::t2LDMDB;
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}
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2009-07-09 23:11:34 +00:00
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case ARM::t2STRi8:
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case ARM::t2STRi12:
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2010-06-22 15:08:57 +00:00
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++NumSTMGened;
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2010-11-16 01:16:36 +00:00
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switch (Mode) {
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default: llvm_unreachable("Unhandled submode!");
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case ARM_AM::ia: return ARM::t2STMIA;
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case ARM_AM::db: return ARM::t2STMDB;
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}
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2009-11-09 00:11:35 +00:00
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case ARM::VLDRS:
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2010-06-22 15:08:57 +00:00
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++NumVLDMGened;
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2010-11-16 01:16:36 +00:00
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switch (Mode) {
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default: llvm_unreachable("Unhandled submode!");
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case ARM_AM::ia: return ARM::VLDMSIA;
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2011-03-29 16:45:53 +00:00
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case ARM_AM::db: return 0; // Only VLDMSDB_UPD exists.
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2010-11-16 01:16:36 +00:00
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}
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2009-11-09 00:11:35 +00:00
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case ARM::VSTRS:
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2010-06-22 15:08:57 +00:00
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++NumVSTMGened;
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2010-11-16 01:16:36 +00:00
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switch (Mode) {
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default: llvm_unreachable("Unhandled submode!");
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case ARM_AM::ia: return ARM::VSTMSIA;
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2011-03-29 16:45:53 +00:00
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case ARM_AM::db: return 0; // Only VSTMSDB_UPD exists.
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2010-11-16 01:16:36 +00:00
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}
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2009-11-09 00:11:35 +00:00
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case ARM::VLDRD:
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2010-06-22 15:08:57 +00:00
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++NumVLDMGened;
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2010-11-16 01:16:36 +00:00
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switch (Mode) {
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default: llvm_unreachable("Unhandled submode!");
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case ARM_AM::ia: return ARM::VLDMDIA;
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2011-03-29 16:45:53 +00:00
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case ARM_AM::db: return 0; // Only VLDMDDB_UPD exists.
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2010-11-16 01:16:36 +00:00
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}
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2009-11-09 00:11:35 +00:00
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case ARM::VSTRD:
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2010-06-22 15:08:57 +00:00
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++NumVSTMGened;
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2010-11-16 01:16:36 +00:00
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switch (Mode) {
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default: llvm_unreachable("Unhandled submode!");
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case ARM_AM::ia: return ARM::VSTMDIA;
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2011-03-29 16:45:53 +00:00
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case ARM_AM::db: return 0; // Only VSTMDDB_UPD exists.
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2010-11-16 01:16:36 +00:00
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}
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2007-01-19 07:51:42 +00:00
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}
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}
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2010-11-17 05:31:09 +00:00
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namespace llvm {
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namespace ARM_AM {
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AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
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2010-11-16 01:16:36 +00:00
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switch (Opcode) {
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default: llvm_unreachable("Unhandled opcode!");
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2010-11-18 19:44:29 +00:00
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case ARM::LDMIA_RET:
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2010-11-16 01:16:36 +00:00
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case ARM::LDMIA:
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2010-11-17 19:16:20 +00:00
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case ARM::LDMIA_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::STMIA:
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2010-11-17 19:16:20 +00:00
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case ARM::STMIA_UPD:
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2010-11-18 19:44:29 +00:00
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case ARM::t2LDMIA_RET:
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2010-11-16 01:16:36 +00:00
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case ARM::t2LDMIA:
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2010-11-17 19:16:20 +00:00
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case ARM::t2LDMIA_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::t2STMIA:
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2010-11-17 19:16:20 +00:00
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case ARM::t2STMIA_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::VLDMSIA:
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2010-11-17 19:16:20 +00:00
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case ARM::VLDMSIA_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::VSTMSIA:
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2010-11-17 19:16:20 +00:00
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case ARM::VSTMSIA_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::VLDMDIA:
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2010-11-17 19:16:20 +00:00
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case ARM::VLDMDIA_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::VSTMDIA:
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2010-11-17 19:16:20 +00:00
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case ARM::VSTMDIA_UPD:
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2010-11-16 01:16:36 +00:00
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return ARM_AM::ia;
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case ARM::LDMDA:
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2010-11-17 19:16:20 +00:00
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case ARM::LDMDA_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::STMDA:
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2010-11-17 19:16:20 +00:00
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case ARM::STMDA_UPD:
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2010-11-16 01:16:36 +00:00
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return ARM_AM::da;
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case ARM::LDMDB:
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2010-11-17 19:16:20 +00:00
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case ARM::LDMDB_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::STMDB:
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2010-11-17 19:16:20 +00:00
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case ARM::STMDB_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::t2LDMDB:
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2010-11-17 19:16:20 +00:00
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case ARM::t2LDMDB_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::t2STMDB:
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2010-11-17 19:16:20 +00:00
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case ARM::t2STMDB_UPD:
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case ARM::VLDMSDB_UPD:
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case ARM::VSTMSDB_UPD:
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case ARM::VLDMDDB_UPD:
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case ARM::VSTMDDB_UPD:
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2010-11-16 01:16:36 +00:00
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return ARM_AM::db;
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case ARM::LDMIB:
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2010-11-17 19:16:20 +00:00
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case ARM::LDMIB_UPD:
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2010-11-16 01:16:36 +00:00
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case ARM::STMIB:
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2010-11-17 19:16:20 +00:00
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case ARM::STMIB_UPD:
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2010-11-16 01:16:36 +00:00
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return ARM_AM::ib;
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}
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}
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2010-11-17 05:31:09 +00:00
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} // end namespace ARM_AM
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} // end namespace llvm
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2009-08-04 01:43:45 +00:00
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static bool isT2i32Load(unsigned Opc) {
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|
|
return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
|
|
|
|
}
|
|
|
|
|
2009-07-09 23:11:34 +00:00
|
|
|
static bool isi32Load(unsigned Opc) {
|
2010-10-26 22:37:02 +00:00
|
|
|
return Opc == ARM::LDRi12 || isT2i32Load(Opc);
|
2009-08-04 01:43:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool isT2i32Store(unsigned Opc) {
|
|
|
|
return Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8;
|
2009-07-09 23:11:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool isi32Store(unsigned Opc) {
|
2010-10-27 23:12:14 +00:00
|
|
|
return Opc == ARM::STRi12 || isT2i32Store(Opc);
|
2009-07-09 23:11:34 +00:00
|
|
|
}
|
|
|
|
|
2009-06-05 19:08:58 +00:00
|
|
|
/// MergeOps - Create and insert a LDM or STM with Base as base register and
|
2007-01-19 07:51:42 +00:00
|
|
|
/// registers in Regs as the register operands that would be loaded / stored.
|
2009-08-11 15:33:49 +00:00
|
|
|
/// It returns true if the transformation is done.
|
2009-06-05 18:19:23 +00:00
|
|
|
bool
|
2009-06-05 19:08:58 +00:00
|
|
|
ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
|
2009-06-05 18:19:23 +00:00
|
|
|
MachineBasicBlock::iterator MBBI,
|
|
|
|
int Offset, unsigned Base, bool BaseKill,
|
|
|
|
int Opcode, ARMCC::CondCodes Pred,
|
|
|
|
unsigned PredReg, unsigned Scratch, DebugLoc dl,
|
|
|
|
SmallVector<std::pair<unsigned, bool>, 8> &Regs) {
|
2007-01-19 07:51:42 +00:00
|
|
|
// Only a single register to load / store. Don't bother.
|
|
|
|
unsigned NumRegs = Regs.size();
|
|
|
|
if (NumRegs <= 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
ARM_AM::AMSubMode Mode = ARM_AM::ia;
|
2010-08-27 23:57:52 +00:00
|
|
|
// VFP and Thumb2 do not support IB or DA modes.
|
2010-08-27 23:18:17 +00:00
|
|
|
bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
|
2010-08-27 23:57:52 +00:00
|
|
|
bool haveIBAndDA = isNotVFP && !isThumb2;
|
|
|
|
if (Offset == 4 && haveIBAndDA)
|
2007-01-19 07:51:42 +00:00
|
|
|
Mode = ARM_AM::ib;
|
2010-08-27 23:57:52 +00:00
|
|
|
else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA)
|
2007-01-19 07:51:42 +00:00
|
|
|
Mode = ARM_AM::da;
|
2010-08-27 23:57:52 +00:00
|
|
|
else if (Offset == -4 * (int)NumRegs && isNotVFP)
|
|
|
|
// VLDM/VSTM do not support DB mode without also updating the base reg.
|
2007-01-19 07:51:42 +00:00
|
|
|
Mode = ARM_AM::db;
|
2010-08-27 23:57:52 +00:00
|
|
|
else if (Offset != 0) {
|
2011-03-29 20:27:38 +00:00
|
|
|
// Check if this is a supported opcode before we insert instructions to
|
|
|
|
// calculate a new base register.
|
|
|
|
if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return false;
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
// If starting offset isn't zero, insert a MI to materialize a new base.
|
|
|
|
// But only do so if it is cost effective, i.e. merging more than two
|
|
|
|
// loads / stores.
|
|
|
|
if (NumRegs <= 2)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned NewBase;
|
2009-07-09 23:11:34 +00:00
|
|
|
if (isi32Load(Opcode))
|
2007-01-19 07:51:42 +00:00
|
|
|
// If it is a load, then just use one of the destination register to
|
|
|
|
// use as the new base.
|
2007-03-06 21:59:20 +00:00
|
|
|
NewBase = Regs[NumRegs-1].first;
|
2007-01-19 07:51:42 +00:00
|
|
|
else {
|
2007-03-07 02:38:05 +00:00
|
|
|
// Use the scratch register to use as a new base.
|
|
|
|
NewBase = Scratch;
|
2007-03-06 21:59:20 +00:00
|
|
|
if (NewBase == 0)
|
|
|
|
return false;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2011-06-29 23:25:04 +00:00
|
|
|
int BaseOpc = !isThumb2 ? ARM::ADDri : ARM::t2ADDri;
|
2007-01-19 07:51:42 +00:00
|
|
|
if (Offset < 0) {
|
2011-06-29 23:25:04 +00:00
|
|
|
BaseOpc = !isThumb2 ? ARM::SUBri : ARM::t2SUBri;
|
2007-01-19 07:51:42 +00:00
|
|
|
Offset = - Offset;
|
|
|
|
}
|
2009-07-09 23:11:34 +00:00
|
|
|
int ImmedOffset = isThumb2
|
|
|
|
? ARM_AM::getT2SOImmVal(Offset) : ARM_AM::getSOImmVal(Offset);
|
|
|
|
if (ImmedOffset == -1)
|
|
|
|
// FIXME: Try t2ADDri12 or t2SUBri12?
|
2007-01-19 07:51:42 +00:00
|
|
|
return false; // Probably not worth it then.
|
2007-03-06 21:59:20 +00:00
|
|
|
|
2009-02-13 02:25:56 +00:00
|
|
|
BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
|
2009-07-08 21:03:57 +00:00
|
|
|
.addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
|
2007-07-10 18:08:01 +00:00
|
|
|
.addImm(Pred).addReg(PredReg).addReg(0);
|
2007-01-19 07:51:42 +00:00
|
|
|
Base = NewBase;
|
2007-03-06 21:59:20 +00:00
|
|
|
BaseKill = true; // New base is always killed right its use.
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2010-03-16 00:31:15 +00:00
|
|
|
bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
|
|
|
|
Opcode == ARM::VLDRD);
|
2010-11-16 01:16:36 +00:00
|
|
|
Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
|
2011-03-29 17:42:25 +00:00
|
|
|
if (!Opcode) return false;
|
2010-08-27 23:18:17 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
|
|
|
|
.addReg(Base, getKillRegState(BaseKill))
|
2010-11-16 01:16:36 +00:00
|
|
|
.addImm(Pred).addReg(PredReg);
|
2007-01-19 07:51:42 +00:00
|
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
2009-05-13 21:33:08 +00:00
|
|
|
MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
|
|
|
|
| getKillRegState(Regs[i].second));
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-12-23 21:28:23 +00:00
|
|
|
// MergeOpsUpdate - call MergeOps and update MemOps and merges accordingly on
|
|
|
|
// success.
|
2010-06-21 21:21:14 +00:00
|
|
|
void ARMLoadStoreOpt::MergeOpsUpdate(MachineBasicBlock &MBB,
|
|
|
|
MemOpQueue &memOps,
|
|
|
|
unsigned memOpsBegin, unsigned memOpsEnd,
|
|
|
|
unsigned insertAfter, int Offset,
|
|
|
|
unsigned Base, bool BaseKill,
|
|
|
|
int Opcode,
|
|
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
|
|
unsigned Scratch,
|
|
|
|
DebugLoc dl,
|
|
|
|
SmallVector<MachineBasicBlock::iterator, 4> &Merges) {
|
2009-12-23 21:28:31 +00:00
|
|
|
// First calculate which of the registers should be killed by the merged
|
|
|
|
// instruction.
|
2009-12-23 21:34:03 +00:00
|
|
|
const unsigned insertPos = memOps[insertAfter].Position;
|
2010-06-21 21:21:14 +00:00
|
|
|
SmallSet<unsigned, 4> KilledRegs;
|
|
|
|
DenseMap<unsigned, unsigned> Killer;
|
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15 19:51:58 +00:00
|
|
|
for (unsigned i = 0, e = memOps.size(); i != e; ++i) {
|
|
|
|
if (i == memOpsBegin) {
|
|
|
|
i = memOpsEnd;
|
|
|
|
if (i == e)
|
|
|
|
break;
|
2010-06-21 21:21:14 +00:00
|
|
|
}
|
|
|
|
if (memOps[i].Position < insertPos && memOps[i].isKill) {
|
|
|
|
unsigned Reg = memOps[i].Reg;
|
|
|
|
KilledRegs.insert(Reg);
|
|
|
|
Killer[Reg] = i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
SmallVector<std::pair<unsigned, bool>, 8> Regs;
|
2009-12-23 21:28:37 +00:00
|
|
|
for (unsigned i = memOpsBegin; i < memOpsEnd; ++i) {
|
2010-06-21 21:21:14 +00:00
|
|
|
unsigned Reg = memOps[i].Reg;
|
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15 19:51:58 +00:00
|
|
|
// If we are inserting the merged operation after an operation that
|
2009-12-23 21:34:03 +00:00
|
|
|
// uses the same register, make sure to transfer any kill flag.
|
2010-06-21 21:21:14 +00:00
|
|
|
bool isKill = memOps[i].isKill || KilledRegs.count(Reg);
|
2009-12-23 21:34:03 +00:00
|
|
|
Regs.push_back(std::make_pair(Reg, isKill));
|
2009-12-23 21:28:31 +00:00
|
|
|
}
|
|
|
|
|
2009-12-23 21:28:37 +00:00
|
|
|
// Try to do the merge.
|
|
|
|
MachineBasicBlock::iterator Loc = memOps[insertAfter].MBBI;
|
2010-06-22 15:08:57 +00:00
|
|
|
++Loc;
|
2009-12-23 21:28:37 +00:00
|
|
|
if (!MergeOps(MBB, Loc, Offset, Base, BaseKill, Opcode,
|
2009-12-23 21:28:23 +00:00
|
|
|
Pred, PredReg, Scratch, dl, Regs))
|
|
|
|
return;
|
2009-12-23 21:28:31 +00:00
|
|
|
|
|
|
|
// Merge succeeded, update records.
|
2009-12-23 21:28:37 +00:00
|
|
|
Merges.push_back(prior(Loc));
|
|
|
|
for (unsigned i = memOpsBegin; i < memOpsEnd; ++i) {
|
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15 19:51:58 +00:00
|
|
|
// Remove kill flags from any memops that come before insertPos.
|
2010-06-21 21:21:14 +00:00
|
|
|
if (Regs[i-memOpsBegin].second) {
|
|
|
|
unsigned Reg = Regs[i-memOpsBegin].first;
|
|
|
|
if (KilledRegs.count(Reg)) {
|
|
|
|
unsigned j = Killer[Reg];
|
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15 19:51:58 +00:00
|
|
|
int Idx = memOps[j].MBBI->findRegisterUseOperandIdx(Reg, true);
|
|
|
|
assert(Idx >= 0 && "Cannot find killing operand");
|
|
|
|
memOps[j].MBBI->getOperand(Idx).setIsKill(false);
|
2010-08-30 21:52:40 +00:00
|
|
|
memOps[j].isKill = false;
|
2010-06-21 21:21:14 +00:00
|
|
|
}
|
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15 19:51:58 +00:00
|
|
|
memOps[i].isKill = true;
|
2010-06-21 21:21:14 +00:00
|
|
|
}
|
2009-12-23 21:28:37 +00:00
|
|
|
MBB.erase(memOps[i].MBBI);
|
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15 19:51:58 +00:00
|
|
|
// Update this memop to refer to the merged instruction.
|
|
|
|
// We may need to move kill flags again.
|
2009-12-23 21:28:37 +00:00
|
|
|
memOps[i].Merged = true;
|
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15 19:51:58 +00:00
|
|
|
memOps[i].MBBI = Merges.back();
|
|
|
|
memOps[i].Position = insertPos;
|
2009-12-23 21:28:23 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-06 21:59:20 +00:00
|
|
|
/// MergeLDR_STR - Merge a number of load / store instructions into one or more
|
|
|
|
/// load / store multiple instructions.
|
2009-06-05 17:56:14 +00:00
|
|
|
void
|
2007-03-07 02:38:05 +00:00
|
|
|
ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
|
2009-06-05 17:56:14 +00:00
|
|
|
unsigned Base, int Opcode, unsigned Size,
|
|
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
|
|
unsigned Scratch, MemOpQueue &MemOps,
|
|
|
|
SmallVector<MachineBasicBlock::iterator, 4> &Merges) {
|
2010-08-27 23:18:17 +00:00
|
|
|
bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
|
2007-01-19 07:51:42 +00:00
|
|
|
int Offset = MemOps[SIndex].Offset;
|
|
|
|
int SOffset = Offset;
|
2009-12-23 21:28:37 +00:00
|
|
|
unsigned insertAfter = SIndex;
|
2007-01-19 07:51:42 +00:00
|
|
|
MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI;
|
2009-06-05 18:19:23 +00:00
|
|
|
DebugLoc dl = Loc->getDebugLoc();
|
2009-12-23 21:28:42 +00:00
|
|
|
const MachineOperand &PMO = Loc->getOperand(0);
|
|
|
|
unsigned PReg = PMO.getReg();
|
|
|
|
unsigned PRegNum = PMO.isUndef() ? UINT_MAX
|
2010-09-15 20:26:25 +00:00
|
|
|
: getARMRegisterNumbering(PReg);
|
2010-03-26 18:41:09 +00:00
|
|
|
unsigned Count = 1;
|
2011-04-05 23:03:25 +00:00
|
|
|
unsigned Limit = ~0U;
|
|
|
|
|
|
|
|
// vldm / vstm limit are 32 for S variants, 16 for D variants.
|
|
|
|
|
|
|
|
switch (Opcode) {
|
|
|
|
default: break;
|
|
|
|
case ARM::VSTRS:
|
|
|
|
Limit = 32;
|
|
|
|
break;
|
|
|
|
case ARM::VSTRD:
|
|
|
|
Limit = 16;
|
|
|
|
break;
|
|
|
|
case ARM::VLDRD:
|
|
|
|
Limit = 16;
|
|
|
|
break;
|
|
|
|
case ARM::VLDRS:
|
|
|
|
Limit = 32;
|
|
|
|
break;
|
|
|
|
}
|
2007-05-15 01:29:07 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
|
|
|
|
int NewOffset = MemOps[i].Offset;
|
2009-12-23 21:28:42 +00:00
|
|
|
const MachineOperand &MO = MemOps[i].MBBI->getOperand(0);
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
unsigned RegNum = MO.isUndef() ? UINT_MAX
|
2010-09-15 20:26:25 +00:00
|
|
|
: getARMRegisterNumbering(Reg);
|
2011-04-05 23:03:25 +00:00
|
|
|
// Register numbers must be in ascending order. For VFP / NEON load and
|
|
|
|
// store multiples, the registers must also be consecutive and within the
|
|
|
|
// limit on the number of registers per instruction.
|
2010-02-12 22:17:21 +00:00
|
|
|
if (Reg != ARM::SP &&
|
|
|
|
NewOffset == Offset + (int)Size &&
|
2011-04-05 23:03:25 +00:00
|
|
|
((isNotVFP && RegNum > PRegNum) ||
|
|
|
|
((Count < Limit) && RegNum == PRegNum+1))) {
|
2007-01-19 07:51:42 +00:00
|
|
|
Offset += Size;
|
|
|
|
PRegNum = RegNum;
|
2010-03-26 18:41:09 +00:00
|
|
|
++Count;
|
2007-01-19 07:51:42 +00:00
|
|
|
} else {
|
|
|
|
// Can't merge this in. Try merge the earlier ones first.
|
2009-12-23 21:28:37 +00:00
|
|
|
MergeOpsUpdate(MBB, MemOps, SIndex, i, insertAfter, SOffset,
|
|
|
|
Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
|
2009-06-05 17:56:14 +00:00
|
|
|
MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
|
|
|
|
MemOps, Merges);
|
|
|
|
return;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2009-12-23 21:28:37 +00:00
|
|
|
if (MemOps[i].Position > MemOps[insertAfter].Position)
|
|
|
|
insertAfter = i;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2007-04-26 19:00:32 +00:00
|
|
|
bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
|
2009-12-23 21:28:37 +00:00
|
|
|
MergeOpsUpdate(MBB, MemOps, SIndex, MemOps.size(), insertAfter, SOffset,
|
|
|
|
Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
|
2009-06-05 17:56:14 +00:00
|
|
|
return;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2012-02-07 07:09:28 +00:00
|
|
|
static bool definesCPSR(MachineInstr *MI) {
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg())
|
|
|
|
continue;
|
|
|
|
if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
|
|
|
|
// If the instruction has live CPSR def, then it's not safe to fold it
|
|
|
|
// into load / store.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
|
|
|
|
unsigned Bytes, unsigned Limit,
|
|
|
|
ARMCC::CondCodes Pred, unsigned PredReg) {
|
2007-07-05 07:18:20 +00:00
|
|
|
unsigned MyPredReg = 0;
|
2009-07-09 23:11:34 +00:00
|
|
|
if (!MI)
|
|
|
|
return false;
|
2012-02-07 07:09:28 +00:00
|
|
|
|
|
|
|
bool CheckCPSRDef = false;
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default: return false;
|
|
|
|
case ARM::t2SUBri:
|
|
|
|
case ARM::SUBri:
|
|
|
|
CheckCPSRDef = true;
|
|
|
|
// fallthrough
|
|
|
|
case ARM::tSUBspi:
|
|
|
|
break;
|
|
|
|
}
|
2009-08-04 01:43:45 +00:00
|
|
|
|
|
|
|
// Make sure the offset fits in 8 bits.
|
2010-08-27 21:44:35 +00:00
|
|
|
if (Bytes == 0 || (Limit && Bytes >= Limit))
|
2009-08-04 01:43:45 +00:00
|
|
|
return false;
|
2009-07-09 23:11:34 +00:00
|
|
|
|
2009-08-07 00:34:42 +00:00
|
|
|
unsigned Scale = (MI->getOpcode() == ARM::tSUBspi) ? 4 : 1; // FIXME
|
2012-02-07 07:09:28 +00:00
|
|
|
if (!(MI->getOperand(0).getReg() == Base &&
|
|
|
|
MI->getOperand(1).getReg() == Base &&
|
|
|
|
(MI->getOperand(2).getImm()*Scale) == Bytes &&
|
2012-03-27 07:21:54 +00:00
|
|
|
getInstrPredicate(MI, MyPredReg) == Pred &&
|
2012-02-07 07:09:28 +00:00
|
|
|
MyPredReg == PredReg))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return CheckCPSRDef ? !definesCPSR(MI) : true;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2012-02-07 07:09:28 +00:00
|
|
|
static bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
|
|
|
|
unsigned Bytes, unsigned Limit,
|
|
|
|
ARMCC::CondCodes Pred, unsigned PredReg) {
|
2007-07-05 07:18:20 +00:00
|
|
|
unsigned MyPredReg = 0;
|
2009-07-09 23:11:34 +00:00
|
|
|
if (!MI)
|
|
|
|
return false;
|
2012-02-07 07:09:28 +00:00
|
|
|
|
|
|
|
bool CheckCPSRDef = false;
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default: return false;
|
|
|
|
case ARM::t2ADDri:
|
|
|
|
case ARM::ADDri:
|
|
|
|
CheckCPSRDef = true;
|
|
|
|
// fallthrough
|
|
|
|
case ARM::tADDspi:
|
|
|
|
break;
|
|
|
|
}
|
2009-08-04 01:43:45 +00:00
|
|
|
|
2010-08-27 21:44:35 +00:00
|
|
|
if (Bytes == 0 || (Limit && Bytes >= Limit))
|
2009-07-09 23:11:34 +00:00
|
|
|
// Make sure the offset fits in 8 bits.
|
2009-08-04 01:43:45 +00:00
|
|
|
return false;
|
2009-07-09 23:11:34 +00:00
|
|
|
|
2009-08-07 00:34:42 +00:00
|
|
|
unsigned Scale = (MI->getOpcode() == ARM::tADDspi) ? 4 : 1; // FIXME
|
2012-02-07 07:09:28 +00:00
|
|
|
if (!(MI->getOperand(0).getReg() == Base &&
|
|
|
|
MI->getOperand(1).getReg() == Base &&
|
|
|
|
(MI->getOperand(2).getImm()*Scale) == Bytes &&
|
2012-03-27 07:21:54 +00:00
|
|
|
getInstrPredicate(MI, MyPredReg) == Pred &&
|
2012-02-07 07:09:28 +00:00
|
|
|
MyPredReg == PredReg))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return CheckCPSRDef ? !definesCPSR(MI) : true;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default: return 0;
|
2010-10-26 22:37:02 +00:00
|
|
|
case ARM::LDRi12:
|
2010-10-27 23:12:14 +00:00
|
|
|
case ARM::STRi12:
|
2009-07-09 23:11:34 +00:00
|
|
|
case ARM::t2LDRi8:
|
|
|
|
case ARM::t2LDRi12:
|
|
|
|
case ARM::t2STRi8:
|
|
|
|
case ARM::t2STRi12:
|
2009-11-09 00:11:35 +00:00
|
|
|
case ARM::VLDRS:
|
|
|
|
case ARM::VSTRS:
|
2007-01-19 07:51:42 +00:00
|
|
|
return 4;
|
2009-11-09 00:11:35 +00:00
|
|
|
case ARM::VLDRD:
|
|
|
|
case ARM::VSTRD:
|
2007-01-19 07:51:42 +00:00
|
|
|
return 8;
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::LDMIA:
|
|
|
|
case ARM::LDMDA:
|
|
|
|
case ARM::LDMDB:
|
|
|
|
case ARM::LDMIB:
|
|
|
|
case ARM::STMIA:
|
|
|
|
case ARM::STMDA:
|
|
|
|
case ARM::STMDB:
|
|
|
|
case ARM::STMIB:
|
|
|
|
case ARM::t2LDMIA:
|
|
|
|
case ARM::t2LDMDB:
|
|
|
|
case ARM::t2STMIA:
|
|
|
|
case ARM::t2STMDB:
|
|
|
|
case ARM::VLDMSIA:
|
|
|
|
case ARM::VSTMSIA:
|
2010-09-10 18:25:35 +00:00
|
|
|
return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 4;
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::VLDMDIA:
|
|
|
|
case ARM::VSTMDIA:
|
2010-09-10 18:25:35 +00:00
|
|
|
return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 8;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-16 01:16:36 +00:00
|
|
|
static unsigned getUpdatingLSMultipleOpcode(unsigned Opc,
|
|
|
|
ARM_AM::AMSubMode Mode) {
|
2010-03-13 01:08:20 +00:00
|
|
|
switch (Opc) {
|
|
|
|
default: llvm_unreachable("Unhandled opcode!");
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::LDMIA:
|
|
|
|
case ARM::LDMDA:
|
|
|
|
case ARM::LDMDB:
|
|
|
|
case ARM::LDMIB:
|
|
|
|
switch (Mode) {
|
|
|
|
default: llvm_unreachable("Unhandled submode!");
|
|
|
|
case ARM_AM::ia: return ARM::LDMIA_UPD;
|
|
|
|
case ARM_AM::ib: return ARM::LDMIB_UPD;
|
|
|
|
case ARM_AM::da: return ARM::LDMDA_UPD;
|
|
|
|
case ARM_AM::db: return ARM::LDMDB_UPD;
|
|
|
|
}
|
|
|
|
case ARM::STMIA:
|
|
|
|
case ARM::STMDA:
|
|
|
|
case ARM::STMDB:
|
|
|
|
case ARM::STMIB:
|
|
|
|
switch (Mode) {
|
|
|
|
default: llvm_unreachable("Unhandled submode!");
|
|
|
|
case ARM_AM::ia: return ARM::STMIA_UPD;
|
|
|
|
case ARM_AM::ib: return ARM::STMIB_UPD;
|
|
|
|
case ARM_AM::da: return ARM::STMDA_UPD;
|
|
|
|
case ARM_AM::db: return ARM::STMDB_UPD;
|
|
|
|
}
|
|
|
|
case ARM::t2LDMIA:
|
|
|
|
case ARM::t2LDMDB:
|
|
|
|
switch (Mode) {
|
|
|
|
default: llvm_unreachable("Unhandled submode!");
|
|
|
|
case ARM_AM::ia: return ARM::t2LDMIA_UPD;
|
|
|
|
case ARM_AM::db: return ARM::t2LDMDB_UPD;
|
|
|
|
}
|
|
|
|
case ARM::t2STMIA:
|
|
|
|
case ARM::t2STMDB:
|
|
|
|
switch (Mode) {
|
|
|
|
default: llvm_unreachable("Unhandled submode!");
|
|
|
|
case ARM_AM::ia: return ARM::t2STMIA_UPD;
|
|
|
|
case ARM_AM::db: return ARM::t2STMDB_UPD;
|
|
|
|
}
|
|
|
|
case ARM::VLDMSIA:
|
|
|
|
switch (Mode) {
|
|
|
|
default: llvm_unreachable("Unhandled submode!");
|
|
|
|
case ARM_AM::ia: return ARM::VLDMSIA_UPD;
|
|
|
|
case ARM_AM::db: return ARM::VLDMSDB_UPD;
|
|
|
|
}
|
|
|
|
case ARM::VLDMDIA:
|
|
|
|
switch (Mode) {
|
|
|
|
default: llvm_unreachable("Unhandled submode!");
|
|
|
|
case ARM_AM::ia: return ARM::VLDMDIA_UPD;
|
|
|
|
case ARM_AM::db: return ARM::VLDMDDB_UPD;
|
|
|
|
}
|
|
|
|
case ARM::VSTMSIA:
|
|
|
|
switch (Mode) {
|
|
|
|
default: llvm_unreachable("Unhandled submode!");
|
|
|
|
case ARM_AM::ia: return ARM::VSTMSIA_UPD;
|
|
|
|
case ARM_AM::db: return ARM::VSTMSDB_UPD;
|
|
|
|
}
|
|
|
|
case ARM::VSTMDIA:
|
|
|
|
switch (Mode) {
|
|
|
|
default: llvm_unreachable("Unhandled submode!");
|
|
|
|
case ARM_AM::ia: return ARM::VSTMDIA_UPD;
|
|
|
|
case ARM_AM::db: return ARM::VSTMDDB_UPD;
|
|
|
|
}
|
2010-03-13 01:08:20 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-07-09 23:11:34 +00:00
|
|
|
/// MergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base
|
2009-11-09 00:11:35 +00:00
|
|
|
/// register into the LDM/STM/VLDM{D|S}/VSTM{D|S} op when possible:
|
2007-01-19 07:51:42 +00:00
|
|
|
///
|
|
|
|
/// stmia rn, <ra, rb, rc>
|
|
|
|
/// rn := rn + 4 * 3;
|
|
|
|
/// =>
|
|
|
|
/// stmia rn!, <ra, rb, rc>
|
|
|
|
///
|
|
|
|
/// rn := rn - 4 * 3;
|
|
|
|
/// ldmia rn, <ra, rb, rc>
|
|
|
|
/// =>
|
|
|
|
/// ldmdb rn!, <ra, rb, rc>
|
2009-07-09 23:11:34 +00:00
|
|
|
bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MBBI,
|
|
|
|
bool &Advance,
|
|
|
|
MachineBasicBlock::iterator &I) {
|
2007-01-19 07:51:42 +00:00
|
|
|
MachineInstr *MI = MBBI;
|
|
|
|
unsigned Base = MI->getOperand(0).getReg();
|
2010-03-13 01:08:20 +00:00
|
|
|
bool BaseKill = MI->getOperand(0).isKill();
|
2007-01-19 07:51:42 +00:00
|
|
|
unsigned Bytes = getLSMultipleTransferSize(MI);
|
2007-07-05 07:18:20 +00:00
|
|
|
unsigned PredReg = 0;
|
2012-03-27 07:21:54 +00:00
|
|
|
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
2007-01-19 07:51:42 +00:00
|
|
|
int Opcode = MI->getOpcode();
|
2010-03-13 01:08:20 +00:00
|
|
|
DebugLoc dl = MI->getDebugLoc();
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2010-08-27 23:18:17 +00:00
|
|
|
// Can't use an updating ld/st if the base register is also a dest
|
|
|
|
// register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
|
2010-11-16 01:16:36 +00:00
|
|
|
for (unsigned i = 2, e = MI->getNumOperands(); i != e; ++i)
|
2010-08-27 23:18:17 +00:00
|
|
|
if (MI->getOperand(i).getReg() == Base)
|
|
|
|
return false;
|
2010-11-16 01:16:36 +00:00
|
|
|
|
|
|
|
bool DoMerge = false;
|
2010-11-17 05:31:09 +00:00
|
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(Opcode);
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2010-03-13 01:08:20 +00:00
|
|
|
// Try merging with the previous instruction.
|
2010-06-03 22:41:15 +00:00
|
|
|
MachineBasicBlock::iterator BeginMBBI = MBB.begin();
|
|
|
|
if (MBBI != BeginMBBI) {
|
2010-03-13 01:08:20 +00:00
|
|
|
MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
|
2010-06-03 22:41:15 +00:00
|
|
|
while (PrevMBBI != BeginMBBI && PrevMBBI->isDebugValue())
|
|
|
|
--PrevMBBI;
|
2010-08-27 23:18:17 +00:00
|
|
|
if (Mode == ARM_AM::ia &&
|
|
|
|
isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
|
|
|
|
Mode = ARM_AM::db;
|
|
|
|
DoMerge = true;
|
|
|
|
} else if (Mode == ARM_AM::ib &&
|
|
|
|
isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
|
|
|
|
Mode = ARM_AM::da;
|
|
|
|
DoMerge = true;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2010-03-13 01:08:20 +00:00
|
|
|
if (DoMerge)
|
|
|
|
MBB.erase(PrevMBBI);
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2010-03-13 01:08:20 +00:00
|
|
|
// Try merging with the next instruction.
|
2010-06-03 22:41:15 +00:00
|
|
|
MachineBasicBlock::iterator EndMBBI = MBB.end();
|
|
|
|
if (!DoMerge && MBBI != EndMBBI) {
|
2010-03-13 01:08:20 +00:00
|
|
|
MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
|
2010-06-03 22:41:15 +00:00
|
|
|
while (NextMBBI != EndMBBI && NextMBBI->isDebugValue())
|
|
|
|
++NextMBBI;
|
2010-08-27 23:18:17 +00:00
|
|
|
if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
|
|
|
|
isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
|
|
|
|
DoMerge = true;
|
|
|
|
} else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
|
|
|
|
isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
|
|
|
|
DoMerge = true;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2010-03-13 01:08:20 +00:00
|
|
|
if (DoMerge) {
|
|
|
|
if (NextMBBI == I) {
|
|
|
|
Advance = true;
|
|
|
|
++I;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2010-03-13 01:08:20 +00:00
|
|
|
MBB.erase(NextMBBI);
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-03-13 01:08:20 +00:00
|
|
|
if (!DoMerge)
|
|
|
|
return false;
|
|
|
|
|
2010-11-16 01:16:36 +00:00
|
|
|
unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
|
2010-03-13 01:08:20 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
|
|
|
|
.addReg(Base, getDefRegState(true)) // WB base register
|
2010-08-27 23:18:17 +00:00
|
|
|
.addReg(Base, getKillRegState(BaseKill))
|
|
|
|
.addImm(Pred).addReg(PredReg);
|
2010-11-16 01:16:36 +00:00
|
|
|
|
2010-03-13 01:08:20 +00:00
|
|
|
// Transfer the rest of operands.
|
2010-11-16 01:16:36 +00:00
|
|
|
for (unsigned OpNum = 3, e = MI->getNumOperands(); OpNum != e; ++OpNum)
|
2010-03-13 01:08:20 +00:00
|
|
|
MIB.addOperand(MI->getOperand(OpNum));
|
2010-11-16 01:16:36 +00:00
|
|
|
|
2010-03-13 01:08:20 +00:00
|
|
|
// Transfer memoperands.
|
2011-04-29 05:24:29 +00:00
|
|
|
MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
|
2010-03-13 01:08:20 +00:00
|
|
|
|
|
|
|
MBB.erase(MBBI);
|
|
|
|
return true;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2010-11-16 01:16:36 +00:00
|
|
|
static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc,
|
|
|
|
ARM_AM::AddrOpc Mode) {
|
2007-01-19 07:51:42 +00:00
|
|
|
switch (Opc) {
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::LDRi12:
|
2011-08-26 20:43:14 +00:00
|
|
|
return ARM::LDR_PRE_IMM;
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::STRi12:
|
2011-07-26 20:54:26 +00:00
|
|
|
return ARM::STR_PRE_IMM;
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::VLDRS:
|
|
|
|
return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD;
|
|
|
|
case ARM::VLDRD:
|
|
|
|
return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD;
|
|
|
|
case ARM::VSTRS:
|
|
|
|
return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD;
|
|
|
|
case ARM::VSTRD:
|
|
|
|
return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD;
|
2009-07-09 23:11:34 +00:00
|
|
|
case ARM::t2LDRi8:
|
|
|
|
case ARM::t2LDRi12:
|
|
|
|
return ARM::t2LDR_PRE;
|
|
|
|
case ARM::t2STRi8:
|
|
|
|
case ARM::t2STRi12:
|
|
|
|
return ARM::t2STR_PRE;
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unhandled opcode!");
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-16 01:16:36 +00:00
|
|
|
static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc,
|
|
|
|
ARM_AM::AddrOpc Mode) {
|
2007-01-19 07:51:42 +00:00
|
|
|
switch (Opc) {
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::LDRi12:
|
2011-07-26 20:54:26 +00:00
|
|
|
return ARM::LDR_POST_IMM;
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::STRi12:
|
2011-07-26 20:54:26 +00:00
|
|
|
return ARM::STR_POST_IMM;
|
2010-11-16 01:16:36 +00:00
|
|
|
case ARM::VLDRS:
|
|
|
|
return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD;
|
|
|
|
case ARM::VLDRD:
|
|
|
|
return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD;
|
|
|
|
case ARM::VSTRS:
|
|
|
|
return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD;
|
|
|
|
case ARM::VSTRD:
|
|
|
|
return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD;
|
2009-07-09 23:11:34 +00:00
|
|
|
case ARM::t2LDRi8:
|
|
|
|
case ARM::t2LDRi12:
|
|
|
|
return ARM::t2LDR_POST;
|
|
|
|
case ARM::t2STRi8:
|
|
|
|
case ARM::t2STRi12:
|
|
|
|
return ARM::t2STR_POST;
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unhandled opcode!");
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-07-09 23:11:34 +00:00
|
|
|
/// MergeBaseUpdateLoadStore - Fold proceeding/trailing inc/dec of base
|
2007-01-19 07:51:42 +00:00
|
|
|
/// register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible:
|
2009-07-09 23:11:34 +00:00
|
|
|
bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MBBI,
|
|
|
|
const TargetInstrInfo *TII,
|
|
|
|
bool &Advance,
|
|
|
|
MachineBasicBlock::iterator &I) {
|
2007-01-19 07:51:42 +00:00
|
|
|
MachineInstr *MI = MBBI;
|
|
|
|
unsigned Base = MI->getOperand(1).getReg();
|
2007-03-06 21:59:20 +00:00
|
|
|
bool BaseKill = MI->getOperand(1).isKill();
|
2007-01-19 07:51:42 +00:00
|
|
|
unsigned Bytes = getLSMultipleTransferSize(MI);
|
|
|
|
int Opcode = MI->getOpcode();
|
2009-02-13 02:25:56 +00:00
|
|
|
DebugLoc dl = MI->getDebugLoc();
|
2010-03-12 22:50:09 +00:00
|
|
|
bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
|
|
|
|
Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
|
2010-10-27 23:12:14 +00:00
|
|
|
bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);
|
|
|
|
if (isi32Load(Opcode) || isi32Store(Opcode))
|
2010-10-26 22:37:02 +00:00
|
|
|
if (MI->getOperand(2).getImm() != 0)
|
|
|
|
return false;
|
2010-03-12 22:50:09 +00:00
|
|
|
if (isAM5 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
|
2007-01-19 07:51:42 +00:00
|
|
|
return false;
|
|
|
|
|
2009-11-09 00:11:35 +00:00
|
|
|
bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
|
2007-01-19 07:51:42 +00:00
|
|
|
// Can't do the merge if the destination register is the same as the would-be
|
|
|
|
// writeback register.
|
|
|
|
if (isLd && MI->getOperand(0).getReg() == Base)
|
|
|
|
return false;
|
|
|
|
|
2007-07-05 07:18:20 +00:00
|
|
|
unsigned PredReg = 0;
|
2012-03-27 07:21:54 +00:00
|
|
|
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
2007-01-19 07:51:42 +00:00
|
|
|
bool DoMerge = false;
|
|
|
|
ARM_AM::AddrOpc AddSub = ARM_AM::add;
|
|
|
|
unsigned NewOpc = 0;
|
2009-08-04 01:43:45 +00:00
|
|
|
// AM2 - 12 bits, thumb2 - 8 bits.
|
|
|
|
unsigned Limit = isAM5 ? 0 : (isAM2 ? 0x1000 : 0x100);
|
2010-03-12 22:50:09 +00:00
|
|
|
|
|
|
|
// Try merging with the previous instruction.
|
2010-06-03 22:41:15 +00:00
|
|
|
MachineBasicBlock::iterator BeginMBBI = MBB.begin();
|
|
|
|
if (MBBI != BeginMBBI) {
|
2007-01-19 07:51:42 +00:00
|
|
|
MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
|
2010-06-03 22:41:15 +00:00
|
|
|
while (PrevMBBI != BeginMBBI && PrevMBBI->isDebugValue())
|
|
|
|
--PrevMBBI;
|
2009-08-04 01:43:45 +00:00
|
|
|
if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) {
|
2007-01-19 07:51:42 +00:00
|
|
|
DoMerge = true;
|
|
|
|
AddSub = ARM_AM::sub;
|
2009-08-04 01:43:45 +00:00
|
|
|
} else if (!isAM5 &&
|
|
|
|
isMatchingIncrement(PrevMBBI, Base, Bytes, Limit,Pred,PredReg)) {
|
2007-01-19 07:51:42 +00:00
|
|
|
DoMerge = true;
|
|
|
|
}
|
2010-03-12 22:50:09 +00:00
|
|
|
if (DoMerge) {
|
2010-11-16 01:16:36 +00:00
|
|
|
NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
|
2007-01-19 07:51:42 +00:00
|
|
|
MBB.erase(PrevMBBI);
|
2010-03-12 22:50:09 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2010-03-12 22:50:09 +00:00
|
|
|
// Try merging with the next instruction.
|
2010-06-08 22:53:32 +00:00
|
|
|
MachineBasicBlock::iterator EndMBBI = MBB.end();
|
2010-06-03 22:41:15 +00:00
|
|
|
if (!DoMerge && MBBI != EndMBBI) {
|
2009-12-03 00:50:42 +00:00
|
|
|
MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
|
2010-06-03 22:41:15 +00:00
|
|
|
while (NextMBBI != EndMBBI && NextMBBI->isDebugValue())
|
|
|
|
++NextMBBI;
|
2009-08-04 01:43:45 +00:00
|
|
|
if (!isAM5 &&
|
|
|
|
isMatchingDecrement(NextMBBI, Base, Bytes, Limit, Pred, PredReg)) {
|
2007-01-19 07:51:42 +00:00
|
|
|
DoMerge = true;
|
|
|
|
AddSub = ARM_AM::sub;
|
2009-08-04 01:43:45 +00:00
|
|
|
} else if (isMatchingIncrement(NextMBBI, Base, Bytes, Limit,Pred,PredReg)) {
|
2007-01-19 07:51:42 +00:00
|
|
|
DoMerge = true;
|
|
|
|
}
|
2007-09-19 21:48:07 +00:00
|
|
|
if (DoMerge) {
|
2010-11-16 01:16:36 +00:00
|
|
|
NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
|
2007-09-19 21:48:07 +00:00
|
|
|
if (NextMBBI == I) {
|
|
|
|
Advance = true;
|
|
|
|
++I;
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
MBB.erase(NextMBBI);
|
2007-09-19 21:48:07 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!DoMerge)
|
|
|
|
return false;
|
|
|
|
|
2010-03-13 00:43:32 +00:00
|
|
|
if (isAM5) {
|
2010-03-13 01:08:20 +00:00
|
|
|
// VLDM[SD}_UPD, VSTM[SD]_UPD
|
2010-08-27 23:18:17 +00:00
|
|
|
// (There are no base-updating versions of VLDR/VSTR instructions, but the
|
|
|
|
// updating load/store-multiple instructions can be used with only one
|
|
|
|
// register.)
|
2010-03-13 00:43:32 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(0);
|
|
|
|
BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
|
2010-03-13 01:08:20 +00:00
|
|
|
.addReg(Base, getDefRegState(true)) // WB base register
|
2010-03-13 00:43:32 +00:00
|
|
|
.addReg(Base, getKillRegState(isLd ? BaseKill : false))
|
|
|
|
.addImm(Pred).addReg(PredReg)
|
|
|
|
.addReg(MO.getReg(), (isLd ? getDefRegState(true) :
|
|
|
|
getKillRegState(MO.isKill())));
|
|
|
|
} else if (isLd) {
|
2011-08-12 22:20:41 +00:00
|
|
|
if (isAM2) {
|
2011-08-29 17:59:41 +00:00
|
|
|
// LDR_PRE, LDR_POST
|
|
|
|
if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
|
2011-08-29 21:14:19 +00:00
|
|
|
int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
|
2011-08-29 17:59:41 +00:00
|
|
|
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
|
|
|
|
.addReg(Base, RegState::Define)
|
|
|
|
.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
|
|
|
|
} else {
|
2011-08-29 21:14:19 +00:00
|
|
|
int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
|
2011-08-29 17:59:41 +00:00
|
|
|
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
|
|
|
|
.addReg(Base, RegState::Define)
|
|
|
|
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
|
|
|
|
}
|
2011-08-12 22:20:41 +00:00
|
|
|
} else {
|
|
|
|
int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
|
2009-08-04 01:43:45 +00:00
|
|
|
// t2LDR_PRE, t2LDR_POST
|
|
|
|
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
|
|
|
|
.addReg(Base, RegState::Define)
|
|
|
|
.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
|
2011-08-12 22:20:41 +00:00
|
|
|
}
|
2009-08-04 01:43:45 +00:00
|
|
|
} else {
|
|
|
|
MachineOperand &MO = MI->getOperand(0);
|
2011-08-05 20:35:44 +00:00
|
|
|
// FIXME: post-indexed stores use am2offset_imm, which still encodes
|
|
|
|
// the vestigal zero-reg offset register. When that's fixed, this clause
|
|
|
|
// can be removed entirely.
|
2011-08-12 22:20:41 +00:00
|
|
|
if (isAM2 && NewOpc == ARM::STR_POST_IMM) {
|
|
|
|
int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
|
2009-08-04 01:43:45 +00:00
|
|
|
// STR_PRE, STR_POST
|
|
|
|
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
|
|
|
|
.addReg(MO.getReg(), getKillRegState(MO.isKill()))
|
|
|
|
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
|
2011-08-12 22:20:41 +00:00
|
|
|
} else {
|
|
|
|
int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
|
2009-08-04 01:43:45 +00:00
|
|
|
// t2STR_PRE, t2STR_POST
|
|
|
|
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
|
|
|
|
.addReg(MO.getReg(), getKillRegState(MO.isKill()))
|
|
|
|
.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
|
2011-08-12 22:20:41 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
MBB.erase(MBBI);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-05-25 21:19:19 +00:00
|
|
|
/// isMemoryOp - Returns true if instruction is a memory operation that this
|
|
|
|
/// pass is capable of operating on.
|
2009-07-09 23:11:34 +00:00
|
|
|
static bool isMemoryOp(const MachineInstr *MI) {
|
2010-06-29 01:13:07 +00:00
|
|
|
// When no memory operands are present, conservatively assume unaligned,
|
|
|
|
// volatile, unfoldable.
|
|
|
|
if (!MI->hasOneMemOperand())
|
|
|
|
return false;
|
2010-01-14 00:54:10 +00:00
|
|
|
|
2010-06-29 01:13:07 +00:00
|
|
|
const MachineMemOperand *MMO = *MI->memoperands_begin();
|
2010-01-14 00:54:10 +00:00
|
|
|
|
2010-06-29 01:13:07 +00:00
|
|
|
// Don't touch volatile memory accesses - we may be changing their order.
|
|
|
|
if (MMO->isVolatile())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Unaligned ldr/str is emulated by some kernels, but unaligned ldm/stm is
|
|
|
|
// not.
|
|
|
|
if (MMO->getAlignment() < 4)
|
|
|
|
return false;
|
2010-01-14 00:54:10 +00:00
|
|
|
|
2010-02-24 18:57:08 +00:00
|
|
|
// str <undef> could probably be eliminated entirely, but for now we just want
|
|
|
|
// to avoid making a mess of it.
|
|
|
|
// FIXME: Use str <undef> as a wildcard to enable better stm folding.
|
|
|
|
if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg() &&
|
|
|
|
MI->getOperand(0).isUndef())
|
|
|
|
return false;
|
|
|
|
|
2010-03-04 21:04:38 +00:00
|
|
|
// Likewise don't mess with references to undefined addresses.
|
|
|
|
if (MI->getNumOperands() > 1 && MI->getOperand(1).isReg() &&
|
|
|
|
MI->getOperand(1).isUndef())
|
|
|
|
return false;
|
|
|
|
|
2007-03-06 18:02:41 +00:00
|
|
|
int Opcode = MI->getOpcode();
|
|
|
|
switch (Opcode) {
|
|
|
|
default: break;
|
2009-11-09 00:11:35 +00:00
|
|
|
case ARM::VLDRS:
|
|
|
|
case ARM::VSTRS:
|
2008-10-03 15:45:36 +00:00
|
|
|
return MI->getOperand(1).isReg();
|
2009-11-09 00:11:35 +00:00
|
|
|
case ARM::VLDRD:
|
|
|
|
case ARM::VSTRD:
|
2008-10-03 15:45:36 +00:00
|
|
|
return MI->getOperand(1).isReg();
|
2010-10-26 22:37:02 +00:00
|
|
|
case ARM::LDRi12:
|
2010-10-27 23:12:14 +00:00
|
|
|
case ARM::STRi12:
|
2009-07-09 23:11:34 +00:00
|
|
|
case ARM::t2LDRi8:
|
|
|
|
case ARM::t2LDRi12:
|
|
|
|
case ARM::t2STRi8:
|
|
|
|
case ARM::t2STRi12:
|
2009-09-27 09:46:04 +00:00
|
|
|
return MI->getOperand(1).isReg();
|
2007-03-06 18:02:41 +00:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-03-08 02:55:08 +00:00
|
|
|
/// AdvanceRS - Advance register scavenger to just before the earliest memory
|
|
|
|
/// op that is being merged.
|
|
|
|
void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) {
|
|
|
|
MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
|
|
|
|
unsigned Position = MemOps[0].Position;
|
|
|
|
for (unsigned i = 1, e = MemOps.size(); i != e; ++i) {
|
|
|
|
if (MemOps[i].Position < Position) {
|
|
|
|
Position = MemOps[i].Position;
|
|
|
|
Loc = MemOps[i].MBBI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Loc != MBB.begin())
|
|
|
|
RS->forward(prior(Loc));
|
|
|
|
}
|
|
|
|
|
2009-06-13 09:12:55 +00:00
|
|
|
static int getMemoryOpOffset(const MachineInstr *MI) {
|
|
|
|
int Opcode = MI->getOpcode();
|
2009-06-15 08:28:29 +00:00
|
|
|
bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
|
2009-06-13 09:12:55 +00:00
|
|
|
unsigned NumOperands = MI->getDesc().getNumOperands();
|
|
|
|
unsigned OffField = MI->getOperand(NumOperands-3).getImm();
|
2009-07-09 23:11:34 +00:00
|
|
|
|
|
|
|
if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
|
|
|
|
Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
|
2010-10-26 22:37:02 +00:00
|
|
|
Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
|
2010-10-27 23:12:14 +00:00
|
|
|
Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
|
2009-07-09 23:11:34 +00:00
|
|
|
return OffField;
|
|
|
|
|
2010-10-27 23:12:14 +00:00
|
|
|
int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField)
|
|
|
|
: ARM_AM::getAM5Offset(OffField) * 4;
|
|
|
|
if (isAM3) {
|
2009-06-15 08:28:29 +00:00
|
|
|
if (ARM_AM::getAM3Op(OffField) == ARM_AM::sub)
|
|
|
|
Offset = -Offset;
|
2009-06-13 09:12:55 +00:00
|
|
|
} else {
|
|
|
|
if (ARM_AM::getAM5Op(OffField) == ARM_AM::sub)
|
|
|
|
Offset = -Offset;
|
|
|
|
}
|
|
|
|
return Offset;
|
|
|
|
}
|
|
|
|
|
2009-06-15 08:28:29 +00:00
|
|
|
static void InsertLDR_STR(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MBBI,
|
2010-10-27 23:12:14 +00:00
|
|
|
int Offset, bool isDef,
|
2009-06-15 08:28:29 +00:00
|
|
|
DebugLoc dl, unsigned NewOpc,
|
2009-09-27 09:46:04 +00:00
|
|
|
unsigned Reg, bool RegDeadKill, bool RegUndef,
|
|
|
|
unsigned BaseReg, bool BaseKill, bool BaseUndef,
|
2010-10-27 23:12:14 +00:00
|
|
|
bool OffKill, bool OffUndef,
|
2009-06-15 08:28:29 +00:00
|
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
2009-09-27 09:46:04 +00:00
|
|
|
const TargetInstrInfo *TII, bool isT2) {
|
|
|
|
if (isDef) {
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
|
|
|
|
TII->get(NewOpc))
|
2009-06-19 01:59:04 +00:00
|
|
|
.addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
|
2009-09-27 09:46:04 +00:00
|
|
|
.addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
|
|
|
|
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
|
|
|
|
} else {
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
|
|
|
|
TII->get(NewOpc))
|
|
|
|
.addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
|
|
|
|
.addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
|
|
|
|
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
|
|
|
|
}
|
2009-06-15 08:28:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MBBI) {
|
|
|
|
MachineInstr *MI = &*MBBI;
|
|
|
|
unsigned Opcode = MI->getOpcode();
|
2009-09-27 09:46:04 +00:00
|
|
|
if (Opcode == ARM::LDRD || Opcode == ARM::STRD ||
|
|
|
|
Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) {
|
2011-11-08 21:21:09 +00:00
|
|
|
const MachineOperand &BaseOp = MI->getOperand(2);
|
|
|
|
unsigned BaseReg = BaseOp.getReg();
|
2009-06-15 08:28:29 +00:00
|
|
|
unsigned EvenReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned OddReg = MI->getOperand(1).getReg();
|
|
|
|
unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
|
|
|
|
unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
|
2011-11-08 21:21:09 +00:00
|
|
|
// ARM errata 602117: LDRD with base in list may result in incorrect base
|
|
|
|
// register when interrupted or faulted.
|
2011-11-09 01:57:03 +00:00
|
|
|
bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3();
|
2011-11-08 21:21:09 +00:00
|
|
|
if (!Errata602117 &&
|
|
|
|
((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum))
|
2009-06-15 08:28:29 +00:00
|
|
|
return false;
|
|
|
|
|
2010-06-21 21:21:14 +00:00
|
|
|
MachineBasicBlock::iterator NewBBI = MBBI;
|
2009-09-27 09:46:04 +00:00
|
|
|
bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
|
|
|
|
bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
|
2009-06-19 01:59:04 +00:00
|
|
|
bool EvenDeadKill = isLd ?
|
|
|
|
MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
|
2009-09-27 09:46:04 +00:00
|
|
|
bool EvenUndef = MI->getOperand(0).isUndef();
|
2009-06-19 01:59:04 +00:00
|
|
|
bool OddDeadKill = isLd ?
|
|
|
|
MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
|
2009-09-27 09:46:04 +00:00
|
|
|
bool OddUndef = MI->getOperand(1).isUndef();
|
2009-06-15 08:28:29 +00:00
|
|
|
bool BaseKill = BaseOp.isKill();
|
2009-09-27 09:46:04 +00:00
|
|
|
bool BaseUndef = BaseOp.isUndef();
|
|
|
|
bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
|
|
|
|
bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
|
2009-06-15 08:28:29 +00:00
|
|
|
int OffImm = getMemoryOpOffset(MI);
|
|
|
|
unsigned PredReg = 0;
|
2012-03-27 07:21:54 +00:00
|
|
|
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
2009-06-15 08:28:29 +00:00
|
|
|
|
2010-10-27 23:12:14 +00:00
|
|
|
if (OddRegNum > EvenRegNum && OffImm == 0) {
|
2009-06-15 08:28:29 +00:00
|
|
|
// Ascending register numbers and no offset. It's safe to change it to a
|
|
|
|
// ldm or stm.
|
2009-09-27 09:46:04 +00:00
|
|
|
unsigned NewOpc = (isLd)
|
2010-11-16 01:16:36 +00:00
|
|
|
? (isT2 ? ARM::t2LDMIA : ARM::LDMIA)
|
|
|
|
: (isT2 ? ARM::t2STMIA : ARM::STMIA);
|
2009-06-18 02:04:01 +00:00
|
|
|
if (isLd) {
|
|
|
|
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
|
|
|
|
.addReg(BaseReg, getKillRegState(BaseKill))
|
|
|
|
.addImm(Pred).addReg(PredReg)
|
2009-06-19 01:59:04 +00:00
|
|
|
.addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
|
2009-10-01 01:33:39 +00:00
|
|
|
.addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
|
2009-06-18 02:04:01 +00:00
|
|
|
++NumLDRD2LDM;
|
|
|
|
} else {
|
|
|
|
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
|
|
|
|
.addReg(BaseReg, getKillRegState(BaseKill))
|
|
|
|
.addImm(Pred).addReg(PredReg)
|
2009-09-27 09:46:04 +00:00
|
|
|
.addReg(EvenReg,
|
|
|
|
getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
|
|
|
|
.addReg(OddReg,
|
2009-10-01 01:33:39 +00:00
|
|
|
getKillRegState(OddDeadKill) | getUndefRegState(OddUndef));
|
2009-06-18 02:04:01 +00:00
|
|
|
++NumSTRD2STM;
|
|
|
|
}
|
2010-06-21 21:21:14 +00:00
|
|
|
NewBBI = llvm::prior(MBBI);
|
2009-06-15 08:28:29 +00:00
|
|
|
} else {
|
|
|
|
// Split into two instructions.
|
2009-09-27 09:46:04 +00:00
|
|
|
unsigned NewOpc = (isLd)
|
2010-10-26 22:37:02 +00:00
|
|
|
? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
|
2010-10-27 23:12:14 +00:00
|
|
|
: (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
|
2009-06-15 08:28:29 +00:00
|
|
|
DebugLoc dl = MBBI->getDebugLoc();
|
|
|
|
// If this is a load and base register is killed, it may have been
|
|
|
|
// re-defed by the load, make sure the first load does not clobber it.
|
2009-06-18 02:04:01 +00:00
|
|
|
if (isLd &&
|
2009-06-15 08:28:29 +00:00
|
|
|
(BaseKill || OffKill) &&
|
2010-10-27 23:12:14 +00:00
|
|
|
(TRI->regsOverlap(EvenReg, BaseReg))) {
|
|
|
|
assert(!TRI->regsOverlap(OddReg, BaseReg));
|
2009-09-27 09:46:04 +00:00
|
|
|
InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
|
|
|
|
OddReg, OddDeadKill, false,
|
2010-10-27 23:12:14 +00:00
|
|
|
BaseReg, false, BaseUndef, false, OffUndef,
|
2009-09-27 09:46:04 +00:00
|
|
|
Pred, PredReg, TII, isT2);
|
2010-06-21 21:21:14 +00:00
|
|
|
NewBBI = llvm::prior(MBBI);
|
2009-09-27 09:46:04 +00:00
|
|
|
InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
|
|
|
|
EvenReg, EvenDeadKill, false,
|
2010-10-27 23:12:14 +00:00
|
|
|
BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
|
2009-09-27 09:46:04 +00:00
|
|
|
Pred, PredReg, TII, isT2);
|
2009-06-15 08:28:29 +00:00
|
|
|
} else {
|
2009-11-14 01:50:00 +00:00
|
|
|
if (OddReg == EvenReg && EvenDeadKill) {
|
2010-06-02 21:53:11 +00:00
|
|
|
// If the two source operands are the same, the kill marker is
|
|
|
|
// probably on the first one. e.g.
|
2009-11-14 01:50:00 +00:00
|
|
|
// t2STRDi8 %R5<kill>, %R5, %R9<kill>, 0, 14, %reg0
|
|
|
|
EvenDeadKill = false;
|
|
|
|
OddDeadKill = true;
|
|
|
|
}
|
2009-06-19 01:59:04 +00:00
|
|
|
InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
|
2009-09-27 09:46:04 +00:00
|
|
|
EvenReg, EvenDeadKill, EvenUndef,
|
2010-10-27 23:12:14 +00:00
|
|
|
BaseReg, false, BaseUndef, false, OffUndef,
|
2009-09-27 09:46:04 +00:00
|
|
|
Pred, PredReg, TII, isT2);
|
2010-06-21 21:21:14 +00:00
|
|
|
NewBBI = llvm::prior(MBBI);
|
2009-06-19 01:59:04 +00:00
|
|
|
InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
|
2009-09-27 09:46:04 +00:00
|
|
|
OddReg, OddDeadKill, OddUndef,
|
2010-10-27 23:12:14 +00:00
|
|
|
BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
|
2009-09-27 09:46:04 +00:00
|
|
|
Pred, PredReg, TII, isT2);
|
2009-06-15 08:28:29 +00:00
|
|
|
}
|
2009-06-18 02:04:01 +00:00
|
|
|
if (isLd)
|
|
|
|
++NumLDRD2LDR;
|
|
|
|
else
|
|
|
|
++NumSTRD2STR;
|
2009-06-15 08:28:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MBB.erase(MI);
|
2010-06-21 21:21:14 +00:00
|
|
|
MBBI = NewBBI;
|
|
|
|
return true;
|
2009-06-15 08:28:29 +00:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
/// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
|
|
|
|
/// ops of the same base and incrementing offset into LDM / STM ops.
|
|
|
|
bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
|
|
|
unsigned NumMerges = 0;
|
|
|
|
unsigned NumMemOps = 0;
|
|
|
|
MemOpQueue MemOps;
|
|
|
|
unsigned CurrBase = 0;
|
|
|
|
int CurrOpc = -1;
|
|
|
|
unsigned CurrSize = 0;
|
2007-05-15 01:29:07 +00:00
|
|
|
ARMCC::CondCodes CurrPred = ARMCC::AL;
|
2007-07-05 07:18:20 +00:00
|
|
|
unsigned CurrPredReg = 0;
|
2007-01-19 07:51:42 +00:00
|
|
|
unsigned Position = 0;
|
2009-06-05 17:56:14 +00:00
|
|
|
SmallVector<MachineBasicBlock::iterator,4> Merges;
|
2007-03-06 18:02:41 +00:00
|
|
|
|
2007-03-07 02:38:05 +00:00
|
|
|
RS->enterBasicBlock(&MBB);
|
2007-01-19 07:51:42 +00:00
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
|
|
|
while (MBBI != E) {
|
2009-06-15 08:28:29 +00:00
|
|
|
if (FixInvalidRegPairOp(MBB, MBBI))
|
|
|
|
continue;
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
bool Advance = false;
|
|
|
|
bool TryMerge = false;
|
|
|
|
bool Clobber = false;
|
|
|
|
|
2007-03-06 18:02:41 +00:00
|
|
|
bool isMemOp = isMemoryOp(MBBI);
|
2007-01-19 07:51:42 +00:00
|
|
|
if (isMemOp) {
|
2007-03-06 18:02:41 +00:00
|
|
|
int Opcode = MBBI->getOpcode();
|
|
|
|
unsigned Size = getLSMultipleTransferSize(MBBI);
|
2010-06-21 21:21:14 +00:00
|
|
|
const MachineOperand &MO = MBBI->getOperand(0);
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
bool isKill = MO.isDef() ? false : MO.isKill();
|
2007-01-19 07:51:42 +00:00
|
|
|
unsigned Base = MBBI->getOperand(1).getReg();
|
2007-07-05 07:18:20 +00:00
|
|
|
unsigned PredReg = 0;
|
2012-03-27 07:21:54 +00:00
|
|
|
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
|
2009-06-13 09:12:55 +00:00
|
|
|
int Offset = getMemoryOpOffset(MBBI);
|
2007-01-19 07:51:42 +00:00
|
|
|
// Watch out for:
|
|
|
|
// r4 := ldr [r5]
|
|
|
|
// r5 := ldr [r5, #4]
|
|
|
|
// r6 := ldr [r5, #8]
|
|
|
|
//
|
|
|
|
// The second ldr has effectively broken the chain even though it
|
|
|
|
// looks like the later ldr(s) use the same base register. Try to
|
|
|
|
// merge the ldr's so far, including this one. But don't try to
|
|
|
|
// combine the following ldr(s).
|
2009-07-09 23:11:34 +00:00
|
|
|
Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg());
|
2007-01-19 07:51:42 +00:00
|
|
|
if (CurrBase == 0 && !Clobber) {
|
|
|
|
// Start of a new chain.
|
|
|
|
CurrBase = Base;
|
|
|
|
CurrOpc = Opcode;
|
|
|
|
CurrSize = Size;
|
2007-05-15 01:29:07 +00:00
|
|
|
CurrPred = Pred;
|
2007-07-05 07:18:20 +00:00
|
|
|
CurrPredReg = PredReg;
|
2010-06-21 21:21:14 +00:00
|
|
|
MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill, Position, MBBI));
|
2010-06-22 15:08:57 +00:00
|
|
|
++NumMemOps;
|
2007-01-19 07:51:42 +00:00
|
|
|
Advance = true;
|
|
|
|
} else {
|
|
|
|
if (Clobber) {
|
|
|
|
TryMerge = true;
|
|
|
|
Advance = true;
|
|
|
|
}
|
|
|
|
|
2007-05-15 01:29:07 +00:00
|
|
|
if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
|
2007-07-05 07:18:20 +00:00
|
|
|
// No need to match PredReg.
|
2007-01-19 07:51:42 +00:00
|
|
|
// Continue adding to the queue.
|
|
|
|
if (Offset > MemOps.back().Offset) {
|
2010-06-21 21:21:14 +00:00
|
|
|
MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill,
|
|
|
|
Position, MBBI));
|
2010-06-22 15:08:57 +00:00
|
|
|
++NumMemOps;
|
2007-01-19 07:51:42 +00:00
|
|
|
Advance = true;
|
|
|
|
} else {
|
|
|
|
for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
if (Offset < I->Offset) {
|
2010-06-21 21:21:14 +00:00
|
|
|
MemOps.insert(I, MemOpQueueEntry(Offset, Reg, isKill,
|
|
|
|
Position, MBBI));
|
2010-06-22 15:08:57 +00:00
|
|
|
++NumMemOps;
|
2007-01-19 07:51:42 +00:00
|
|
|
Advance = true;
|
|
|
|
break;
|
|
|
|
} else if (Offset == I->Offset) {
|
|
|
|
// Collision! This can't be merged!
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-06-09 22:21:24 +00:00
|
|
|
if (MBBI->isDebugValue()) {
|
|
|
|
++MBBI;
|
|
|
|
if (MBBI == E)
|
|
|
|
// Reach the end of the block, try merging the memory instructions.
|
|
|
|
TryMerge = true;
|
|
|
|
} else if (Advance) {
|
2007-01-19 07:51:42 +00:00
|
|
|
++Position;
|
|
|
|
++MBBI;
|
2009-10-22 06:47:35 +00:00
|
|
|
if (MBBI == E)
|
|
|
|
// Reach the end of the block, try merging the memory instructions.
|
|
|
|
TryMerge = true;
|
2007-01-19 07:51:42 +00:00
|
|
|
} else
|
|
|
|
TryMerge = true;
|
|
|
|
|
|
|
|
if (TryMerge) {
|
|
|
|
if (NumMemOps > 1) {
|
2007-03-07 02:38:05 +00:00
|
|
|
// Try to find a free register to use as a new base in case it's needed.
|
|
|
|
// First advance to the instruction just before the start of the chain.
|
2007-03-08 02:55:08 +00:00
|
|
|
AdvanceRS(MBB, MemOps);
|
2009-08-18 21:14:54 +00:00
|
|
|
// Find a scratch register.
|
2009-09-11 19:49:06 +00:00
|
|
|
unsigned Scratch = RS->FindUnusedReg(ARM::GPRRegisterClass);
|
2007-03-07 02:38:05 +00:00
|
|
|
// Process the load / store instructions.
|
|
|
|
RS->forward(prior(MBBI));
|
|
|
|
|
|
|
|
// Merge ops.
|
2009-06-05 17:56:14 +00:00
|
|
|
Merges.clear();
|
|
|
|
MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize,
|
|
|
|
CurrPred, CurrPredReg, Scratch, MemOps, Merges);
|
2007-03-07 02:38:05 +00:00
|
|
|
|
2011-04-15 05:18:47 +00:00
|
|
|
// Try folding preceding/trailing base inc/dec into the generated
|
2007-01-19 07:51:42 +00:00
|
|
|
// LDM/STM ops.
|
2009-06-05 17:56:14 +00:00
|
|
|
for (unsigned i = 0, e = Merges.size(); i < e; ++i)
|
2009-07-09 23:11:34 +00:00
|
|
|
if (MergeBaseUpdateLSMultiple(MBB, Merges[i], Advance, MBBI))
|
2009-06-03 06:14:58 +00:00
|
|
|
++NumMerges;
|
2009-06-05 17:56:14 +00:00
|
|
|
NumMerges += Merges.size();
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2011-04-15 05:18:47 +00:00
|
|
|
// Try folding preceding/trailing base inc/dec into those load/store
|
2007-03-07 02:38:05 +00:00
|
|
|
// that were not merged to form LDM/STM ops.
|
|
|
|
for (unsigned i = 0; i != NumMemOps; ++i)
|
|
|
|
if (!MemOps[i].Merged)
|
2009-07-09 23:11:34 +00:00
|
|
|
if (MergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
|
2009-06-03 06:14:58 +00:00
|
|
|
++NumMerges;
|
2007-03-07 02:38:05 +00:00
|
|
|
|
2009-08-11 15:33:49 +00:00
|
|
|
// RS may be pointing to an instruction that's deleted.
|
2007-03-07 02:38:05 +00:00
|
|
|
RS->skipTo(prior(MBBI));
|
2009-06-04 01:15:28 +00:00
|
|
|
} else if (NumMemOps == 1) {
|
2011-04-15 05:18:47 +00:00
|
|
|
// Try folding preceding/trailing base inc/dec into the single
|
2009-06-04 01:15:28 +00:00
|
|
|
// load/store.
|
2009-07-09 23:11:34 +00:00
|
|
|
if (MergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) {
|
2009-06-04 01:15:28 +00:00
|
|
|
++NumMerges;
|
|
|
|
RS->forward(prior(MBBI));
|
|
|
|
}
|
2007-03-07 02:38:05 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
CurrBase = 0;
|
|
|
|
CurrOpc = -1;
|
2007-05-15 01:29:07 +00:00
|
|
|
CurrSize = 0;
|
|
|
|
CurrPred = ARMCC::AL;
|
2007-07-05 07:18:20 +00:00
|
|
|
CurrPredReg = 0;
|
2007-01-19 07:51:42 +00:00
|
|
|
if (NumMemOps) {
|
|
|
|
MemOps.clear();
|
|
|
|
NumMemOps = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If iterator hasn't been advanced and this is not a memory op, skip it.
|
|
|
|
// It can't start a new chain anyway.
|
|
|
|
if (!Advance && !isMemOp && MBBI != E) {
|
|
|
|
++Position;
|
|
|
|
++MBBI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return NumMerges > 0;
|
|
|
|
}
|
|
|
|
|
2010-03-20 22:20:40 +00:00
|
|
|
/// MergeReturnIntoLDM - If this is a exit BB, try merging the return ops
|
2011-04-15 05:18:47 +00:00
|
|
|
/// ("bx lr" and "mov pc, lr") into the preceding stack restore so it
|
2010-03-20 22:20:40 +00:00
|
|
|
/// directly restore the value of LR into pc.
|
|
|
|
/// ldmfd sp!, {..., lr}
|
2007-01-19 07:51:42 +00:00
|
|
|
/// bx lr
|
2010-03-20 22:20:40 +00:00
|
|
|
/// or
|
|
|
|
/// ldmfd sp!, {..., lr}
|
|
|
|
/// mov pc, lr
|
2007-01-19 07:51:42 +00:00
|
|
|
/// =>
|
2010-03-20 22:20:40 +00:00
|
|
|
/// ldmfd sp!, {..., pc}
|
2007-01-19 07:51:42 +00:00
|
|
|
bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
|
|
|
|
if (MBB.empty()) return false;
|
|
|
|
|
2011-01-13 22:47:43 +00:00
|
|
|
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
2009-07-09 23:11:34 +00:00
|
|
|
if (MBBI != MBB.begin() &&
|
2010-03-20 22:20:40 +00:00
|
|
|
(MBBI->getOpcode() == ARM::BX_RET ||
|
|
|
|
MBBI->getOpcode() == ARM::tBX_RET ||
|
|
|
|
MBBI->getOpcode() == ARM::MOVPCLR)) {
|
2007-01-19 07:51:42 +00:00
|
|
|
MachineInstr *PrevMI = prior(MBBI);
|
2010-11-16 01:16:36 +00:00
|
|
|
unsigned Opcode = PrevMI->getOpcode();
|
|
|
|
if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||
|
|
|
|
Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||
|
|
|
|
Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
|
2007-01-19 07:51:42 +00:00
|
|
|
MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1);
|
2009-08-04 01:43:45 +00:00
|
|
|
if (MO.getReg() != ARM::LR)
|
|
|
|
return false;
|
2010-11-16 01:16:36 +00:00
|
|
|
unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET);
|
|
|
|
assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||
|
|
|
|
Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
|
2009-08-04 01:43:45 +00:00
|
|
|
PrevMI->setDesc(TII->get(NewOpc));
|
|
|
|
MO.setReg(ARM::PC);
|
2010-10-22 21:29:58 +00:00
|
|
|
PrevMI->copyImplicitOps(&*MBBI);
|
2009-08-04 01:43:45 +00:00
|
|
|
MBB.erase(MBBI);
|
|
|
|
return true;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
|
2007-03-06 18:02:41 +00:00
|
|
|
const TargetMachine &TM = Fn.getTarget();
|
2007-03-07 20:30:36 +00:00
|
|
|
AFI = Fn.getInfo<ARMFunctionInfo>();
|
2007-03-06 18:02:41 +00:00
|
|
|
TII = TM.getInstrInfo();
|
2008-02-10 18:45:23 +00:00
|
|
|
TRI = TM.getRegisterInfo();
|
2011-11-08 21:21:09 +00:00
|
|
|
STI = &TM.getSubtarget<ARMSubtarget>();
|
2007-03-07 02:38:05 +00:00
|
|
|
RS = new RegScavenger();
|
2009-07-09 23:11:34 +00:00
|
|
|
isThumb2 = AFI->isThumb2Function();
|
2007-03-06 18:02:41 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
bool Modified = false;
|
|
|
|
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
|
|
|
|
++MFI) {
|
|
|
|
MachineBasicBlock &MBB = *MFI;
|
|
|
|
Modified |= LoadStoreMultipleOpti(MBB);
|
2011-01-06 19:24:41 +00:00
|
|
|
if (TM.getSubtarget<ARMSubtarget>().hasV5TOps())
|
|
|
|
Modified |= MergeReturnIntoLDM(MBB);
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2007-03-06 18:02:41 +00:00
|
|
|
|
|
|
|
delete RS;
|
2007-01-19 07:51:42 +00:00
|
|
|
return Modified;
|
|
|
|
}
|
2009-06-13 09:12:55 +00:00
|
|
|
|
|
|
|
|
|
|
|
/// ARMPreAllocLoadStoreOpt - Pre- register allocation pass that move
|
|
|
|
/// load / stores from consecutive locations close to make it more
|
|
|
|
/// likely they will be combined later.
|
|
|
|
|
|
|
|
namespace {
|
2009-10-25 06:33:48 +00:00
|
|
|
struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass{
|
2009-06-13 09:12:55 +00:00
|
|
|
static char ID;
|
2010-08-06 18:33:48 +00:00
|
|
|
ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
|
2009-06-13 09:12:55 +00:00
|
|
|
|
2009-06-15 08:28:29 +00:00
|
|
|
const TargetData *TD;
|
2009-06-13 09:12:55 +00:00
|
|
|
const TargetInstrInfo *TII;
|
|
|
|
const TargetRegisterInfo *TRI;
|
2009-06-15 08:28:29 +00:00
|
|
|
const ARMSubtarget *STI;
|
2009-06-13 09:12:55 +00:00
|
|
|
MachineRegisterInfo *MRI;
|
2009-09-25 21:44:53 +00:00
|
|
|
MachineFunction *MF;
|
2009-06-13 09:12:55 +00:00
|
|
|
|
|
|
|
virtual bool runOnMachineFunction(MachineFunction &Fn);
|
|
|
|
|
|
|
|
virtual const char *getPassName() const {
|
|
|
|
return "ARM pre- register allocation load / store optimization pass";
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
2009-06-15 20:54:56 +00:00
|
|
|
bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
|
|
|
|
unsigned &NewOpc, unsigned &EvenReg,
|
|
|
|
unsigned &OddReg, unsigned &BaseReg,
|
2010-10-27 23:12:14 +00:00
|
|
|
int &Offset,
|
2009-09-25 21:44:53 +00:00
|
|
|
unsigned &PredReg, ARMCC::CondCodes &Pred,
|
|
|
|
bool &isT2);
|
2009-06-13 09:12:55 +00:00
|
|
|
bool RescheduleOps(MachineBasicBlock *MBB,
|
|
|
|
SmallVector<MachineInstr*, 4> &Ops,
|
|
|
|
unsigned Base, bool isLd,
|
|
|
|
DenseMap<MachineInstr*, unsigned> &MI2LocMap);
|
|
|
|
bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
|
|
|
|
};
|
|
|
|
char ARMPreAllocLoadStoreOpt::ID = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
|
2009-06-15 08:28:29 +00:00
|
|
|
TD = Fn.getTarget().getTargetData();
|
2009-06-13 09:12:55 +00:00
|
|
|
TII = Fn.getTarget().getInstrInfo();
|
|
|
|
TRI = Fn.getTarget().getRegisterInfo();
|
2009-06-15 08:28:29 +00:00
|
|
|
STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
|
2009-06-13 09:12:55 +00:00
|
|
|
MRI = &Fn.getRegInfo();
|
2009-09-25 21:44:53 +00:00
|
|
|
MF = &Fn;
|
2009-06-13 09:12:55 +00:00
|
|
|
|
|
|
|
bool Modified = false;
|
|
|
|
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
|
|
|
|
++MFI)
|
|
|
|
Modified |= RescheduleLoadStoreInstrs(MFI);
|
|
|
|
|
|
|
|
return Modified;
|
|
|
|
}
|
|
|
|
|
2009-06-19 23:17:27 +00:00
|
|
|
static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
|
|
|
|
MachineBasicBlock::iterator I,
|
|
|
|
MachineBasicBlock::iterator E,
|
|
|
|
SmallPtrSet<MachineInstr*, 4> &MemOps,
|
|
|
|
SmallSet<unsigned, 4> &MemRegs,
|
|
|
|
const TargetRegisterInfo *TRI) {
|
2009-06-13 09:12:55 +00:00
|
|
|
// Are there stores / loads / calls between them?
|
|
|
|
// FIXME: This is overly conservative. We should make use of alias information
|
|
|
|
// some day.
|
2009-06-19 23:17:27 +00:00
|
|
|
SmallSet<unsigned, 4> AddedRegPressure;
|
2009-06-13 09:12:55 +00:00
|
|
|
while (++I != E) {
|
2010-06-04 01:23:30 +00:00
|
|
|
if (I->isDebugValue() || MemOps.count(&*I))
|
2009-06-19 23:17:27 +00:00
|
|
|
continue;
|
2011-12-07 07:15:52 +00:00
|
|
|
if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
|
2009-06-13 09:12:55 +00:00
|
|
|
return false;
|
2011-12-07 07:15:52 +00:00
|
|
|
if (isLd && I->mayStore())
|
2009-06-13 09:12:55 +00:00
|
|
|
return false;
|
|
|
|
if (!isLd) {
|
2011-12-07 07:15:52 +00:00
|
|
|
if (I->mayLoad())
|
2009-06-13 09:12:55 +00:00
|
|
|
return false;
|
|
|
|
// It's not safe to move the first 'str' down.
|
|
|
|
// str r1, [r0]
|
|
|
|
// strh r5, [r0]
|
|
|
|
// str r4, [r0, #+4]
|
2011-12-07 07:15:52 +00:00
|
|
|
if (I->mayStore())
|
2009-06-13 09:12:55 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {
|
|
|
|
MachineOperand &MO = I->getOperand(j);
|
2009-06-19 23:17:27 +00:00
|
|
|
if (!MO.isReg())
|
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (MO.isDef() && TRI->regsOverlap(Reg, Base))
|
2009-06-13 09:12:55 +00:00
|
|
|
return false;
|
2009-06-19 23:17:27 +00:00
|
|
|
if (Reg != Base && !MemRegs.count(Reg))
|
|
|
|
AddedRegPressure.insert(Reg);
|
2009-06-13 09:12:55 +00:00
|
|
|
}
|
|
|
|
}
|
2009-06-19 23:17:27 +00:00
|
|
|
|
|
|
|
// Estimate register pressure increase due to the transformation.
|
|
|
|
if (MemRegs.size() <= 4)
|
|
|
|
// Ok if we are moving small number of instructions.
|
|
|
|
return true;
|
|
|
|
return AddedRegPressure.size() <= MemRegs.size() * 2;
|
2009-06-13 09:12:55 +00:00
|
|
|
}
|
|
|
|
|
2011-11-11 22:18:09 +00:00
|
|
|
|
|
|
|
/// Copy Op0 and Op1 operands into a new array assigned to MI.
|
|
|
|
static void concatenateMemOperands(MachineInstr *MI, MachineInstr *Op0,
|
|
|
|
MachineInstr *Op1) {
|
|
|
|
assert(MI->memoperands_empty() && "expected a new machineinstr");
|
|
|
|
size_t numMemRefs = (Op0->memoperands_end() - Op0->memoperands_begin())
|
|
|
|
+ (Op1->memoperands_end() - Op1->memoperands_begin());
|
|
|
|
|
|
|
|
MachineFunction *MF = MI->getParent()->getParent();
|
|
|
|
MachineSDNode::mmo_iterator MemBegin = MF->allocateMemRefsArray(numMemRefs);
|
|
|
|
MachineSDNode::mmo_iterator MemEnd =
|
|
|
|
std::copy(Op0->memoperands_begin(), Op0->memoperands_end(), MemBegin);
|
|
|
|
MemEnd =
|
|
|
|
std::copy(Op1->memoperands_begin(), Op1->memoperands_end(), MemEnd);
|
|
|
|
MI->setMemRefs(MemBegin, MemEnd);
|
|
|
|
}
|
|
|
|
|
2009-06-15 20:54:56 +00:00
|
|
|
bool
|
|
|
|
ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
|
|
|
|
DebugLoc &dl,
|
|
|
|
unsigned &NewOpc, unsigned &EvenReg,
|
|
|
|
unsigned &OddReg, unsigned &BaseReg,
|
2010-10-27 23:12:14 +00:00
|
|
|
int &Offset, unsigned &PredReg,
|
2009-09-25 21:44:53 +00:00
|
|
|
ARMCC::CondCodes &Pred,
|
|
|
|
bool &isT2) {
|
2009-09-29 07:07:30 +00:00
|
|
|
// Make sure we're allowed to generate LDRD/STRD.
|
|
|
|
if (!STI->hasV5TEOps())
|
|
|
|
return false;
|
|
|
|
|
2009-11-09 00:11:35 +00:00
|
|
|
// FIXME: VLDRS / VSTRS -> VLDRD / VSTRD
|
2009-09-25 21:44:53 +00:00
|
|
|
unsigned Scale = 1;
|
2009-06-15 20:54:56 +00:00
|
|
|
unsigned Opcode = Op0->getOpcode();
|
2010-10-26 22:37:02 +00:00
|
|
|
if (Opcode == ARM::LDRi12)
|
2009-06-15 20:54:56 +00:00
|
|
|
NewOpc = ARM::LDRD;
|
2010-10-27 23:12:14 +00:00
|
|
|
else if (Opcode == ARM::STRi12)
|
2009-06-15 20:54:56 +00:00
|
|
|
NewOpc = ARM::STRD;
|
2009-09-25 21:44:53 +00:00
|
|
|
else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {
|
|
|
|
NewOpc = ARM::t2LDRDi8;
|
|
|
|
Scale = 4;
|
|
|
|
isT2 = true;
|
|
|
|
} else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {
|
|
|
|
NewOpc = ARM::t2STRDi8;
|
|
|
|
Scale = 4;
|
|
|
|
isT2 = true;
|
|
|
|
} else
|
|
|
|
return false;
|
|
|
|
|
2010-10-26 19:34:41 +00:00
|
|
|
// Make sure the base address satisfies i64 ld / st alignment requirement.
|
2009-06-15 20:54:56 +00:00
|
|
|
if (!Op0->hasOneMemOperand() ||
|
2009-09-25 20:36:54 +00:00
|
|
|
!(*Op0->memoperands_begin())->getValue() ||
|
|
|
|
(*Op0->memoperands_begin())->isVolatile())
|
2009-06-15 08:28:29 +00:00
|
|
|
return false;
|
|
|
|
|
2009-09-25 20:36:54 +00:00
|
|
|
unsigned Align = (*Op0->memoperands_begin())->getAlignment();
|
2010-04-15 04:33:49 +00:00
|
|
|
const Function *Func = MF->getFunction();
|
2009-06-15 08:28:29 +00:00
|
|
|
unsigned ReqAlign = STI->hasV6Ops()
|
2010-10-27 23:12:14 +00:00
|
|
|
? TD->getABITypeAlignment(Type::getInt64Ty(Func->getContext()))
|
2009-09-25 21:44:53 +00:00
|
|
|
: 8; // Pre-v6 need 8-byte align
|
2009-06-15 20:54:56 +00:00
|
|
|
if (Align < ReqAlign)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Then make sure the immediate offset fits.
|
|
|
|
int OffImm = getMemoryOpOffset(Op0);
|
2009-09-27 09:46:04 +00:00
|
|
|
if (isT2) {
|
2011-03-15 18:41:52 +00:00
|
|
|
int Limit = (1 << 8) * Scale;
|
|
|
|
if (OffImm >= Limit || (OffImm <= -Limit) || (OffImm & (Scale-1)))
|
|
|
|
return false;
|
2009-09-25 21:44:53 +00:00
|
|
|
Offset = OffImm;
|
2009-09-27 09:46:04 +00:00
|
|
|
} else {
|
|
|
|
ARM_AM::AddrOpc AddSub = ARM_AM::add;
|
|
|
|
if (OffImm < 0) {
|
|
|
|
AddSub = ARM_AM::sub;
|
|
|
|
OffImm = - OffImm;
|
|
|
|
}
|
|
|
|
int Limit = (1 << 8) * Scale;
|
|
|
|
if (OffImm >= Limit || (OffImm & (Scale-1)))
|
|
|
|
return false;
|
2009-09-25 21:44:53 +00:00
|
|
|
Offset = ARM_AM::getAM3Opc(AddSub, OffImm);
|
2009-09-27 09:46:04 +00:00
|
|
|
}
|
2009-06-15 20:54:56 +00:00
|
|
|
EvenReg = Op0->getOperand(0).getReg();
|
2009-06-15 21:18:20 +00:00
|
|
|
OddReg = Op1->getOperand(0).getReg();
|
2009-06-15 20:54:56 +00:00
|
|
|
if (EvenReg == OddReg)
|
|
|
|
return false;
|
|
|
|
BaseReg = Op0->getOperand(1).getReg();
|
2012-03-27 07:21:54 +00:00
|
|
|
Pred = getInstrPredicate(Op0, PredReg);
|
2009-06-15 20:54:56 +00:00
|
|
|
dl = Op0->getDebugLoc();
|
|
|
|
return true;
|
2009-06-15 08:28:29 +00:00
|
|
|
}
|
|
|
|
|
2011-02-07 17:43:03 +00:00
|
|
|
namespace {
|
|
|
|
struct OffsetCompare {
|
|
|
|
bool operator()(const MachineInstr *LHS, const MachineInstr *RHS) const {
|
|
|
|
int LOffset = getMemoryOpOffset(LHS);
|
|
|
|
int ROffset = getMemoryOpOffset(RHS);
|
|
|
|
assert(LHS == RHS || LOffset != ROffset);
|
|
|
|
return LOffset > ROffset;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2009-06-13 09:12:55 +00:00
|
|
|
bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
|
|
|
|
SmallVector<MachineInstr*, 4> &Ops,
|
|
|
|
unsigned Base, bool isLd,
|
|
|
|
DenseMap<MachineInstr*, unsigned> &MI2LocMap) {
|
|
|
|
bool RetVal = false;
|
|
|
|
|
|
|
|
// Sort by offset (in reverse order).
|
|
|
|
std::sort(Ops.begin(), Ops.end(), OffsetCompare());
|
|
|
|
|
|
|
|
// The loads / stores of the same base are in order. Scan them from first to
|
2010-06-04 00:15:00 +00:00
|
|
|
// last and check for the following:
|
2009-06-13 09:12:55 +00:00
|
|
|
// 1. Any def of base.
|
|
|
|
// 2. Any gaps.
|
|
|
|
while (Ops.size() > 1) {
|
|
|
|
unsigned FirstLoc = ~0U;
|
|
|
|
unsigned LastLoc = 0;
|
|
|
|
MachineInstr *FirstOp = 0;
|
|
|
|
MachineInstr *LastOp = 0;
|
|
|
|
int LastOffset = 0;
|
2009-06-18 02:04:01 +00:00
|
|
|
unsigned LastOpcode = 0;
|
2009-06-13 09:12:55 +00:00
|
|
|
unsigned LastBytes = 0;
|
|
|
|
unsigned NumMove = 0;
|
|
|
|
for (int i = Ops.size() - 1; i >= 0; --i) {
|
|
|
|
MachineInstr *Op = Ops[i];
|
|
|
|
unsigned Loc = MI2LocMap[Op];
|
|
|
|
if (Loc <= FirstLoc) {
|
|
|
|
FirstLoc = Loc;
|
|
|
|
FirstOp = Op;
|
|
|
|
}
|
|
|
|
if (Loc >= LastLoc) {
|
|
|
|
LastLoc = Loc;
|
|
|
|
LastOp = Op;
|
|
|
|
}
|
|
|
|
|
2012-01-11 03:56:08 +00:00
|
|
|
unsigned LSMOpcode
|
|
|
|
= getLoadStoreMultipleOpcode(Op->getOpcode(), ARM_AM::ia);
|
|
|
|
if (LastOpcode && LSMOpcode != LastOpcode)
|
2009-06-18 02:04:01 +00:00
|
|
|
break;
|
|
|
|
|
2009-06-13 09:12:55 +00:00
|
|
|
int Offset = getMemoryOpOffset(Op);
|
|
|
|
unsigned Bytes = getLSMultipleTransferSize(Op);
|
|
|
|
if (LastBytes) {
|
|
|
|
if (Bytes != LastBytes || Offset != (LastOffset + (int)Bytes))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LastOffset = Offset;
|
|
|
|
LastBytes = Bytes;
|
2012-01-11 03:56:08 +00:00
|
|
|
LastOpcode = LSMOpcode;
|
2009-09-25 21:44:53 +00:00
|
|
|
if (++NumMove == 8) // FIXME: Tune this limit.
|
2009-06-13 09:12:55 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (NumMove <= 1)
|
|
|
|
Ops.pop_back();
|
|
|
|
else {
|
2009-06-19 23:17:27 +00:00
|
|
|
SmallPtrSet<MachineInstr*, 4> MemOps;
|
|
|
|
SmallSet<unsigned, 4> MemRegs;
|
|
|
|
for (int i = NumMove-1; i >= 0; --i) {
|
|
|
|
MemOps.insert(Ops[i]);
|
|
|
|
MemRegs.insert(Ops[i]->getOperand(0).getReg());
|
|
|
|
}
|
2009-06-13 09:12:55 +00:00
|
|
|
|
|
|
|
// Be conservative, if the instructions are too far apart, don't
|
|
|
|
// move them. We want to limit the increase of register pressure.
|
2009-06-19 23:17:27 +00:00
|
|
|
bool DoMove = (LastLoc - FirstLoc) <= NumMove*4; // FIXME: Tune this.
|
2009-06-13 09:12:55 +00:00
|
|
|
if (DoMove)
|
2009-06-19 23:17:27 +00:00
|
|
|
DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,
|
|
|
|
MemOps, MemRegs, TRI);
|
2009-06-13 09:12:55 +00:00
|
|
|
if (!DoMove) {
|
|
|
|
for (unsigned i = 0; i != NumMove; ++i)
|
|
|
|
Ops.pop_back();
|
|
|
|
} else {
|
|
|
|
// This is the new location for the loads / stores.
|
|
|
|
MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
|
2010-06-15 00:41:09 +00:00
|
|
|
while (InsertPos != MBB->end()
|
|
|
|
&& (MemOps.count(InsertPos) || InsertPos->isDebugValue()))
|
2009-06-13 09:12:55 +00:00
|
|
|
++InsertPos;
|
2009-06-15 08:28:29 +00:00
|
|
|
|
|
|
|
// If we are moving a pair of loads / stores, see if it makes sense
|
|
|
|
// to try to allocate a pair of registers that can form register pairs.
|
2009-06-15 20:54:56 +00:00
|
|
|
MachineInstr *Op0 = Ops.back();
|
|
|
|
MachineInstr *Op1 = Ops[Ops.size()-2];
|
|
|
|
unsigned EvenReg = 0, OddReg = 0;
|
2010-10-27 23:12:14 +00:00
|
|
|
unsigned BaseReg = 0, PredReg = 0;
|
2009-06-15 20:54:56 +00:00
|
|
|
ARMCC::CondCodes Pred = ARMCC::AL;
|
2009-09-25 21:44:53 +00:00
|
|
|
bool isT2 = false;
|
2009-06-15 20:54:56 +00:00
|
|
|
unsigned NewOpc = 0;
|
2009-09-27 09:46:04 +00:00
|
|
|
int Offset = 0;
|
2009-06-15 20:54:56 +00:00
|
|
|
DebugLoc dl;
|
|
|
|
if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
|
2010-10-27 23:12:14 +00:00
|
|
|
EvenReg, OddReg, BaseReg,
|
2009-09-25 21:44:53 +00:00
|
|
|
Offset, PredReg, Pred, isT2)) {
|
2009-06-15 20:54:56 +00:00
|
|
|
Ops.pop_back();
|
|
|
|
Ops.pop_back();
|
2009-06-15 08:28:29 +00:00
|
|
|
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &MCID = TII->get(NewOpc);
|
|
|
|
const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI);
|
2011-05-18 21:25:14 +00:00
|
|
|
MRI->constrainRegClass(EvenReg, TRC);
|
|
|
|
MRI->constrainRegClass(OddReg, TRC);
|
|
|
|
|
2009-06-15 20:54:56 +00:00
|
|
|
// Form the pair instruction.
|
2009-06-18 02:04:01 +00:00
|
|
|
if (isLd) {
|
2011-06-28 19:10:37 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
|
2009-06-15 08:28:29 +00:00
|
|
|
.addReg(EvenReg, RegState::Define)
|
|
|
|
.addReg(OddReg, RegState::Define)
|
2009-09-25 21:44:53 +00:00
|
|
|
.addReg(BaseReg);
|
2010-10-27 23:12:14 +00:00
|
|
|
// FIXME: We're converting from LDRi12 to an insn that still
|
2010-10-26 22:37:02 +00:00
|
|
|
// uses addrmode2, so we need an explicit offset reg. It should
|
2010-10-27 23:12:14 +00:00
|
|
|
// always by reg0 since we're transforming LDRi12s.
|
2009-09-25 21:44:53 +00:00
|
|
|
if (!isT2)
|
2010-10-26 22:37:02 +00:00
|
|
|
MIB.addReg(0);
|
2009-09-25 21:44:53 +00:00
|
|
|
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
|
2011-11-11 22:18:09 +00:00
|
|
|
concatenateMemOperands(MIB, Op0, Op1);
|
|
|
|
DEBUG(dbgs() << "Formed " << *MIB << "\n");
|
2009-06-18 02:04:01 +00:00
|
|
|
++NumLDRDFormed;
|
|
|
|
} else {
|
2011-06-28 19:10:37 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
|
2009-06-15 08:28:29 +00:00
|
|
|
.addReg(EvenReg)
|
|
|
|
.addReg(OddReg)
|
2009-09-25 21:44:53 +00:00
|
|
|
.addReg(BaseReg);
|
2010-10-27 23:12:14 +00:00
|
|
|
// FIXME: We're converting from LDRi12 to an insn that still
|
|
|
|
// uses addrmode2, so we need an explicit offset reg. It should
|
|
|
|
// always by reg0 since we're transforming STRi12s.
|
2009-09-25 21:44:53 +00:00
|
|
|
if (!isT2)
|
2010-10-27 23:12:14 +00:00
|
|
|
MIB.addReg(0);
|
2009-09-25 21:44:53 +00:00
|
|
|
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
|
2011-11-11 22:18:09 +00:00
|
|
|
concatenateMemOperands(MIB, Op0, Op1);
|
|
|
|
DEBUG(dbgs() << "Formed " << *MIB << "\n");
|
2009-06-18 02:04:01 +00:00
|
|
|
++NumSTRDFormed;
|
|
|
|
}
|
|
|
|
MBB->erase(Op0);
|
|
|
|
MBB->erase(Op1);
|
2009-06-15 08:28:29 +00:00
|
|
|
|
|
|
|
// Add register allocation hints to form register pairs.
|
|
|
|
MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg);
|
|
|
|
MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg);
|
2009-06-15 20:54:56 +00:00
|
|
|
} else {
|
|
|
|
for (unsigned i = 0; i != NumMove; ++i) {
|
|
|
|
MachineInstr *Op = Ops.back();
|
|
|
|
Ops.pop_back();
|
|
|
|
MBB->splice(InsertPos, MBB, Op);
|
|
|
|
}
|
2009-06-13 09:12:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
NumLdStMoved += NumMove;
|
|
|
|
RetVal = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return RetVal;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
|
|
|
|
bool RetVal = false;
|
|
|
|
|
|
|
|
DenseMap<MachineInstr*, unsigned> MI2LocMap;
|
|
|
|
DenseMap<unsigned, SmallVector<MachineInstr*, 4> > Base2LdsMap;
|
|
|
|
DenseMap<unsigned, SmallVector<MachineInstr*, 4> > Base2StsMap;
|
|
|
|
SmallVector<unsigned, 4> LdBases;
|
|
|
|
SmallVector<unsigned, 4> StBases;
|
|
|
|
|
|
|
|
unsigned Loc = 0;
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB->begin();
|
|
|
|
MachineBasicBlock::iterator E = MBB->end();
|
|
|
|
while (MBBI != E) {
|
|
|
|
for (; MBBI != E; ++MBBI) {
|
|
|
|
MachineInstr *MI = MBBI;
|
2011-12-07 07:15:52 +00:00
|
|
|
if (MI->isCall() || MI->isTerminator()) {
|
2009-06-13 09:12:55 +00:00
|
|
|
// Stop at barriers.
|
|
|
|
++MBBI;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-06-04 01:23:30 +00:00
|
|
|
if (!MI->isDebugValue())
|
|
|
|
MI2LocMap[MI] = ++Loc;
|
|
|
|
|
2009-06-13 09:12:55 +00:00
|
|
|
if (!isMemoryOp(MI))
|
|
|
|
continue;
|
|
|
|
unsigned PredReg = 0;
|
2012-03-27 07:21:54 +00:00
|
|
|
if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
|
2009-06-13 09:12:55 +00:00
|
|
|
continue;
|
|
|
|
|
2009-09-25 21:44:53 +00:00
|
|
|
int Opc = MI->getOpcode();
|
2009-11-09 00:11:35 +00:00
|
|
|
bool isLd = isi32Load(Opc) || Opc == ARM::VLDRS || Opc == ARM::VLDRD;
|
2009-06-13 09:12:55 +00:00
|
|
|
unsigned Base = MI->getOperand(1).getReg();
|
|
|
|
int Offset = getMemoryOpOffset(MI);
|
|
|
|
|
|
|
|
bool StopHere = false;
|
|
|
|
if (isLd) {
|
|
|
|
DenseMap<unsigned, SmallVector<MachineInstr*, 4> >::iterator BI =
|
|
|
|
Base2LdsMap.find(Base);
|
|
|
|
if (BI != Base2LdsMap.end()) {
|
|
|
|
for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
|
|
|
|
if (Offset == getMemoryOpOffset(BI->second[i])) {
|
|
|
|
StopHere = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!StopHere)
|
|
|
|
BI->second.push_back(MI);
|
|
|
|
} else {
|
|
|
|
SmallVector<MachineInstr*, 4> MIs;
|
|
|
|
MIs.push_back(MI);
|
|
|
|
Base2LdsMap[Base] = MIs;
|
|
|
|
LdBases.push_back(Base);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
DenseMap<unsigned, SmallVector<MachineInstr*, 4> >::iterator BI =
|
|
|
|
Base2StsMap.find(Base);
|
|
|
|
if (BI != Base2StsMap.end()) {
|
|
|
|
for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
|
|
|
|
if (Offset == getMemoryOpOffset(BI->second[i])) {
|
|
|
|
StopHere = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!StopHere)
|
|
|
|
BI->second.push_back(MI);
|
|
|
|
} else {
|
|
|
|
SmallVector<MachineInstr*, 4> MIs;
|
|
|
|
MIs.push_back(MI);
|
|
|
|
Base2StsMap[Base] = MIs;
|
|
|
|
StBases.push_back(Base);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (StopHere) {
|
2009-06-19 23:17:27 +00:00
|
|
|
// Found a duplicate (a base+offset combination that's seen earlier).
|
|
|
|
// Backtrack.
|
2009-06-13 09:12:55 +00:00
|
|
|
--Loc;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Re-schedule loads.
|
|
|
|
for (unsigned i = 0, e = LdBases.size(); i != e; ++i) {
|
|
|
|
unsigned Base = LdBases[i];
|
|
|
|
SmallVector<MachineInstr*, 4> &Lds = Base2LdsMap[Base];
|
|
|
|
if (Lds.size() > 1)
|
|
|
|
RetVal |= RescheduleOps(MBB, Lds, Base, true, MI2LocMap);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Re-schedule stores.
|
|
|
|
for (unsigned i = 0, e = StBases.size(); i != e; ++i) {
|
|
|
|
unsigned Base = StBases[i];
|
|
|
|
SmallVector<MachineInstr*, 4> &Sts = Base2StsMap[Base];
|
|
|
|
if (Sts.size() > 1)
|
|
|
|
RetVal |= RescheduleOps(MBB, Sts, Base, false, MI2LocMap);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (MBBI != E) {
|
|
|
|
Base2LdsMap.clear();
|
|
|
|
Base2StsMap.clear();
|
|
|
|
LdBases.clear();
|
|
|
|
StBases.clear();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return RetVal;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// createARMLoadStoreOptimizationPass - returns an instance of the load / store
|
|
|
|
/// optimization pass.
|
|
|
|
FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) {
|
|
|
|
if (PreAlloc)
|
|
|
|
return new ARMPreAllocLoadStoreOpt();
|
|
|
|
return new ARMLoadStoreOpt();
|
|
|
|
}
|