2012-02-17 08:55:11 +00:00
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//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MIPS assembly language.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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2011-07-07 23:56:50 +00:00
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#include "InstPrinter/MipsInstPrinter.h"
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2011-11-11 22:58:42 +00:00
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#include "MCTargetDesc/MipsBaseInfo.h"
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2014-02-28 10:00:38 +00:00
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#include "MCTargetDesc/MipsMCNaCl.h"
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2012-12-03 16:50:05 +00:00
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#include "Mips.h"
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2013-01-18 21:20:38 +00:00
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#include "MipsAsmPrinter.h"
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2012-12-03 16:50:05 +00:00
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#include "MipsInstrInfo.h"
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#include "MipsMCInstLower.h"
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2013-10-08 13:08:17 +00:00
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#include "MipsTargetStreamer.h"
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2011-11-08 22:26:47 +00:00
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Twine.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/MachineConstantPool.h"
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2007-07-11 23:24:41 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2012-07-05 23:58:21 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/MachineInstr.h"
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2014-02-28 10:00:38 +00:00
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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2011-08-12 21:30:06 +00:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instructions.h"
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2014-01-07 21:19:40 +00:00
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#include "llvm/IR/Mangler.h"
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2009-08-22 20:48:53 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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2014-01-27 01:33:33 +00:00
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#include "llvm/MC/MCContext.h"
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2013-10-05 16:42:21 +00:00
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#include "llvm/MC/MCELFStreamer.h"
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2014-02-14 19:16:39 +00:00
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#include "llvm/MC/MCExpr.h"
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2011-07-07 23:56:50 +00:00
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#include "llvm/MC/MCInst.h"
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2014-02-14 19:16:39 +00:00
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#include "llvm/MC/MCSection.h"
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2014-01-27 01:33:33 +00:00
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#include "llvm/MC/MCSectionELF.h"
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2009-09-13 17:14:04 +00:00
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#include "llvm/MC/MCSymbol.h"
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2013-02-19 22:04:37 +00:00
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#include "llvm/Support/ELF.h"
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2012-07-05 23:58:21 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Support/raw_ostream.h"
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2011-03-04 17:51:39 +00:00
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#include "llvm/Target/TargetLoweringObjectFile.h"
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2007-11-12 19:49:57 +00:00
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#include "llvm/Target/TargetOptions.h"
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2014-02-14 19:16:39 +00:00
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#include <string>
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2011-07-01 01:04:43 +00:00
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2007-06-06 07:42:06 +00:00
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using namespace llvm;
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2014-04-22 02:41:26 +00:00
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#define DEBUG_TYPE "mips-asm-printer"
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2013-10-08 13:08:17 +00:00
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MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
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2014-01-14 01:21:46 +00:00
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return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
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2013-10-08 13:08:17 +00:00
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}
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2012-03-28 00:22:50 +00:00
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bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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2014-07-18 00:08:53 +00:00
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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2013-04-09 19:46:01 +00:00
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// Initialize TargetLoweringObjectFile.
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2014-07-18 23:41:32 +00:00
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const_cast<TargetLoweringObjectFile &>(getObjFileLowering())
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2013-04-09 19:46:01 +00:00
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.Initialize(OutContext, TM);
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2014-07-18 23:41:32 +00:00
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2012-03-28 00:22:50 +00:00
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MipsFI = MF.getInfo<MipsFunctionInfo>();
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2014-02-14 19:16:39 +00:00
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if (Subtarget->inMips16Mode())
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for (std::map<
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const char *,
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const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
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it = MipsFI->StubsNeeded.begin();
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it != MipsFI->StubsNeeded.end(); ++it) {
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const char *Symbol = it->first;
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const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
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if (StubsNeeded.find(Symbol) == StubsNeeded.end())
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StubsNeeded[Symbol] = Signature;
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}
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2013-10-27 21:57:36 +00:00
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MCP = MF.getConstantPool();
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2014-02-28 10:00:38 +00:00
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// In NaCl, all indirect jump targets must be aligned to bundle size.
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if (Subtarget->isTargetNaCl())
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NaClAlignIndirectJumpTargets(MF);
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2012-03-28 00:22:50 +00:00
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AsmPrinter::runOnMachineFunction(MF);
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return true;
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2011-11-08 22:26:47 +00:00
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}
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2012-09-27 01:59:07 +00:00
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bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
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MCOp = MCInstLowering.LowerOperand(MO);
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return MCOp.isValid();
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}
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#include "MipsGenMCPseudoLowering.inc"
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2014-07-09 10:21:59 +00:00
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// Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
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// JALR, or JALR64 as appropriate for the target
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void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
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const MachineInstr *MI) {
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[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-09 10:16:07 +00:00
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bool HasLinkReg = false;
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MCInst TmpInst0;
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if (Subtarget->hasMips64r6()) {
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// MIPS64r6 should use (JALR64 ZERO_64, $rs)
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TmpInst0.setOpcode(Mips::JALR64);
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HasLinkReg = true;
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} else if (Subtarget->hasMips32r6()) {
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// MIPS32r6 should use (JALR ZERO, $rs)
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TmpInst0.setOpcode(Mips::JALR);
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HasLinkReg = true;
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} else if (Subtarget->inMicroMipsMode())
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// microMIPS should use (JR_MM $rs)
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TmpInst0.setOpcode(Mips::JR_MM);
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else {
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// Everything else should use (JR $rs)
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TmpInst0.setOpcode(Mips::JR);
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}
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MCOperand MCOp;
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if (HasLinkReg) {
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unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
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TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
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}
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lowerOperand(MI->getOperand(0), MCOp);
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TmpInst0.addOperand(MCOp);
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EmitToStreamer(OutStreamer, TmpInst0);
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}
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2011-07-07 20:10:52 +00:00
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void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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2014-07-08 08:59:22 +00:00
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MipsTargetStreamer &TS = getTargetStreamer();
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TS.setCanHaveModuleDir(false);
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2014-07-08 10:11:38 +00:00
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2011-07-07 20:10:52 +00:00
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if (MI->isDebugValue()) {
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2011-12-30 21:09:41 +00:00
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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2011-07-07 20:10:52 +00:00
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PrintDebugValueComment(MI, OS);
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return;
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}
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2007-06-06 07:42:06 +00:00
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2013-10-27 21:57:36 +00:00
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// If we just ended a constant pool, mark it as such.
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if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
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OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
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InConstantPool = false;
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}
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if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
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// CONSTPOOL_ENTRY - This instruction represents a floating
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//constant pool in the function. The first operand is the ID#
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// for this instruction, the second is the index into the
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// MachineConstantPool that this is, the third is the size in
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// bytes of this constant pool entry.
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// The required alignment is specified on the basic block holding this MI.
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//
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unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
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unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
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// If this is the first entry of the pool, mark it.
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if (!InConstantPool) {
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OutStreamer.EmitDataRegion(MCDR_DataRegion);
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InConstantPool = true;
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}
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OutStreamer.EmitLabel(GetCPISymbol(LabelId));
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const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
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if (MCPE.isMachineConstantPoolEntry())
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EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
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else
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EmitGlobalConstant(MCPE.Val.ConstVal);
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return;
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}
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2014-01-25 15:06:56 +00:00
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2012-06-13 23:25:52 +00:00
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MachineBasicBlock::const_instr_iterator I = MI;
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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2013-02-06 21:50:15 +00:00
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// Do any auto-generated pseudo lowerings.
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if (emitPseudoExpansionLowering(OutStreamer, &*I))
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continue;
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2012-08-28 19:07:39 +00:00
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[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-09 10:16:07 +00:00
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if (I->getOpcode() == Mips::PseudoReturn ||
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2014-07-09 10:21:59 +00:00
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I->getOpcode() == Mips::PseudoReturn64 ||
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I->getOpcode() == Mips::PseudoIndirectBranch ||
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I->getOpcode() == Mips::PseudoIndirectBranch64) {
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emitPseudoIndirectBranch(OutStreamer, &*I);
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[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-09 10:16:07 +00:00
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continue;
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}
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2013-02-15 21:05:58 +00:00
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// The inMips16Mode() test is not permanent.
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// Some instructions are marked as pseudo right now which
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// would make the test fail for the wrong reason but
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// that will be fixed soon. We need this here because we are
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// removing another test for this situation downstream in the
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// callchain.
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//
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2014-04-30 15:06:25 +00:00
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if (I->isPseudo() && !Subtarget->inMips16Mode()
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&& !isLongBranchPseudo(I->getOpcode()))
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2013-02-15 21:05:58 +00:00
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llvm_unreachable("Pseudo opcode found in EmitInstruction()");
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2013-02-06 21:50:15 +00:00
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MCInst TmpInst0;
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MCInstLowering.Lower(I, TmpInst0);
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2014-01-28 23:12:42 +00:00
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EmitToStreamer(OutStreamer, TmpInst0);
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2013-02-06 21:50:15 +00:00
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} while ((++I != E) && I->isInsideBundle()); // Delay slot check
|
2011-07-07 20:10:52 +00:00
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}
|
2007-06-06 07:42:06 +00:00
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2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-28 05:06:17 +00:00
|
|
|
//
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|
// Mips Asm Directives
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|
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
|
2011-03-04 17:51:39 +00:00
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|
// -- Mask directives "(f)mask bitmask, offset"
|
2007-08-28 05:06:17 +00:00
|
|
|
// Tells the assembler which registers are saved and where.
|
2011-03-04 17:51:39 +00:00
|
|
|
// bitmask - contain a little endian bitset indicating which registers are
|
|
|
|
// saved on function prologue (e.g. with a 0x80000000 mask, the
|
2007-08-28 05:06:17 +00:00
|
|
|
// assembler knows the register 31 (RA) is saved at prologue.
|
2011-03-04 17:51:39 +00:00
|
|
|
// offset - the position before stack pointer subtraction indicating where
|
2007-08-28 05:06:17 +00:00
|
|
|
// the first saved register on prologue is located. (e.g. with a
|
|
|
|
//
|
|
|
|
// Consider the following function prologue:
|
|
|
|
//
|
2008-02-27 06:33:05 +00:00
|
|
|
// .frame $fp,48,$ra
|
|
|
|
// .mask 0xc0000000,-8
|
|
|
|
// addiu $sp, $sp, -48
|
|
|
|
// sw $ra, 40($sp)
|
|
|
|
// sw $fp, 36($sp)
|
2007-08-28 05:06:17 +00:00
|
|
|
//
|
2011-03-04 17:51:39 +00:00
|
|
|
// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
|
|
|
|
// 30 (FP) are saved at prologue. As the save order on prologue is from
|
|
|
|
// left to right, RA is saved first. A -8 offset means that after the
|
2007-08-28 05:06:17 +00:00
|
|
|
// stack pointer subtration, the first register in the mask (RA) will be
|
|
|
|
// saved at address 48-8=40.
|
|
|
|
//
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-07-11 23:24:41 +00:00
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2008-07-14 14:42:54 +00:00
|
|
|
// Mask directives
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2008-07-14 14:42:54 +00:00
|
|
|
|
2011-03-04 17:51:39 +00:00
|
|
|
// Create a bitmask with all callee saved registers for CPU or Floating Point
|
2008-08-06 06:14:43 +00:00
|
|
|
// registers. For CPU registers consider RA, GP and FP for saving if necessary.
|
2014-01-27 04:33:11 +00:00
|
|
|
void MipsAsmPrinter::printSavedRegsBitmask() {
|
2008-08-06 06:14:43 +00:00
|
|
|
// CPU and FPU Saved Registers Bitmasks
|
2011-05-23 20:34:30 +00:00
|
|
|
unsigned CPUBitmask = 0, FPUBitmask = 0;
|
|
|
|
int CPUTopSavedRegOff, FPUTopSavedRegOff;
|
2007-08-28 05:06:17 +00:00
|
|
|
|
2008-08-06 06:14:43 +00:00
|
|
|
// Set the CPU and FPU Bitmasks
|
2010-01-28 06:22:43 +00:00
|
|
|
const MachineFrameInfo *MFI = MF->getFrameInfo();
|
2007-08-28 05:06:17 +00:00
|
|
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
2011-05-23 20:34:30 +00:00
|
|
|
// size of stack area to which FP callee-saved regs are saved.
|
2013-08-06 23:08:38 +00:00
|
|
|
unsigned CPURegSize = Mips::GPR32RegClass.getSize();
|
2012-04-20 07:30:17 +00:00
|
|
|
unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
|
|
|
|
unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
|
2011-05-23 20:34:30 +00:00
|
|
|
bool HasAFGR64Reg = false;
|
|
|
|
unsigned CSFPRegsSize = 0;
|
|
|
|
unsigned i, e = CSI.size();
|
|
|
|
|
|
|
|
// Set FPU Bitmask.
|
|
|
|
for (i = 0; i != e; ++i) {
|
2010-06-02 20:02:30 +00:00
|
|
|
unsigned Reg = CSI[i].getReg();
|
2013-08-06 23:08:38 +00:00
|
|
|
if (Mips::GPR32RegClass.contains(Reg))
|
2011-05-23 20:34:30 +00:00
|
|
|
break;
|
|
|
|
|
2012-12-10 20:04:40 +00:00
|
|
|
unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
|
2012-04-20 07:30:17 +00:00
|
|
|
if (Mips::AFGR64RegClass.contains(Reg)) {
|
2011-05-23 20:34:30 +00:00
|
|
|
FPUBitmask |= (3 << RegNum);
|
|
|
|
CSFPRegsSize += AFGR64RegSize;
|
|
|
|
HasAFGR64Reg = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
FPUBitmask |= (1 << RegNum);
|
|
|
|
CSFPRegsSize += FGR32RegSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set CPU Bitmask.
|
|
|
|
for (; i != e; ++i) {
|
|
|
|
unsigned Reg = CSI[i].getReg();
|
2012-12-10 20:04:40 +00:00
|
|
|
unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
|
2011-05-23 20:34:30 +00:00
|
|
|
CPUBitmask |= (1 << RegNum);
|
2008-08-06 06:14:43 +00:00
|
|
|
}
|
2007-08-28 05:06:17 +00:00
|
|
|
|
2011-05-23 20:34:30 +00:00
|
|
|
// FP Regs are saved right below where the virtual frame pointer points to.
|
|
|
|
FPUTopSavedRegOff = FPUBitmask ?
|
|
|
|
(HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
|
2010-11-18 21:19:35 +00:00
|
|
|
|
2011-05-23 20:34:30 +00:00
|
|
|
// CPU Regs are saved below FP Regs.
|
|
|
|
CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
|
2007-08-28 05:06:17 +00:00
|
|
|
|
2014-01-27 04:33:11 +00:00
|
|
|
MipsTargetStreamer &TS = getTargetStreamer();
|
2008-08-06 06:14:43 +00:00
|
|
|
// Print CPUBitmask
|
2014-01-27 04:33:11 +00:00
|
|
|
TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
|
2008-08-06 06:14:43 +00:00
|
|
|
|
|
|
|
// Print FPUBitmask
|
2014-01-27 04:33:11 +00:00
|
|
|
TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
|
2007-07-11 23:24:41 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2008-07-14 14:42:54 +00:00
|
|
|
// Frame and Set directives
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2008-07-14 14:42:54 +00:00
|
|
|
|
|
|
|
/// Frame Directive
|
2010-04-04 07:05:53 +00:00
|
|
|
void MipsAsmPrinter::emitFrameDirective() {
|
2008-07-14 14:42:54 +00:00
|
|
|
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
|
|
|
|
|
2010-01-28 06:22:43 +00:00
|
|
|
unsigned stackReg = RI.getFrameRegister(*MF);
|
2008-07-14 14:42:54 +00:00
|
|
|
unsigned returnReg = RI.getRARegister();
|
2010-01-28 06:22:43 +00:00
|
|
|
unsigned stackSize = MF->getFrameInfo()->getStackSize();
|
2008-07-14 14:42:54 +00:00
|
|
|
|
2014-01-27 03:53:56 +00:00
|
|
|
getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
|
2008-07-14 14:42:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Emit Set directives.
|
2011-03-04 17:51:39 +00:00
|
|
|
const char *MipsAsmPrinter::getCurrentABIString() const {
|
2010-04-04 07:05:53 +00:00
|
|
|
switch (Subtarget->getTargetABI()) {
|
2011-03-04 17:51:39 +00:00
|
|
|
case MipsSubtarget::O32: return "abi32";
|
2010-04-04 07:05:53 +00:00
|
|
|
case MipsSubtarget::N32: return "abiN32";
|
|
|
|
case MipsSubtarget::N64: return "abi64";
|
|
|
|
case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
|
2012-09-10 21:26:47 +00:00
|
|
|
default: llvm_unreachable("Unknown Mips ABI");
|
2008-07-14 14:42:54 +00:00
|
|
|
}
|
2011-03-04 17:51:39 +00:00
|
|
|
}
|
2008-07-14 14:42:54 +00:00
|
|
|
|
2010-01-27 23:23:58 +00:00
|
|
|
void MipsAsmPrinter::EmitFunctionEntryLabel() {
|
2014-01-14 18:57:12 +00:00
|
|
|
MipsTargetStreamer &TS = getTargetStreamer();
|
2014-02-28 10:00:38 +00:00
|
|
|
|
|
|
|
// NaCl sandboxing requires that indirect call instructions are masked.
|
|
|
|
// This means that function entry points should be bundle-aligned.
|
|
|
|
if (Subtarget->isTargetNaCl())
|
|
|
|
EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
|
|
|
|
|
2014-01-14 04:25:13 +00:00
|
|
|
if (Subtarget->inMicroMipsMode())
|
2014-01-14 18:57:12 +00:00
|
|
|
TS.emitDirectiveSetMicroMips();
|
2014-04-16 11:46:59 +00:00
|
|
|
else
|
|
|
|
TS.emitDirectiveSetNoMicroMips();
|
2014-01-14 04:25:13 +00:00
|
|
|
|
2014-01-14 18:57:12 +00:00
|
|
|
if (Subtarget->inMips16Mode())
|
|
|
|
TS.emitDirectiveSetMips16();
|
|
|
|
else
|
|
|
|
TS.emitDirectiveSetNoMips16();
|
2013-02-19 22:04:37 +00:00
|
|
|
|
2014-01-14 18:57:12 +00:00
|
|
|
TS.emitDirectiveEnt(*CurrentFnSym);
|
2010-01-27 23:23:58 +00:00
|
|
|
OutStreamer.EmitLabel(CurrentFnSym);
|
|
|
|
}
|
|
|
|
|
2010-01-28 06:22:43 +00:00
|
|
|
/// EmitFunctionBodyStart - Targets can override this to emit stuff before
|
|
|
|
/// the first basic block in the function.
|
|
|
|
void MipsAsmPrinter::EmitFunctionBodyStart() {
|
2014-01-26 05:06:48 +00:00
|
|
|
MipsTargetStreamer &TS = getTargetStreamer();
|
|
|
|
|
2013-10-29 16:24:21 +00:00
|
|
|
MCInstLowering.Initialize(&MF->getContext());
|
2012-03-28 00:22:50 +00:00
|
|
|
|
2013-05-03 23:17:24 +00:00
|
|
|
bool IsNakedFunction =
|
|
|
|
MF->getFunction()->
|
|
|
|
getAttributes().hasAttribute(AttributeSet::FunctionIndex,
|
|
|
|
Attribute::Naked);
|
|
|
|
if (!IsNakedFunction)
|
|
|
|
emitFrameDirective();
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2014-01-27 04:33:11 +00:00
|
|
|
if (!IsNakedFunction)
|
|
|
|
printSavedRegsBitmask();
|
|
|
|
|
2014-01-26 05:06:48 +00:00
|
|
|
if (!Subtarget->inMips16Mode()) {
|
|
|
|
TS.emitDirectiveSetNoReorder();
|
|
|
|
TS.emitDirectiveSetNoMacro();
|
|
|
|
TS.emitDirectiveSetNoAt();
|
2012-05-12 00:48:43 +00:00
|
|
|
}
|
2010-01-28 06:22:43 +00:00
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-01-28 06:22:43 +00:00
|
|
|
/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
|
|
|
|
/// the last basic block in the function.
|
|
|
|
void MipsAsmPrinter::EmitFunctionBodyEnd() {
|
2014-01-26 05:06:48 +00:00
|
|
|
MipsTargetStreamer &TS = getTargetStreamer();
|
|
|
|
|
2010-01-28 01:48:52 +00:00
|
|
|
// There are instruction for this macros, but they must
|
|
|
|
// always be at the function end, and we can't emit and
|
2011-03-04 17:51:39 +00:00
|
|
|
// break with BB logic.
|
2014-01-26 05:06:48 +00:00
|
|
|
if (!Subtarget->inMips16Mode()) {
|
|
|
|
TS.emitDirectiveSetAt();
|
|
|
|
TS.emitDirectiveSetMacro();
|
|
|
|
TS.emitDirectiveSetReorder();
|
2011-11-08 22:26:47 +00:00
|
|
|
}
|
2014-01-26 05:06:48 +00:00
|
|
|
TS.emitDirectiveEnd(CurrentFnSym->getName());
|
2013-10-27 21:57:36 +00:00
|
|
|
// Make sure to terminate any constant pools that were at the end
|
|
|
|
// of the function.
|
|
|
|
if (!InConstantPool)
|
|
|
|
return;
|
|
|
|
InConstantPool = false;
|
|
|
|
OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2010-07-20 08:37:04 +00:00
|
|
|
/// isBlockOnlyReachableByFallthough - Return true if the basic block has
|
|
|
|
/// exactly one predecessor and the control transfer mechanism between
|
|
|
|
/// the predecessor and this block is a fall-through.
|
2011-04-15 21:51:11 +00:00
|
|
|
bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
|
|
|
|
MBB) const {
|
2010-07-20 08:37:04 +00:00
|
|
|
// The predecessor has to be immediately before this block.
|
|
|
|
const MachineBasicBlock *Pred = *MBB->pred_begin();
|
|
|
|
|
|
|
|
// If the predecessor is a switch statement, assume a jump table
|
|
|
|
// implementation, so it is not a fall through.
|
|
|
|
if (const BasicBlock *bb = Pred->getBasicBlock())
|
|
|
|
if (isa<SwitchInst>(bb->getTerminator()))
|
|
|
|
return false;
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 18:57:38 +00:00
|
|
|
// If this is a landing pad, it isn't a fall through. If it has no preds,
|
|
|
|
// then nothing falls through to it.
|
|
|
|
if (MBB->isLandingPad() || MBB->pred_empty())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If there isn't exactly one predecessor, it can't be a fall through.
|
|
|
|
MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
|
|
|
|
++PI2;
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-04-01 18:57:38 +00:00
|
|
|
if (PI2 != MBB->pred_end())
|
2012-02-28 07:46:26 +00:00
|
|
|
return false;
|
2011-04-01 18:57:38 +00:00
|
|
|
|
|
|
|
// The predecessor has to be immediately before this block.
|
|
|
|
if (!Pred->isLayoutSuccessor(MBB))
|
|
|
|
return false;
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-04-01 18:57:38 +00:00
|
|
|
// If the block is completely empty, then it definitely does fall through.
|
|
|
|
if (Pred->empty())
|
|
|
|
return true;
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-04-01 18:57:38 +00:00
|
|
|
// Otherwise, check the last instruction.
|
|
|
|
// Check if the last terminator is an unconditional branch.
|
|
|
|
MachineBasicBlock::const_iterator I = Pred->end();
|
2011-12-07 07:15:52 +00:00
|
|
|
while (I != Pred->begin() && !(--I)->isTerminator()) ;
|
2011-04-01 18:57:38 +00:00
|
|
|
|
2011-12-07 07:15:52 +00:00
|
|
|
return !I->isBarrier();
|
2010-07-20 08:37:04 +00:00
|
|
|
}
|
|
|
|
|
2008-08-02 19:42:36 +00:00
|
|
|
// Print out an operand for an inline asm expression.
|
2012-05-10 21:48:22 +00:00
|
|
|
bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
2010-04-04 05:29:35 +00:00
|
|
|
unsigned AsmVariant,const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
2008-08-02 19:42:36 +00:00
|
|
|
// Does this asm operand have a single letter operand modifier?
|
2012-05-10 21:48:22 +00:00
|
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
|
|
|
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
switch (ExtraCode[0]) {
|
2012-05-19 00:51:56 +00:00
|
|
|
default:
|
2012-06-21 17:14:46 +00:00
|
|
|
// See if this is a generic print operand
|
|
|
|
return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
|
2012-05-19 00:51:56 +00:00
|
|
|
case 'X': // hex const int
|
|
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
|
|
|
|
return false;
|
|
|
|
case 'x': // hex const int (low 16 bits)
|
|
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
|
|
|
|
return false;
|
|
|
|
case 'd': // decimal const int
|
|
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
O << MO.getImm();
|
|
|
|
return false;
|
2012-05-30 19:05:19 +00:00
|
|
|
case 'm': // decimal const int minus 1
|
|
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
O << MO.getImm() - 1;
|
|
|
|
return false;
|
2012-06-28 20:46:26 +00:00
|
|
|
case 'z': {
|
|
|
|
// $0 if zero, regular printing otherwise
|
2012-06-28 01:33:40 +00:00
|
|
|
if (MO.getType() != MachineOperand::MO_Immediate)
|
|
|
|
return true;
|
|
|
|
int64_t Val = MO.getImm();
|
|
|
|
if (Val)
|
|
|
|
O << Val;
|
|
|
|
else
|
|
|
|
O << "$0";
|
|
|
|
return false;
|
|
|
|
}
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
case 'D': // Second part of a double word register operand
|
|
|
|
case 'L': // Low order register of a double word register operand
|
2012-07-18 06:41:36 +00:00
|
|
|
case 'M': // High order register of a double word register operand
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
{
|
2012-07-05 23:58:21 +00:00
|
|
|
if (OpNum == 0)
|
|
|
|
return true;
|
|
|
|
const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
|
|
|
|
if (!FlagsOP.isImm())
|
|
|
|
return true;
|
|
|
|
unsigned Flags = FlagsOP.getImm();
|
|
|
|
unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
|
2012-07-06 02:44:22 +00:00
|
|
|
// Number of registers represented by this operand. We are looking
|
|
|
|
// for 2 for 32 bit mode and 1 for 64 bit mode.
|
2012-07-05 23:58:21 +00:00
|
|
|
if (NumVals != 2) {
|
2012-07-06 02:44:22 +00:00
|
|
|
if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
|
2012-07-05 23:58:21 +00:00
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
O << '$' << MipsInstPrinter::getRegisterName(Reg);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
2012-07-11 21:41:49 +00:00
|
|
|
|
|
|
|
unsigned RegOp = OpNum;
|
|
|
|
if (!Subtarget->isGP64bit()){
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
// Endianess reverses which register holds the high or low value
|
2012-07-18 06:41:36 +00:00
|
|
|
// between M and L.
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
switch(ExtraCode[0]) {
|
2012-07-18 06:41:36 +00:00
|
|
|
case 'M':
|
|
|
|
RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
break;
|
|
|
|
case 'L':
|
2012-07-18 06:41:36 +00:00
|
|
|
RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
|
|
|
|
break;
|
|
|
|
case 'D': // Always the second part
|
|
|
|
RegOp = OpNum + 1;
|
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
|
|
|
}
|
|
|
|
if (RegOp >= MI->getNumOperands())
|
|
|
|
return true;
|
|
|
|
const MachineOperand &MO = MI->getOperand(RegOp);
|
|
|
|
if (!MO.isReg())
|
|
|
|
return true;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
O << '$' << MipsInstPrinter::getRegisterName(Reg);
|
|
|
|
return false;
|
2012-07-05 23:58:21 +00:00
|
|
|
}
|
2012-05-10 21:48:22 +00:00
|
|
|
}
|
2013-11-12 12:56:01 +00:00
|
|
|
case 'w':
|
|
|
|
// Print MSA registers for the 'f' constraint
|
|
|
|
// In LLVM, the 'w' modifier doesn't need to do anything.
|
|
|
|
// We can just call printOperand as normal.
|
|
|
|
break;
|
2012-07-06 02:44:22 +00:00
|
|
|
}
|
|
|
|
}
|
2008-08-02 19:42:36 +00:00
|
|
|
|
2012-05-10 21:48:22 +00:00
|
|
|
printOperand(MI, OpNum, O);
|
2008-08-02 19:42:36 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-06-21 00:40:49 +00:00
|
|
|
bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
|
|
|
unsigned OpNum, unsigned AsmVariant,
|
|
|
|
const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
Mips specific inline asm operand modifier 'D'
Modifier 'D' is to use the second word of a double integer.
We had previously implemented the pure register varient of
the modifier and this patch implements the memory reference.
#include "stdio.h"
int b[8] = {0,1,2,3,4,5,6,7};
void main()
{
int i;
// The first word. Notice, no 'D'
{asm (
"lw %0,%1;"
: "=r" (i)
: "m" (*(b+4))
);}
printf("%d\n",i);
// The second word
{asm (
"lw %0,%D1;"
: "=r" (i)
: "m" (*(b+4))
);}
printf("%d\n",i);
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 23:19:50 +00:00
|
|
|
int Offset = 0;
|
|
|
|
// Currently we are expecting either no ExtraCode or 'D'
|
|
|
|
if (ExtraCode) {
|
|
|
|
if (ExtraCode[0] == 'D')
|
|
|
|
Offset = 4;
|
|
|
|
else
|
|
|
|
return true; // Unknown modifier.
|
|
|
|
}
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-06-21 00:40:49 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
assert(MO.isReg() && "unexpected inline asm memory operand");
|
Mips specific inline asm operand modifier 'D'
Modifier 'D' is to use the second word of a double integer.
We had previously implemented the pure register varient of
the modifier and this patch implements the memory reference.
#include "stdio.h"
int b[8] = {0,1,2,3,4,5,6,7};
void main()
{
int i;
// The first word. Notice, no 'D'
{asm (
"lw %0,%1;"
: "=r" (i)
: "m" (*(b+4))
);}
printf("%d\n",i);
// The second word
{asm (
"lw %0,%D1;"
: "=r" (i)
: "m" (*(b+4))
);}
printf("%d\n",i);
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 23:19:50 +00:00
|
|
|
O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
|
2012-06-28 01:33:40 +00:00
|
|
|
|
2011-06-21 00:40:49 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-04-04 04:47:45 +00:00
|
|
|
void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
|
|
|
|
raw_ostream &O) {
|
2014-01-03 19:21:54 +00:00
|
|
|
const DataLayout *DL = TM.getDataLayout();
|
2007-06-06 07:42:06 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
2007-11-05 03:02:32 +00:00
|
|
|
bool closeP = false;
|
2009-09-01 17:27:58 +00:00
|
|
|
|
|
|
|
if (MO.getTargetFlags())
|
2009-08-27 19:57:56 +00:00
|
|
|
closeP = true;
|
2009-09-01 17:27:58 +00:00
|
|
|
|
|
|
|
switch(MO.getTargetFlags()) {
|
|
|
|
case MipsII::MO_GPREL: O << "%gp_rel("; break;
|
|
|
|
case MipsII::MO_GOT_CALL: O << "%call16("; break;
|
2011-04-01 21:41:06 +00:00
|
|
|
case MipsII::MO_GOT: O << "%got("; break;
|
|
|
|
case MipsII::MO_ABS_HI: O << "%hi("; break;
|
|
|
|
case MipsII::MO_ABS_LO: O << "%lo("; break;
|
2011-05-31 02:53:58 +00:00
|
|
|
case MipsII::MO_TLSGD: O << "%tlsgd("; break;
|
|
|
|
case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
|
|
|
|
case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
|
|
|
|
case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
|
2011-09-22 03:09:07 +00:00
|
|
|
case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
|
|
|
|
case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
|
|
|
|
case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
|
|
|
|
case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
|
|
|
|
case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2009-09-01 17:27:58 +00:00
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
switch (MO.getType()) {
|
2007-06-06 07:42:06 +00:00
|
|
|
case MachineOperand::MO_Register:
|
2011-07-07 23:56:50 +00:00
|
|
|
O << '$'
|
2011-11-06 20:37:06 +00:00
|
|
|
<< StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MachineOperand::MO_Immediate:
|
2011-05-24 21:22:21 +00:00
|
|
|
O << MO.getImm();
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
2010-03-13 21:04:28 +00:00
|
|
|
O << *MO.getMBB()->getSymbol();
|
2007-06-06 07:42:06 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
case MachineOperand::MO_GlobalAddress:
|
2013-10-29 17:07:16 +00:00
|
|
|
O << *getSymbol(MO.getGlobal());
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
|
|
|
|
2011-03-04 20:01:52 +00:00
|
|
|
case MachineOperand::MO_BlockAddress: {
|
2012-06-14 21:10:56 +00:00
|
|
|
MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
|
2011-03-04 20:01:52 +00:00
|
|
|
O << BA->getName();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
2014-01-03 19:21:54 +00:00
|
|
|
O << DL->getPrivateGlobalPrefix() << "CPI"
|
2007-12-30 23:10:15 +00:00
|
|
|
<< getFunctionNumber() << "_" << MO.getIndex();
|
2009-11-19 06:06:13 +00:00
|
|
|
if (MO.getOffset())
|
|
|
|
O << "+" << MO.getOffset();
|
2007-06-06 07:42:06 +00:00
|
|
|
break;
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
default:
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("<unknown operand type>");
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (closeP) O << ")";
|
|
|
|
}
|
|
|
|
|
2010-04-04 04:47:45 +00:00
|
|
|
void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
|
|
|
|
raw_ostream &O) {
|
2008-08-13 07:13:40 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
2010-04-27 22:24:37 +00:00
|
|
|
if (MO.isImm())
|
2008-08-13 07:13:40 +00:00
|
|
|
O << (unsigned short int)MO.getImm();
|
2011-03-04 17:51:39 +00:00
|
|
|
else
|
2010-04-04 04:47:45 +00:00
|
|
|
printOperand(MI, opNum, O);
|
2008-08-13 07:13:40 +00:00
|
|
|
}
|
|
|
|
|
2013-11-12 10:45:18 +00:00
|
|
|
void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
|
|
|
|
raw_ostream &O) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
|
|
if (MO.isImm())
|
|
|
|
O << (unsigned short int)(unsigned char)MO.getImm();
|
|
|
|
else
|
|
|
|
printOperand(MI, opNum, O);
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
void MipsAsmPrinter::
|
2011-07-07 20:54:20 +00:00
|
|
|
printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
2011-03-04 17:51:39 +00:00
|
|
|
// Load/Store memory operands -- imm($reg)
|
|
|
|
// If PIC target the target is loaded as the
|
2007-11-05 03:02:32 +00:00
|
|
|
// pattern lw $25,%call16($28)
|
2010-04-04 04:47:45 +00:00
|
|
|
printOperand(MI, opNum+1, O);
|
2011-07-07 18:57:00 +00:00
|
|
|
O << "(";
|
|
|
|
printOperand(MI, opNum, O);
|
2007-06-06 07:42:06 +00:00
|
|
|
O << ")";
|
|
|
|
}
|
|
|
|
|
2011-07-07 20:54:20 +00:00
|
|
|
void MipsAsmPrinter::
|
|
|
|
printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
|
|
|
// when using stack locations for not load/store instructions
|
|
|
|
// print the same way as all normal 3 operand instructions.
|
|
|
|
printOperand(MI, opNum, O);
|
|
|
|
O << ", ";
|
|
|
|
printOperand(MI, opNum+1, O);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
void MipsAsmPrinter::
|
2010-04-04 04:47:45 +00:00
|
|
|
printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
|
|
|
|
const char *Modifier) {
|
2012-06-14 21:10:56 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
2011-03-04 17:51:39 +00:00
|
|
|
O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
2009-09-30 22:06:26 +00:00
|
|
|
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
|
2013-06-18 19:47:15 +00:00
|
|
|
// TODO: Need to add -mabicalls and -mno-abicalls flags.
|
|
|
|
// Currently we assume that -mabicalls is the default.
|
2014-04-16 13:58:57 +00:00
|
|
|
bool IsABICalls = true;
|
|
|
|
if (IsABICalls) {
|
|
|
|
getTargetStreamer().emitDirectiveAbiCalls();
|
2014-07-18 00:08:53 +00:00
|
|
|
Reloc::Model RM = TM.getRelocationModel();
|
2014-04-16 13:58:57 +00:00
|
|
|
// FIXME: This condition should be a lot more complicated that it is here.
|
|
|
|
// Ideally it should test for properties of the ABI and not the ABI
|
|
|
|
// itself.
|
|
|
|
// For the moment, I'm only correcting enough to make MIPS-IV work.
|
|
|
|
if (RM == Reloc::Static && !Subtarget->isABI_N64())
|
|
|
|
getTargetStreamer().emitDirectiveOptionPic0();
|
|
|
|
}
|
2013-06-18 19:47:15 +00:00
|
|
|
|
2008-07-14 14:42:54 +00:00
|
|
|
// Tell the assembler which ABI we are using
|
2014-01-27 01:33:33 +00:00
|
|
|
std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
|
|
|
|
OutStreamer.SwitchSection(OutContext.getELFSection(
|
|
|
|
SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
|
2008-07-14 14:42:54 +00:00
|
|
|
|
2014-04-16 15:48:55 +00:00
|
|
|
// NaN: At the moment we only support:
|
|
|
|
// 1. .nan legacy (default)
|
|
|
|
// 2. .nan 2008
|
|
|
|
Subtarget->isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
|
|
|
|
: getTargetStreamer().emitDirectiveNaNLegacy();
|
|
|
|
|
2008-07-14 14:42:54 +00:00
|
|
|
// TODO: handle O64 ABI
|
|
|
|
|
2014-01-27 01:33:33 +00:00
|
|
|
if (Subtarget->isABI_EABI()) {
|
|
|
|
if (Subtarget->isGP32bit())
|
|
|
|
OutStreamer.SwitchSection(
|
|
|
|
OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
|
|
|
|
SectionKind::getDataRel()));
|
|
|
|
else
|
|
|
|
OutStreamer.SwitchSection(
|
|
|
|
OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
|
|
|
|
SectionKind::getDataRel()));
|
|
|
|
}
|
2014-07-10 13:38:23 +00:00
|
|
|
|
2014-07-08 08:59:22 +00:00
|
|
|
getTargetStreamer().updateABIInfo(*Subtarget);
|
2014-07-21 15:25:24 +00:00
|
|
|
|
|
|
|
// We should always emit a '.module fp=...' but binutils 2.24 does not accept
|
|
|
|
// it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
|
|
|
|
// -mfp64) and omit it otherwise.
|
|
|
|
if (Subtarget->isABI_O32() && (Subtarget->isABI_FPXX() ||
|
|
|
|
Subtarget->isFP64bit()))
|
|
|
|
getTargetStreamer().emitDirectiveModuleFP();
|
|
|
|
|
|
|
|
// We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
|
|
|
|
// accept it. We therefore emit it when it contradicts the default or an
|
|
|
|
// option has changed the default (i.e. FPXX) and omit it otherwise.
|
|
|
|
if (Subtarget->isABI_O32() && (!Subtarget->useOddSPReg() ||
|
|
|
|
Subtarget->isABI_FPXX()))
|
|
|
|
getTargetStreamer().emitDirectiveModuleOddSPReg(Subtarget->useOddSPReg(),
|
|
|
|
Subtarget->isABI_O32());
|
2014-02-14 19:16:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
|
|
|
|
MCInst I;
|
|
|
|
I.setOpcode(Mips::JAL);
|
|
|
|
I.addOperand(
|
|
|
|
MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
|
|
|
|
OutStreamer.EmitInstruction(I, getSubtargetInfo());
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
|
|
|
|
MCInst I;
|
|
|
|
I.setOpcode(Opcode);
|
|
|
|
I.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
OutStreamer.EmitInstruction(I, getSubtargetInfo());
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
|
|
|
|
unsigned Reg2) {
|
|
|
|
MCInst I;
|
|
|
|
//
|
|
|
|
// Because of the current td files for Mips32, the operands for MTC1
|
|
|
|
// appear backwards from their normal assembly order. It's not a trivial
|
|
|
|
// change to fix this in the td file so we adjust for it here.
|
|
|
|
//
|
|
|
|
if (Opcode == Mips::MTC1) {
|
|
|
|
unsigned Temp = Reg1;
|
|
|
|
Reg1 = Reg2;
|
|
|
|
Reg2 = Temp;
|
|
|
|
}
|
|
|
|
I.setOpcode(Opcode);
|
|
|
|
I.addOperand(MCOperand::CreateReg(Reg1));
|
|
|
|
I.addOperand(MCOperand::CreateReg(Reg2));
|
|
|
|
OutStreamer.EmitInstruction(I, getSubtargetInfo());
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
|
|
|
|
unsigned Reg2, unsigned Reg3) {
|
|
|
|
MCInst I;
|
|
|
|
I.setOpcode(Opcode);
|
|
|
|
I.addOperand(MCOperand::CreateReg(Reg1));
|
|
|
|
I.addOperand(MCOperand::CreateReg(Reg2));
|
|
|
|
I.addOperand(MCOperand::CreateReg(Reg3));
|
|
|
|
OutStreamer.EmitInstruction(I, getSubtargetInfo());
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
|
|
|
|
unsigned Reg2, unsigned FPReg1,
|
|
|
|
unsigned FPReg2, bool LE) {
|
|
|
|
if (!LE) {
|
|
|
|
unsigned temp = Reg1;
|
|
|
|
Reg1 = Reg2;
|
|
|
|
Reg2 = temp;
|
|
|
|
}
|
|
|
|
EmitInstrRegReg(MovOpc, Reg1, FPReg1);
|
|
|
|
EmitInstrRegReg(MovOpc, Reg2, FPReg2);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
|
|
|
|
bool LE, bool ToFP) {
|
|
|
|
using namespace Mips16HardFloatInfo;
|
|
|
|
unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
|
|
|
|
switch (PV) {
|
|
|
|
case FSig:
|
|
|
|
EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
|
|
|
|
break;
|
|
|
|
case FFSig:
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
|
|
|
|
break;
|
|
|
|
case FDSig:
|
|
|
|
EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
|
|
|
|
break;
|
|
|
|
case DSig:
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
|
|
|
|
break;
|
|
|
|
case DDSig:
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
|
|
|
|
break;
|
|
|
|
case DFSig:
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
|
|
|
|
EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
|
|
|
|
break;
|
|
|
|
case NoSig:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
|
|
|
|
bool LE) {
|
|
|
|
using namespace Mips16HardFloatInfo;
|
|
|
|
unsigned MovOpc = Mips::MFC1;
|
|
|
|
switch (RV) {
|
|
|
|
case FRet:
|
|
|
|
EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
|
|
|
|
break;
|
|
|
|
case DRet:
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
|
|
|
|
break;
|
|
|
|
case CFRet:
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
|
|
|
|
break;
|
|
|
|
case CDRet:
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
|
|
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
|
|
|
|
break;
|
|
|
|
case NoFPRet:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2013-01-18 21:20:38 +00:00
|
|
|
|
2014-02-14 19:16:39 +00:00
|
|
|
void MipsAsmPrinter::EmitFPCallStub(
|
|
|
|
const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
|
|
|
|
MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
|
|
|
|
using namespace Mips16HardFloatInfo;
|
|
|
|
bool LE = Subtarget->isLittle();
|
|
|
|
//
|
|
|
|
// .global xxxx
|
|
|
|
//
|
|
|
|
OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
|
|
|
|
const char *RetType;
|
|
|
|
//
|
|
|
|
// make the comment field identifying the return and parameter
|
|
|
|
// types of the floating point stub
|
|
|
|
// # Stub function to call rettype xxxx (params)
|
|
|
|
//
|
|
|
|
switch (Signature->RetSig) {
|
|
|
|
case FRet:
|
|
|
|
RetType = "float";
|
|
|
|
break;
|
|
|
|
case DRet:
|
|
|
|
RetType = "double";
|
|
|
|
break;
|
|
|
|
case CFRet:
|
|
|
|
RetType = "complex";
|
|
|
|
break;
|
|
|
|
case CDRet:
|
|
|
|
RetType = "double complex";
|
|
|
|
break;
|
|
|
|
case NoFPRet:
|
|
|
|
RetType = "";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
const char *Parms;
|
|
|
|
switch (Signature->ParamSig) {
|
|
|
|
case FSig:
|
|
|
|
Parms = "float";
|
|
|
|
break;
|
|
|
|
case FFSig:
|
|
|
|
Parms = "float, float";
|
|
|
|
break;
|
|
|
|
case FDSig:
|
|
|
|
Parms = "float, double";
|
|
|
|
break;
|
|
|
|
case DSig:
|
|
|
|
Parms = "double";
|
|
|
|
break;
|
|
|
|
case DDSig:
|
|
|
|
Parms = "double, double";
|
|
|
|
break;
|
|
|
|
case DFSig:
|
|
|
|
Parms = "double, float";
|
|
|
|
break;
|
|
|
|
case NoSig:
|
|
|
|
Parms = "";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
|
|
|
|
Twine(Symbol) + " (" + Twine(Parms) + ")");
|
|
|
|
//
|
|
|
|
// probably not necessary but we save and restore the current section state
|
|
|
|
//
|
|
|
|
OutStreamer.PushSection();
|
|
|
|
//
|
|
|
|
// .section mips16.call.fpxxxx,"ax",@progbits
|
|
|
|
//
|
|
|
|
const MCSectionELF *M = OutContext.getELFSection(
|
|
|
|
".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
|
|
|
|
ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
|
2014-04-25 05:30:21 +00:00
|
|
|
OutStreamer.SwitchSection(M, nullptr);
|
2014-02-14 19:16:39 +00:00
|
|
|
//
|
|
|
|
// .align 2
|
|
|
|
//
|
|
|
|
OutStreamer.EmitValueToAlignment(4);
|
|
|
|
MipsTargetStreamer &TS = getTargetStreamer();
|
|
|
|
//
|
|
|
|
// .set nomips16
|
|
|
|
// .set nomicromips
|
|
|
|
//
|
|
|
|
TS.emitDirectiveSetNoMips16();
|
|
|
|
TS.emitDirectiveSetNoMicroMips();
|
|
|
|
//
|
|
|
|
// .ent __call_stub_fp_xxxx
|
2014-07-08 08:59:22 +00:00
|
|
|
// .type __call_stub_fp_xxxx,@function
|
2014-02-14 19:16:39 +00:00
|
|
|
// __call_stub_fp_xxxx:
|
|
|
|
//
|
|
|
|
std::string x = "__call_stub_fp_" + std::string(Symbol);
|
|
|
|
MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
|
|
|
|
TS.emitDirectiveEnt(*Stub);
|
|
|
|
MCSymbol *MType =
|
|
|
|
OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
|
|
|
|
OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
|
|
|
|
OutStreamer.EmitLabel(Stub);
|
|
|
|
//
|
|
|
|
// we just handle non pic for now. these function will not be
|
|
|
|
// called otherwise. when the full stub generation is moved here
|
|
|
|
// we need to deal with pic.
|
|
|
|
//
|
|
|
|
if (Subtarget->getRelocationModel() == Reloc::PIC_)
|
|
|
|
llvm_unreachable("should not be here if we are compiling pic");
|
|
|
|
TS.emitDirectiveSetReorder();
|
|
|
|
//
|
|
|
|
// We need to add a MipsMCExpr class to MCTargetDesc to fully implement
|
|
|
|
// stubs without raw text but this current patch is for compiler generated
|
|
|
|
// functions and they all return some value.
|
|
|
|
// The calling sequence for non pic is different in that case and we need
|
|
|
|
// to implement %lo and %hi in order to handle the case of no return value
|
|
|
|
// See the corresponding method in Mips16HardFloat for details.
|
|
|
|
//
|
|
|
|
// mov the return address to S2.
|
|
|
|
// we have no stack space to store it and we are about to make another call.
|
|
|
|
// We need to make sure that the enclosing function knows to save S2
|
|
|
|
// This should have already been handled.
|
|
|
|
//
|
|
|
|
// Mov $18, $31
|
|
|
|
|
|
|
|
EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
|
|
|
|
|
|
|
|
EmitSwapFPIntParams(Signature->ParamSig, LE, true);
|
|
|
|
|
|
|
|
// Jal xxxx
|
|
|
|
//
|
|
|
|
EmitJal(MSymbol);
|
|
|
|
|
|
|
|
// fix return values
|
|
|
|
EmitSwapFPIntRetval(Signature->RetSig, LE);
|
|
|
|
//
|
|
|
|
// do the return
|
|
|
|
// if (Signature->RetSig == NoFPRet)
|
|
|
|
// llvm_unreachable("should not be any stubs here with no return value");
|
|
|
|
// else
|
|
|
|
EmitInstrReg(Mips::JR, Mips::S2);
|
|
|
|
|
|
|
|
MCSymbol *Tmp = OutContext.CreateTempSymbol();
|
|
|
|
OutStreamer.EmitLabel(Tmp);
|
|
|
|
const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
|
|
|
|
const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
|
|
|
|
const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
|
|
|
|
OutStreamer.EmitELFSize(Stub, T_min_E);
|
|
|
|
TS.emitDirectiveEnd(x);
|
|
|
|
OutStreamer.PopSection();
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
|
|
|
// Emit needed stubs
|
|
|
|
//
|
|
|
|
for (std::map<
|
|
|
|
const char *,
|
|
|
|
const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
|
|
|
|
it = StubsNeeded.begin();
|
|
|
|
it != StubsNeeded.end(); ++it) {
|
|
|
|
const char *Symbol = it->first;
|
|
|
|
const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
|
|
|
|
EmitFPCallStub(Symbol, Signature);
|
|
|
|
}
|
2014-01-27 01:33:33 +00:00
|
|
|
// return to the text section
|
|
|
|
OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
|
2013-01-18 21:20:38 +00:00
|
|
|
}
|
|
|
|
|
2011-07-01 01:04:43 +00:00
|
|
|
void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
|
|
|
|
raw_ostream &OS) {
|
|
|
|
// TODO: implement
|
|
|
|
}
|
|
|
|
|
2014-02-28 10:00:38 +00:00
|
|
|
// Align all targets of indirect branches on bundle size. Used only if target
|
|
|
|
// is NaCl.
|
|
|
|
void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
|
|
|
|
// Align all blocks that are jumped to through jump table.
|
|
|
|
if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
|
|
|
|
const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
|
|
|
|
for (unsigned I = 0; I < JT.size(); ++I) {
|
|
|
|
const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
|
|
|
|
|
|
|
|
for (unsigned J = 0; J < MBBs.size(); ++J)
|
|
|
|
MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If basic block address is taken, block can be target of indirect branch.
|
|
|
|
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
|
|
|
|
MBB != E; ++MBB) {
|
|
|
|
if (MBB->hasAddressTaken())
|
|
|
|
MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-30 15:06:25 +00:00
|
|
|
bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
|
|
|
|
return (Opcode == Mips::LONG_BRANCH_LUi
|
|
|
|
|| Opcode == Mips::LONG_BRANCH_ADDiu
|
|
|
|
|| Opcode == Mips::LONG_BRANCH_DADDiu);
|
|
|
|
}
|
|
|
|
|
2009-06-23 23:59:40 +00:00
|
|
|
// Force static initialization.
|
2011-03-04 17:51:39 +00:00
|
|
|
extern "C" void LLVMInitializeMipsAsmPrinter() {
|
2009-07-25 06:49:55 +00:00
|
|
|
RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
|
|
|
|
RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
|
2011-09-21 03:00:58 +00:00
|
|
|
RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
|
|
|
|
RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
|
2009-07-15 20:24:03 +00:00
|
|
|
}
|