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Author SHA1 Message Date
Dan Gohman
3112581441 Arithmetic instructions don't set EFLAGS bits OF and CF bits 
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66318 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-07 01:58:32 +00:00
Dan Gohman
16e8eda4b8 Fix ScheduleDAGRRList::CopyAndMoveSuccessors' handling of nodes 
with multiple chain operands. This can occur when the scheduler
has added chain operands to a node that already has a chain
operand, in order to handle physical register dependencies.

This fixes an llvm-gcc bootstrap failure on x86-64 introduced
in r66058.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66240 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-06 02:23:01 +00:00
Dan Gohman
4bfcf2a2a6 Fix the "test" optimization to recognize "dec" as an add of 
negative one, as subtracts of immediates are canonicalized
to adds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66180 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-05 19:32:48 +00:00
Dan Gohman
8733db351a Make this test more thorough. Not only should there be no %esi, 
there should be no spilling of anything.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66179 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-05 19:31:32 +00:00
Evan Cheng
6fb8f421ee Do not split edges to EH landing pads. It will cause code size explosion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66140 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-05 06:31:26 +00:00
Dan Gohman
076aee32e8 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66058 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 19:44:21 +00:00
Owen Anderson
c93023a89e Add a restore folder, which shaves a dozen or so machineinstrs off oggenc. Update a testcase to check this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66029 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 08:52:31 +00:00
Evan Cheng
ae3f2b6c77 Fix PR3666: isel calls to constant addresses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 06:48:53 +00:00
Eli Friedman
27759f41ca PR3686: make the legalizer handle bitcast from i80 to x86 long double. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66021 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 06:23:34 +00:00
Dan Gohman
29582d1223 Revert r66004 for now; it's causing a variety of test failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66008 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 03:54:19 +00:00
Evan Cheng
10029df79a Rename test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 02:47:25 +00:00
Dan Gohman
12bbc52aa7 Teach the x86 backend to eliminate "test" instructions by using the EFLAGS 
result from add, sub, inc, and dec instructions in simple cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66004 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 02:33:24 +00:00
Evan Cheng
599a6a88ce Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 01:41:49 +00:00
Bill Wendling
36ae6c1827 The DAG combiner was performing a BT combine. The BT combine had a value of -1, 
so it changed it into a 31 via the TLO.ShrinkDemandedConstant() call. Then it
would go through the DAG combiner again. This time it had a value of 31, which
was turned into a -1 by TLI.SimplifyDemandedBits(). This would ping pong
forever.

Teach the TLO.ShrinkDemandedConstant() call not to lower a value if the demanded
value is an XOR of all ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65985 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 00:18:06 +00:00
Nate Begeman
cbd88adea6 Fix a problem with DAGCombine on 64b targets where folding 
extracts + build_vector into a shuffle would fail, because the
type of the new build_vector would not be legal.  Try harder to
create a legal build_vector type.  Note: this will be totally 
irrelevant once vector_shuffle no longer takes a build_vector for
shuffle mask.

New:
_foo:
	xorps	%xmm0, %xmm0
	xorps	%xmm1, %xmm1
	subps	%xmm1, %xmm1
	mulps	%xmm0, %xmm1
	addps	%xmm0, %xmm1
	movaps	%xmm1, 0

Old:
_foo:
	xorps	%xmm0, %xmm0
	movss	%xmm0, %xmm1
	xorps	%xmm2, %xmm2
	unpcklps	%xmm1, %xmm2
	pshufd	$80, %xmm1, %xmm1
	unpcklps	%xmm1, %xmm2
	pslldq	$16, %xmm2
	pshufd	$57, %xmm2, %xmm1
	subps	%xmm0, %xmm1
	mulps	%xmm0, %xmm1
	addps	%xmm0, %xmm1
	movaps	%xmm1, 0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65791 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-01 23:44:07 +00:00
Evan Cheng
870b80722f Minor optimization: 
Look for situations like this:                                                                                                                                                              
%reg1024<def> = MOV r1                                                                                                                                                                      
%reg1025<def> = MOV r0                                                                                                                                                                      
%reg1026<def> = ADD %reg1024, %reg1025                                                                                                                                                      
r0            = MOV %reg1026                                                                                                                                                                
Commute the ADD to hopefully eliminate an otherwise unavoidable copy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65752 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-01 02:03:43 +00:00
Rafael Espindola
9a58023c6c Refactor TLS code and add some tests. The tests and expected results are: 
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-27 13:37:18 +00:00
Evan Cheng
98f122fc40 Make sure this test passes on linux-ppc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-27 00:51:50 +00:00
Evan Cheng
efc783951c MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65592 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-27 00:02:22 +00:00
Evan Cheng
236aa8a503 ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65499 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-26 03:12:02 +00:00
Evan Cheng
a87008d90b Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65482 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-25 22:49:59 +00:00
Dan Gohman
e9865945ad Fast-isel can't do TLS yet, so it should fall back to SDISel 
if it sees TLS addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65341 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-23 22:03:08 +00:00
Dan Gohman
834db732ba Use the -stack-alignment option instead of using a target triple 
for avoiding dynamic stack realignment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65319 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-23 16:34:46 +00:00
Evan Cheng
242b38bae5 Only v1i16 (i.e. _m64) is returned via RAX / RDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65313 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-23 09:03:22 +00:00
Nate Begeman
932be21c08 Make this test use darwin targe triple, to avoid stack traffic on linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65312 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-23 09:03:06 +00:00
Nate Begeman
b9a47b824f Generate better code for v8i16 shuffles on SSE2 
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
  cleanups.
New tests that test the above.

Examples:

New:
_shuf2:
	pextrw	$7, %xmm0, %eax
	punpcklqdq	%xmm1, %xmm0
	pshuflw	$128, %xmm0, %xmm0
	pinsrw	$2, %eax, %xmm0

Old:
_shuf2:
	pextrw	$2, %xmm0, %eax
	pextrw	$7, %xmm0, %ecx
	pinsrw	$2, %ecx, %xmm0
	pinsrw	$3, %eax, %xmm0
	movd	%xmm1, %eax
	pinsrw	$4, %eax, %xmm0
	ret

=========

New:
_shuf4:
	punpcklqdq	%xmm1, %xmm0
	pshufb	LCPI1_0, %xmm0

Old:
_shuf4:
	pextrw	$3, %xmm0, %eax
	movsd	%xmm1, %xmm0
	pextrw	$3, %xmm1, %ecx
	pinsrw	$4, %ecx, %xmm0
	pinsrw	$5, %eax, %xmm0

========

New:
_shuf1:
	pushl	%ebx
	pushl	%edi
	pushl	%esi
	pextrw	$1, %xmm0, %eax
	rolw	$8, %ax
	movd	%xmm0, %ecx
	rolw	$8, %cx
	pextrw	$5, %xmm0, %edx
	pextrw	$4, %xmm0, %esi
	pextrw	$3, %xmm0, %edi
	pextrw	$2, %xmm0, %ebx
	movaps	%xmm0, %xmm1
	pinsrw	$0, %ecx, %xmm1
	pinsrw	$1, %eax, %xmm1
	rolw	$8, %bx
	pinsrw	$2, %ebx, %xmm1
	rolw	$8, %di
	pinsrw	$3, %edi, %xmm1
	rolw	$8, %si
	pinsrw	$4, %esi, %xmm1
	rolw	$8, %dx
	pinsrw	$5, %edx, %xmm1
	pextrw	$7, %xmm0, %eax
	rolw	$8, %ax
	movaps	%xmm1, %xmm0
	pinsrw	$7, %eax, %xmm0
	popl	%esi
	popl	%edi
	popl	%ebx
	ret

Old:
_shuf1:
	subl	$252, %esp
	movaps	%xmm0, (%esp)
	movaps	%xmm0, 16(%esp)
	movaps	%xmm0, 32(%esp)
	movaps	%xmm0, 48(%esp)
	movaps	%xmm0, 64(%esp)
	movaps	%xmm0, 80(%esp)
	movaps	%xmm0, 96(%esp)
	movaps	%xmm0, 224(%esp)
	movaps	%xmm0, 208(%esp)
	movaps	%xmm0, 192(%esp)
	movaps	%xmm0, 176(%esp)
	movaps	%xmm0, 160(%esp)
	movaps	%xmm0, 144(%esp)
	movaps	%xmm0, 128(%esp)
	movaps	%xmm0, 112(%esp)
	movzbl	14(%esp), %eax
	movd	%eax, %xmm1
	movzbl	22(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	42(%esp), %eax
	movd	%eax, %xmm1
	movzbl	50(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm1, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	77(%esp), %eax
	movd	%eax, %xmm1
	movzbl	84(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	104(%esp), %eax
	movd	%eax, %xmm1
	punpcklbw	%xmm1, %xmm0
	punpcklbw	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	punpcklbw	%xmm3, %xmm1
	movzbl	127(%esp), %eax
	movd	%eax, %xmm0
	movzbl	135(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	155(%esp), %eax
	movd	%eax, %xmm0
	movzbl	163(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm0, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	188(%esp), %eax
	movd	%eax, %xmm0
	movzbl	197(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	217(%esp), %eax
	movd	%eax, %xmm4
	movzbl	225(%esp), %eax
	movd	%eax, %xmm0
	punpcklbw	%xmm4, %xmm0
	punpcklbw	%xmm2, %xmm0
	punpcklbw	%xmm3, %xmm0
	punpcklbw	%xmm1, %xmm0
	addl	$252, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65311 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-23 08:49:38 +00:00
Scott Michel
4214a5531c Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR 
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-22 23:36:09 +00:00
Evan Cheng
6140a8b057 Be bug compatible with gcc by returning MMX values in RAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65274 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-22 08:05:12 +00:00
Anton Korobeynikov
b5bd026a75 Drop bunch of half-working stuff in the ext_weak linkage support. 
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).

The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65230 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-21 11:53:32 +00:00
Evan Cheng
28c7ce3fd4 If two-address def is dead and the instruction does not define other registers, and it doesn't produce side effects, just delete the instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-21 03:14:25 +00:00
Evan Cheng
d9fb712403 Teach LSR sink to sink the immediate portion of the common expression back into uses if they fit in address modes of all the uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65215 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-21 02:06:47 +00:00
Evan Cheng
d33cec18a9 Fix strange logic in CollectIVUsers used to determine whether all uses are 
addresses, part 1. This fixes an obvious logic bug. Previously if the only
in-loop use is a PHI, it would return AllUsesAreAddresses as true.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65178 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-20 22:16:49 +00:00
Evan Cheng
79fb3b434f Support return of MMX values in 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65152 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-20 20:43:02 +00:00
Owen Anderson
4cafbb58e2 Fix a crash in the pre-alloc splitter exposed by recent codegen changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65121 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-20 10:02:23 +00:00
Chris Lattner
e772842505 make these tests pass when run on a G5. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65117 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-20 07:10:11 +00:00
Dan Gohman
c17e0cf6c0 Implement "superhero" strength reduction, or full strength 
reduction of address calculations down to basic pointer arithmetic.
This is currently off by default, as it needs a few other features
before it becomes generally useful. And even when enabled, full
strength reduction is only performed when it doesn't increase
register pressure, and when several other conditions are true.

This also factors out a bunch of exisiting LSR code out of
StrengthReduceStridedIVUsers into separate functions, and tidies
up IV insertion. This actually decreases register pressure even
in non-superhero mode. The change in iv-users-in-other-loops.ll
is an example of this; there are two more adds because there are
two fewer leas, and there is less spilling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65108 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-20 04:17:46 +00:00
Evan Cheng
caa0c2cadd GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64877 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-18 02:19:52 +00:00
Dan Gohman
926b0a27b9 Change these tests to use regular loads instead of llvm.x86.sse2.loadu.dq. 
Enhance instcombine to use the preferred field of
GetOrEnforceKnownAlignment in more cases, so that regular IR operations are
optimized in the same way that the intrinsics currently are.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64623 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-16 00:44:23 +00:00
Evan Cheng
b599979ab5 Fix PR3522. It's not safe to sink into landing pad BB's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-15 08:36:12 +00:00
Evan Cheng
c7ce29b04f Teach x86 target -soft-float. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64496 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-13 22:36:38 +00:00
Dan Gohman
9194e8b0c8 Fix the code that checked if a SCEVAddRecExpr Start contains an 
addrec in a different loop to check the value being added to
the accumulated Start value, not the Start value before it has
the new value added to it. This prevents LSR from going crazy
on the included testcase. Dale, please review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64440 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-13 03:58:31 +00:00
Dan Gohman
bc511725f0 Fix LSR's IV sorting function to explicitly sort by bitwidth 
after sorting by stride value. This prevents it from missing
IV reuse opportunities in a host-sensitive manner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64415 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-13 00:26:43 +00:00
Dale Johannesen
78e3e521cd Arrange to print constants that match "n" and "i" constraints 
in inline asm as signed (what gcc does).  Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64400 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 20:58:09 +00:00
Chris Lattner
1823c92aa7 fix the X86 backend to just drop llvm.declare nodes for VLAs instead of 
leaving them in the DAG and then getting selection errors.  This is a 
fix for PR3538.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64382 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 17:33:11 +00:00
Chris Lattner
327e98fae1 add PR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64377 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 17:04:57 +00:00
Evan Cheng
8679119f4b It's (currently) not safe to keep certain physical registers live across basic blocks, e.g. x86 fp stack registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64374 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 10:32:17 +00:00
Evan Cheng
8182347d70 Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64369 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 08:59:45 +00:00
Chris Lattner
65c02fbf9b fix PR3537: if resetting bbi back to the start of a block, we need to 
forget about already inserted expressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 06:56:08 +00:00
Chris Lattner
afa77434bb rename test to avoid messing with tab completion of dates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 06:54:55 +00:00
Evan Cheng
ce7f5a1e50 Remove a bogus assertion. It's possible a live-in available value is used by a previous instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64339 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-11 23:41:57 +00:00
Dan Gohman
c8db34cb07 Don't use special heuristics for nodes with no data predecessors 
unless they actually have data successors, and likewise for nodes
with no data successors unless they actually have data precessors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64327 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-11 21:29:39 +00:00
Dale Johannesen
85b0edec46 Make a transformation added in 63266 a bit less aggressive. 
It was transforming (x&y)==y to (x&y)!=0 in the case where
y is variable and known to have at most one bit set (e.g. z&1).
This is not correct; the expressions are not equivalent when y==0.
I believe this patch salvages what can be salvaged, including
all the cases in bt.ll.  Dan, please review.
Fixes gcc.c-torture/execute/20040709-[12].c



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64314 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-11 19:19:41 +00:00
Evan Cheng
752272a5e5 Implement PR3495: local spiller optimization. The local spiller can now keep availability information over BB boundaries. It visits BB's in depth first order. After visiting a BB if it find a successor which has a single predecessor it visits the successor next without clearing the availability information. This allows the successor to omit reloads or change them into copies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64298 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-11 08:24:21 +00:00
Evan Cheng
1d76864df3 Handle llvm.x86.sse2.maskmov.dqu in 64-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64240 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-10 22:06:28 +00:00
Evan Cheng
f0e366a929 Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64210 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-10 08:30:11 +00:00
Evan Cheng
a0eedac226 Implement FpSET_ST1_*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64186 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-09 23:32:07 +00:00
Evan Cheng
b1032a8a2f Make sure constant subscript is truncated to ptr size if it may not fit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64163 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-09 20:54:38 +00:00
Evan Cheng
8f0d99e463 Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64126 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-09 08:45:39 +00:00
Evan Cheng
0a1fcce092 Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64082 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-08 11:04:35 +00:00
Evan Cheng
77fde2cbb1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64073 91177308-0d34-0410-b5e6-96231b3b80d8 2009-02-08 07:48:37 +00:00
Bill Wendling
7f51fd3ea9 Revert r63999. It was breaking self-hosting builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64062 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-08 00:58:05 +00:00
Evan Cheng
c963b638c7 Enable machine sinking pass in non-fast mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63999 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-07 01:57:46 +00:00
Evan Cheng
77402d1dbf Fix test. It produces unexpected code if sse4.1 is on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63906 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-06 01:49:19 +00:00
Evan Cheng
54801f78b1 isAsCheapAsMove instructions can have register src operands. Check if they are really re-materializable. 
This fixes sse.expandfft and sse.stepfft.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63890 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-05 22:24:17 +00:00
Evan Cheng
c5d1a4ffd9 Turn on machine LICM in non-fast mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63855 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-05 08:46:33 +00:00
Chris Lattner
4798bbeaf5 if we have a large GEP offset on a 32-bit or other target, make 
sure to print the value properly sext'd to the right pointer size.
This fixes PR3481.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-05 06:55:21 +00:00
Mon P Wang
4781ad62d1 Add test case for r63760. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63774 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-04 21:10:56 +00:00
Mon P Wang
7bcaefaf59 Fixes a case where we generate an incorrect mask for pshfhw in the presence 
of undefs and incorrectly determining if we have punpckldq.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63702 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-04 01:16:59 +00:00
Duncan Sands
95c5f05641 Fix PR3411. When replacing values, nodes are analyzed 
in any old order.  Since analyzing a node analyzes its
operands also, this can mean that when we pop a node
off the list of nodes to be analyzed, it may already
have been analyzed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-03 10:23:33 +00:00
Chris Lattner
7809ecd5b0 rearrange how SRoA handles promotion of allocas to vectors. 
With the new world order, it can handle cases where the first
store into the alloca is an element of the vector, instead of
requiring the first analyzed store to have the vector type 
itself.  This allows us to un-xfail 
test/CodeGen/X86/vec_ins_extract.ll.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-03 01:30:09 +00:00
Dan Gohman
7a01d0e971 Add explicit -march=x86 to these tests so that they don't 
default to -march=x86-64 on 64-bit hosts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63579 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-03 00:20:22 +00:00
Dan Gohman
2ee39de7b6 Fix another test to not use -mcpu=yonah with 64-bit code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-02 23:43:59 +00:00
Dan Gohman
e7f5be7d71 Yonah does not support x86-64. Change the -mcpu value to one that does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63561 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-02 22:50:08 +00:00
Chris Lattner
3f9495a3f7 xfail this for now, will fix shortly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63533 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-02 18:15:33 +00:00
Evan Cheng
67ad9db15b Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63505 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-02 08:07:36 +00:00
Torok Edwin
0c3c0214bc add 2 more testcases for -mattr=-sse (r63495). 
--This line, and those below, will be ignaored--

A    test/CodeGen/X86/nosse-error1.ll
A    test/CodeGen/X86/nosse-error2.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63496 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-01 18:24:20 +00:00
Torok Edwin
3f142c36ad Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for 
var-args, and don't allow FP return values


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63495 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-01 18:15:56 +00:00
Duncan Sands
b0d5cdd52e Fix PR3453 and probably a bunch of other potential 
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-01 18:06:53 +00:00
Duncan Sands
92abc62399 Fix PR3401: when using large integers, the type 
returned by getShiftAmountTy may be too small
to hold shift values (it is an i8 on x86-32).
Before and during type legalization, use a large
but legal type for shift amounts: getPointerTy;
afterwards use getShiftAmountTy, fixing up any
shift amounts with a big type during operation
legalization.  Thanks to Dan for writing the
original patch (which I shamelessly pillaged).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63482 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-31 15:50:11 +00:00
Mon P Wang
a7b6cff99f If unsafe FP optimization is not set, don't allow -(A-B) => B-A because 
when A==B, -0.0 != +0.0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63474 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-31 06:07:45 +00:00
Owen Anderson
af399a6ffe XFAIL this test. It only worked before because of a bug in the spill point selection code. Not deleting because 
it should be possible to enhance the selection code to handle this in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63340 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 22:27:56 +00:00
Evan Cheng
d5a4802708 Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63323 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 18:37:30 +00:00
Dan Gohman
197e88f796 In the case of an extractelement on an insertelement value, 
the element indices may be equal if either one is not a
constant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63311 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 16:10:46 +00:00
Evan Cheng
5a3c6a87b0 Exit with nice warnings when register allocator run out of registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63267 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 02:20:59 +00:00
Dan Gohman
e5af2d3a22 Make x86's BT instruction matching more thorough, and add some 
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 01:59:02 +00:00
Mon P Wang
e91a000889 Fixed lowering of v816 shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-28 23:11:14 +00:00
Bill Wendling
7540561097 Make test platform agnostic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63247 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-28 22:20:56 +00:00
Evan Cheng
1632782fe9 The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63195 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-28 08:35:02 +00:00
Mon P Wang
f4646d9902 Added sse test patterns for r62979 and r63193. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63194 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-28 08:13:56 +00:00
Bill Wendling
ac7de20a49 Add testcase for r63142. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63149 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 23:00:53 +00:00
Evan Cheng
6a86bd71df Implement multiple with overflow by 2 with an add instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63090 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 03:30:42 +00:00
Dan Gohman
4e1fae5125 Add a regression test for x86-64 red zone usage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63075 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 00:40:27 +00:00
Duncan Sands
5bb11b89dd Fix PR3393, which amounts to a bug in the expensive 
checking logic.  Rather than make the checking more
complicated, I've tweaked some logic to make things
conform to how the checking thought things ought to
be, since this results in a simpler "mental model".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 21:54:18 +00:00
Dan Gohman
4699934647 At Nick Lewycky's request, rename this test with a more informative name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 21:36:31 +00:00
Evan Cheng
5b2e5893c6 Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63022 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 18:43:34 +00:00
Nate Begeman
51a0437b16 Map address space 256 to gs; similar mappings could be supported for the 
other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 01:24:32 +00:00
Torok Edwin
c8ad2d2abf revert this patch for now, because Codegen does still want to generate SSE code, 
for example in the case of va-args. XFAIL associated tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62972 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 20:21:24 +00:00
Torok Edwin
7f1d5252c7 If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62967 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 17:58:56 +00:00
Evan Cheng
d498c8f2c8 Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue. 
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1028                                                                                                                                            
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>                                                                                                         

In this case, it might not be possible to coalesce the second MOV8rr                                                                                                                 
instruction if the first one is coalesced. So it would be profitable to                                                                                                              
commute it:                                                                                                                                                                          
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1029                                                                                                                                            
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 03:53:59 +00:00
Dan Gohman
54e853a779 Add a PR comment to this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-24 17:32:54 +00:00
Evan Cheng
3e2351fa2a Update test to reflect command line option name change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62836 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-23 05:45:31 +00:00
Dan Gohman
760f86f339 Don't create ISD::FNEG nodes after legalize if they aren't legal. 
Simplify x+0 to x in unsafe-fp-math mode. This avoids a bunch of
redundant work in many cases, because in unsafe-fp-math mode,
ISD::FADD with a constant is considered free to negate, so the
DAGCombiner often negates x+0 to -0-x thinking it's free, when
in reality the end result is -x, which is more expensive than x.

Also, combine x*0 to 0.

This fixes PR3374.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62789 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 21:58:43 +00:00
Devang Patel
5e3c013f81 Do not use buggy llvm-gcc to generate testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62770 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 18:28:11 +00:00
Bill Wendling
708f5a8fb6 Now with RUN line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62716 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 21:28:03 +00:00
Bill Wendling
e3b014a05f Run this through -simplifycfg and -mem2reg to test only what we need to test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62714 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 21:02:27 +00:00
Dan Gohman
764fd0cbc8 Simplify ReduceLoadWidth's logic: it doesn't need several different 
special cases after producing the new reduced-width load, because the
new load already has the needed adjustments built into it. This fixes
several bugs due to the special cases, including PR3317.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62692 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 15:17:51 +00:00
Dan Gohman
1ef4d8f7ee Fix a recent regression. ClrOpcode is not set for i8; for i8, if 
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62691 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 14:50:16 +00:00
Evan Cheng
aaf414c92c Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62661 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 02:09:05 +00:00
Owen Anderson
6cf7c390ec Be more aggressive about renumbering vregs after splitting them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62639 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 00:13:28 +00:00
Evan Cheng
a894ae130b Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62617 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 21:25:12 +00:00
Evan Cheng
c99031b02a Add test case for PR3154. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62604 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 19:29:54 +00:00
Bill Wendling
20394494cc Testcase for limited precision stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 06:23:59 +00:00
Dan Gohman
f5add58549 Fix a dagcombine to not generate loads of non-round integer types, 
as its comment says, even in the case where it will be generating
extending loads. This fixes PR3216.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 01:06:45 +00:00
Evan Cheng
d0deec20f6 Make linear scan's trivial coalescer slightly more aggressive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62547 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 00:16:18 +00:00
Dale Johannesen
549170206e Move & restructure test per review. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62538 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 22:33:12 +00:00
Dan Gohman
dbe664adcd Fix SelectionDAG::ReplaceAllUsesWith to behave correctly when 
uses are added to the From node while it is processing From's
use list, because of automatic local CSE. The fix is to avoid
visiting any new uses.

Fix a few places in the DAGCombiner that assumed that after
a RAUW call, the From node has no users and may be deleted.

This fixes PR3018.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62533 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 21:44:21 +00:00
Dale Johannesen
1f54f58e64 compile-time fmod was done incorrectly. PR 3316. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62528 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 21:17:05 +00:00
Evan Cheng
2722e7b139 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 19:06:11 +00:00
Evan Cheng
a06ec9efe1 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62504 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 08:08:22 +00:00
Chris Lattner
d62284a804 Fix rdar://6505632, an llc crash on 483.xalancbmk 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62470 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-18 20:35:00 +00:00
Bill Wendling
959fb88949 Testcase for last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62418 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 07:42:44 +00:00
Evan Cheng
8e27826649 Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62413 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 07:09:27 +00:00
Mon P Wang
7ac9cdfc99 Simplify extract element of a scalar to vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62383 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 00:07:25 +00:00
Dan Gohman
3326f16036 Disable the post-RA scheduler on this test, since it uses a 
simple %prcontext which doesn't find what it's looking for
if the scheduler has rearranged the instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 21:40:12 +00:00
Evan Cheng
e57187cbe3 CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62356 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 20:57:18 +00:00
Bill Wendling
64e87326d9 Add support for non-zero __builtin_return_address values on X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62338 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 19:25:27 +00:00
Mon P Wang
fa9c5eac33 Added missing support to widen an operand from a bit convert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62285 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 22:43:38 +00:00
Mon P Wang
f0fcdd8e26 Expand insert/extract of a <4 x i32> with a variable index. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62281 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 21:10:20 +00:00
Rafael Espindola
bb46f52027 Add the private linkage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 20:18:42 +00:00
Dan Gohman
f31408d75c Disable the register+memory forms of the bt instructions for now. Thanks 
to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62194 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-13 23:23:30 +00:00
Duncan Sands
2ecf88d175 When replacing uses and the same node is reached 
via two paths, process it once not twice, d'oh!
Analysis, testcase and original patch thanks to
Mon Ping Wang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62169 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-13 15:17:14 +00:00
Evan Cheng
1d8a76d7d5 FIX llvm-gcc bootstrap on x86_64 linux. If a virtual register is copied to a physical register, it's not necessarily defined by a copy. We have to watch out it doesn't clobber any sub-register that might be live during its live interval. If the live interval crosses a basic block, then it's not safe to check with the less conservative check (by scanning uses and defs) because it's possible a sub-register might be live out of the block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62144 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-13 03:57:45 +00:00
Devang Patel
6fbbe4390b Use DebugInfo interface to lower dbg_* intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62126 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-13 00:32:17 +00:00
Evan Cheng
c29a56dedb Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. 
Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62074 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-12 03:19:55 +00:00
Evan Cheng
5c30667af9 This is a dup of pr2659.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62029 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-10 19:06:32 +00:00
Evan Cheng
5c3c5a4d9c Duplicated node may produce a non-physical register def. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62015 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-09 22:44:02 +00:00
Evan Cheng
0cb24f8131 Add test case from PR2659. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-09 21:01:31 +00:00
Dan Gohman
b24380804c PR2659 was fixed by r61847. Add the testcase as a regression test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-09 08:16:12 +00:00
Evan Cheng
8f90b6eb2f The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: 
v1024 = EDI  // not killed
      =
      = EDI

One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead.

This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61847 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-07 02:08:57 +00:00
Chris Lattner
d37eaa3b97 add a testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61845 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-07 01:48:08 +00:00
Dan Gohman
fbb7486560 Add patterns to match conditional moves with loads folded 
into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61842 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-07 01:00:24 +00:00
Dan Gohman
653456c351 X86_COND_C and X86_COND_NC are alternate mnemonics for 
X86_COND_B and X86_COND_AE, respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-07 00:15:08 +00:00
Dan Gohman
0a79a2f8b0 Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps 
avoid the need for spilling, add a new testcase that tests that the
pcmpeqd used for V_SETALLONES is changed to a constant-pool load as
needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61831 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-06 23:48:10 +00:00
Dan Gohman
cca2983291 Revert r42653 and forward-port the code that lets INC64_32r be 
converted to LEA64_32r in x86's convertToThreeAddress. This
replaces code like this:
   movl  %esi, %edi
   inc   %edi
with this:
   lea   1(%rsi), %edi
which appears to be beneficial.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61830 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-06 23:34:46 +00:00
Dan Gohman
fd2163bcf7 Use a latency value of 0 for the artificial edges inserted by 
AddPseudoTwoAddrDeps. This lets the scheduling infrastructure
avoid recalculating node heights. In very large testcases this
was a major bottleneck. Thanks to Roman Levenstein for finding
this!

As a side effect, fold-pcmpeqd-0.ll is now scheduled better
and it no longer requires spilling on x86-32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-06 01:19:04 +00:00
Evan Cheng
7e66c0d43a Find loop back edges only after empty blocks are eliminated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61752 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-05 21:17:27 +00:00
Dan Gohman
cc91d63ab7 Fix a DAGCombiner abort on an invalid shift count constant. This fixes PR3250. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61613 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-03 19:22:06 +00:00
Evan Cheng
ccb6976a69 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-02 05:35:45 +00:00
Evan Cheng
52ceafa5c7 Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61555 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-02 05:29:08 +00:00
Chris Lattner
1323e8bf6a add PR # 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61427 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-25 05:40:38 +00:00