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297 Commits

Author SHA1 Message Date
Evan Cheng
470a6adc78 Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. 
Fixed some existing bugs (wrong predicates, prefixes) at the same time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 02:26:30 +00:00
Evan Cheng
4e4c71e423 One more round of reorg so sabre doesn't freak out. :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26303 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 20:00:20 +00:00
Evan Cheng
beb07e117d A big more cleaning up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26302 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 19:30:30 +00:00
Evan Cheng
bf156d1ae6 Moving things to their proper places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26301 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 19:26:52 +00:00
Evan Cheng
ffcb95beab Split instruction info into multiple files, one for each of x87, MMX, and SSE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26300 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 19:13:53 +00:00
Evan Cheng
747a90d887 Added separate alias instructions for SSE logical ops that operate on non-packed types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26297 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 02:24:38 +00:00
Evan Cheng
7dbc0a3351 Added MMX and XMM packed integer move instructions, movd and movq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26296 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 01:39:57 +00:00
Evan Cheng
aea20f50e5 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit 
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-20 22:34:53 +00:00
Evan Cheng
2b15271571 Added fisttp for fp to int conversion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26283 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 02:36:28 +00:00
Evan Cheng
7ccced634a x86 / Darwin PIC support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 00:15:05 +00:00
Nate Begeman
551bf3f800 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 05:43:56 +00:00
Evan Cheng
39d1761c70 pxor (for FLD0SS) encoding was missing the OpSize prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26244 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 23:59:30 +00:00
Evan Cheng
fe5cb19405 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This 
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26241 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 22:45:17 +00:00
Evan Cheng
77dea9b3c3 MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26234 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 19:34:41 +00:00
Evan Cheng
f3f0a9c587 cvtsd2ss / cvtss2sd encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26193 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 00:31:03 +00:00
Evan Cheng
7335f9beea movaps, movapd encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26192 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 00:11:37 +00:00
Chris Lattner
a3b8c57b9e Eliminate the printCallOperand method, using a 'call' modifier on 
printOperand instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26025 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-06 23:41:19 +00:00
Evan Cheng
72f514cf39 Remove an unnecessary predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25954 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 02:23:01 +00:00
Evan Cheng
e3de85b447 Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a 
flag so it can be flagged to a FST.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25953 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 02:20:30 +00:00
Evan Cheng
78376d59ab Rearrange code to my liking. :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25887 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 23:01:57 +00:00
Evan Cheng
3c55c54a87 - Use xor to clear integer registers (set R, 0). 
- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25872 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 06:13:50 +00:00
Evan Cheng
223547ab31 - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. 
- Use XORP* to implement fneg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 22:28:30 +00:00
Chris Lattner
259e97cc72 * Fix 80-column violations 
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 19:43:35 +00:00
Evan Cheng
ef6ffb17c7 Added custom lowering of fabs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25831 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 03:14:29 +00:00
Evan Cheng
6dab05363f Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 
conversions. SSE does not have instructions to handle these tasks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25817 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 08:02:57 +00:00
Chris Lattner
44d9b9bb86 The FP stack doesn't support UNDEF, ask the legalizer to legalize it 
instead of lying and saying we have it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25775 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-29 06:44:22 +00:00
Evan Cheng
85214ba3cc AT&T assembly convention: registers are in lower case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25714 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 22:53:29 +00:00
Evan Cheng
559806f575 x86 CPU detection and proper subtarget support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 08:10:46 +00:00
Chris Lattner
cedc6f4b30 PHI and INLINEASM are now built-in instructions provided by Target.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 01:46:15 +00:00
Evan Cheng
71fb9ad5d9 Remove the uses of STATUS flag register. Rely on node property SDNPInFlag, 
SDNPOutFlag, and SDNPOptInFlag instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25629 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 00:29:36 +00:00
Chris Lattner
af63bb03c5 Emit the copies out of call return registers *after* the ISD::CALLSEQ_END 
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25580 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-24 05:17:12 +00:00
Evan Cheng
86556a5f42 Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual). 
Some assemblers can't recognize the aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25494 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-21 02:55:41 +00:00
Evan Cheng
21d5443934 A few more SH{L|R}D peepholes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25473 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-20 01:13:30 +00:00
Evan Cheng
956044cf03 Added i16 SH{L|R}D patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25468 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-19 23:26:24 +00:00
Evan Cheng
41b6dc8dbe adc and sbb need an incoming flag to ensure it reads the carry flag 
from add / sub.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25444 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-19 06:53:20 +00:00
Evan Cheng
68b951a5e5 Two peepholes: 
(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25438 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-19 01:56:29 +00:00
Evan Cheng
e5d9343377 Zero extending load from i1 to i8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25391 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-17 07:02:46 +00:00
Evan Cheng
42ef0bc6fb Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should 
read a flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25378 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-17 00:19:47 +00:00
Evan Cheng
b5d0b0bae5 More typo's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25375 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-16 23:26:53 +00:00
Evan Cheng
8a3f4c75fa Some typo's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25374 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-16 22:48:46 +00:00
Evan Cheng
0cc3945efe Fix FP_TO_INT**_IN_MEM lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25368 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-16 21:21:29 +00:00
Evan Cheng
cf74a7c762 Added patterns for 8-bit multiply 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25338 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-15 10:05:20 +00:00
Nate Begeman
d88fc03602 bswap implementation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25312 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-14 03:14:10 +00:00
Evan Cheng
e3703d44e9 A typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25307 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-14 01:18:49 +00:00
Evan Cheng
b8414333ac Add truncstore i1 patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25296 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-13 21:45:19 +00:00
Evan Cheng
a3195e8643 Fix sint_to_fp (fild*) support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25257 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-12 22:54:21 +00:00
Evan Cheng
77e9043b84 Specify transformation from GlobalAddress to TargetGlobalAddress and 
ExternalSymbol to TargetExternalSymbol.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25253 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-12 19:36:31 +00:00
Evan Cheng
5ee4ccce5b X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be 
linked together).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25247 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-12 08:27:59 +00:00
Evan Cheng
002fe9baf2 * Materialize GlobalAddress and ExternalSym with MOV32ri rather than 
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25246 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-12 07:56:47 +00:00
Evan Cheng
eb422a7234 Added ROTL and ROTR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25232 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-11 23:20:05 +00:00
Evan Cheng
67f92a7649 Support for MEMCPY and MEMSET. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25226 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-11 22:15:48 +00:00
Evan Cheng
8700e14ba1 * Add special entry code main() (to set x87 to 64-bit precision). 
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
  call parmater passing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25207 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-11 06:09:51 +00:00
Evan Cheng
4a46080fe0 SSE cmov support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25190 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-11 00:33:36 +00:00
Evan Cheng
f710062bfb * fp to sint patterns. 
* fiadd, fisub, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25189 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-10 22:22:02 +00:00
Evan Cheng
aaca22ca91 FP_TO_INT*_IN_MEM and x87 FP Select support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25188 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-10 20:26:56 +00:00
Evan Cheng
510e478098 * Added undef patterns. 
* Some reorg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25163 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-09 23:10:28 +00:00
Evan Cheng
e3413160ca Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25158 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-09 18:33:28 +00:00
Evan Cheng
cfa260b2ab Addd (shl x, 1) ==> (shl x, x) peepholes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25123 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-06 02:31:59 +00:00
Evan Cheng
d9558e0ba6 * Fast call support. 
* FP cmp, setcc, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25117 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-06 00:43:03 +00:00
Evan Cheng
650d688db6 Added ConstantFP patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25108 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-05 02:08:37 +00:00
Evan Cheng
d90eb7fb24 DAG based isel call support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25103 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-05 00:27:02 +00:00
Evan Cheng
2b4ea795a2 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-26 09:11:45 +00:00
Evan Cheng
171049d10f * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-23 22:14:32 +00:00
Evan Cheng
38bcbaf23e More X86 floating point patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24990 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-23 07:31:11 +00:00
Evan Cheng
5bc4da4893 Bye bye HACKTROCITY. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24935 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-22 02:26:21 +00:00
Evan Cheng
3a03ebb377 * Fix a GlobalAddress lowering bug. 
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24921 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 23:05:39 +00:00
Evan Cheng
793ca4caa4 Oops. Accidentally deleted RET pattern. It's still needed for return void; 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24920 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 22:22:16 +00:00
Evan Cheng
d5781fca4f * Added support for X86 RET with an additional operand to specify number of 
bytes to pop off stack.
* Added support for X86 SETCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24917 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 20:21:51 +00:00
Chris Lattner
c515ad18f8 This was meant to go in 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24900 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 07:50:26 +00:00
Chris Lattner
58fe459e36 Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns 
that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24899 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 07:47:04 +00:00
Chris Lattner
9fb2422c49 Wrap some long lines: no functionality change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24898 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 05:34:58 +00:00
Evan Cheng
b077b842b6 * Added lowering hook for external weak global address. It inserts a load 
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24888 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 02:39:21 +00:00
Evan Cheng
bbc8ddbea3 SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24886 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-20 22:59:51 +00:00
Evan Cheng
a5386b0823 Added X86 readport patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24879 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-20 07:38:38 +00:00
Evan Cheng
898101c15f X86 conditional branch support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24870 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 23:12:38 +00:00
Chris Lattner
4543251834 eliminate some redundancy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24781 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 19:47:05 +00:00
Evan Cheng
1aabc4ea15 Added anyext, modelled as zext on X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24759 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 01:47:57 +00:00
Evan Cheng
aed7c721df Added support for cmp, test, and conditional move instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24756 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 01:24:02 +00:00
Evan Cheng
cb17bac3a3 * Promote all 1 bit entities to 8 bit. 
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24726 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-15 19:49:23 +00:00
Evan Cheng
502c5bb428 Added frameindex, constpool, globaladdr, and externalsym as root nodes of 
leaaddr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24724 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-15 08:31:04 +00:00
Evan Cheng
f6036a3f1b Use MOV8rm to load 1 bit value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24721 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-15 00:59:17 +00:00
Evan Cheng
7a7e8375a9 Added sext and zext patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24705 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-14 02:22:27 +00:00
Evan Cheng
85dd889ed6 Add load + store folding srl and sra patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24696 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 07:24:22 +00:00
Evan Cheng
c937ffafba Beautify a few patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24690 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 02:40:18 +00:00
Evan Cheng
763b029b28 Some shl patterns which do load + store folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24689 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 02:34:51 +00:00
Evan Cheng
605c415046 A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24688 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 01:57:51 +00:00
Evan Cheng
0ef3a77bdf Add and, or, and xor patterns which fold load + stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24687 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 01:41:36 +00:00
Evan Cheng
6cad276c90 Add inc + dec patterns which fold load + stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24686 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 01:02:47 +00:00
Evan Cheng
5ce4edb967 Add neg and not patterns which fold load + stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24685 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 00:54:44 +00:00
Evan Cheng
5a38e0210d Missed a couple redundant explicit type casts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24684 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 00:25:07 +00:00
Evan Cheng
9b6b642647 Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24683 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 00:14:11 +00:00
Evan Cheng
b3558540b6 * Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands. 
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24682 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 00:01:09 +00:00
Evan Cheng
f281e02cbd Add some integer mul patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24681 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-12 23:47:46 +00:00
Evan Cheng
d160d48a2b Add some sub patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24675 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-12 21:54:05 +00:00
Evan Cheng
ee93f9db87 Add a few more add / store patterns. e.g. ADD32mi8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24670 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-12 19:45:23 +00:00
Evan Cheng
b51a059b2c * Added X86 store patterns. 
* Added X86 dec patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24654 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-10 00:48:20 +00:00
Evan Cheng
ab24ed2a32 Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24648 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-09 22:48:48 +00:00
Evan Cheng
670fd8f8dd Added explicit type field to ComplexPattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24637 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 02:15:07 +00:00
Evan Cheng
ec693f77c0 * Added intelligence to X86 LEA addressing mode matching routine so it returns 
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24635 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 02:01:35 +00:00
Evan Cheng
8d202230b4 Remove unnecessary let hasCtrlDep=1 now it can be inferred. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24611 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 23:09:43 +00:00