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99 Commits

Author SHA1 Message Date
Richard Osborne
9e333ca445 [XCore] Whitespace fixes, no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185519 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 07:49:03 +00:00
Richard Osborne
79186beb28 [XCore] Add ISel pattern for LDWCP 
Patch by Robert Lytton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185518 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 07:48:50 +00:00
Richard Osborne
850ba41ed4 [XCore] Fix instruction selection for zext, mkmsk instructions. 
r182680 replaced CountLeadingZeros_32 with a template function
countLeadingZeros that relies on using the correct argument type to give
the right result. The type passed in the XCore backend after this
revision was incorrect in a couple of places.

Patch by Robert Lytton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185430 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-02 14:46:34 +00:00
Michael J. Spencer
c6af2432c8 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-24 22:23:49 +00:00
Richard Osborne
589ddc9887 [XCore] Add LDAPB instructions. 
With the change the disassembler now supports the XCore ISA in its
entirety.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-05 13:36:53 +00:00
Richard Osborne
fae63389d9 [XCore] Update LDAP to use pcrel_imm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181154 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-05 13:33:10 +00:00
Richard Osborne
24aeab3d8a [XCore] Rename calltarget -> pcrel_imm. 
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181153 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-05 13:29:02 +00:00
Richard Osborne
c601bd69d5 [XCore] Add BLRB instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-05 13:24:16 +00:00
Richard Osborne
1114b0ec15 [XCore] Remove '-' from back branch asm syntax. 
Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-05 13:20:22 +00:00
Richard Osborne
43c7abee14 [XCore] Remove unused operand type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181127 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-04 17:30:05 +00:00
Richard Osborne
6ffbf6ea8f [XCore] Make use of the target independent global address offset folding. 
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-04 17:24:33 +00:00
Richard Osborne
e50faa754b [XCore] Add bru instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 20:05:35 +00:00
Richard Osborne
c6ff29713d [XCore] The RRegs register class is a superset of GRRegs. 
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 19:57:46 +00:00
Richard Osborne
8dc741e400 [XCore] Add missing 2r instructions. 
These instructions are not targeted by the compiler but it is needed for
the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 22:38:05 +00:00
Richard Osborne
763c858ede [XCore] Add TSETR instruction. 
This instruction is not targeted by the compiler but it is needed for the
MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 22:32:41 +00:00
Richard Osborne
a970dde906 [XCore] Add missing u10 / lu10 instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 20:44:48 +00:00
Richard Osborne
cbe6c88b68 [XCore] Add missing u6 / lu6 instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 20:43:17 +00:00
Jakob Stoklund Olesen
0873bc8419 Move MRI liveouts to XCore return instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174414 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 18:21:46 +00:00
Richard Osborne
970a479c02 [XCore] Add missing l2rus instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 22:28:30 +00:00
Richard Osborne
b719d8b100 [XCore] Add missing l2r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 21:26:02 +00:00
Richard Osborne
9d2b1aef1b [XCore] Add missing 1r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 20:46:21 +00:00
Richard Osborne
f5e7e793f1 [XCore] Add missing 0r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 20:42:57 +00:00
Richard Osborne
c47bd9899b Add instruction encodings / disassembly support for l4r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 21:55:32 +00:00
Richard Osborne
1f375e5bc7 Use the correct format in the STW / SETPSC instruction names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 21:25:12 +00:00
Richard Osborne
0f1bcedf5a Fix order of operands for crc8_l4r 
The order in which operands appear in the encoded instruction is different
to order in which they appear in assembly. This changes the XCore backend to
use the instruction encoding order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173493 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 21:20:28 +00:00
Richard Osborne
3b6a5eefe0 Add instruction encodings / disassembly support for l5r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 20:20:07 +00:00
Richard Osborne
f5c3648921 Fix order of operands for l5r instructions. 
With this change the operands order matches the order in which the operands
are encoded in the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173477 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 20:16:00 +00:00
Richard Osborne
907bfd740a Use correct mnemonic / instruction name for ldivu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173476 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 20:11:26 +00:00
Richard Osborne
9e6a5a3746 Add instruction encodings / disassembly support for l6r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-23 20:08:11 +00:00
Richard Osborne
0ec35ac4fc Add instruction encodings / disassembly support for u10 / lu10 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-22 22:55:04 +00:00
Richard Osborne
923cc3ebb0 Fix some incorrectly named u10 / lu10 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-21 21:12:30 +00:00
Richard Osborne
d5ab457c0e Remove unused multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173087 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-21 20:50:54 +00:00
Richard Osborne
8da5434346 Add instruction encodings / disassembly support for u6 / lu6 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-21 20:44:17 +00:00
Richard Osborne
9b709f8b3f Add instruction encoding / disassembly support for ru6 / lru6 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-21 20:42:16 +00:00
Richard Osborne
a3458380b9 Use correct format for the LDAWCP instruction (u6). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173083 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-21 20:32:54 +00:00
Richard Osborne
b853c415c6 Add instruction encodings / disassembly support for l2rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 18:51:15 +00:00
Richard Osborne
c78ec6b6bc Add instruction encodings / disassembly support for l3r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 18:37:49 +00:00
Richard Osborne
a68c64fbb2 Add instruction encodings / disassembler support for 2rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 17:22:43 +00:00
Richard Osborne
62b8786d12 Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 17:18:47 +00:00
Richard Osborne
c47793c62c Add instruction encodings / disassembly support for l2r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 16:28:02 +00:00
Richard Osborne
a839ffc323 Add instruction encodings for PEEK and ENDIN. 
Previously these were marked with the wrong format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170334 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 14:23:54 +00:00
Richard Osborne
35150cbf41 Add instruction encodings / disassembly support for rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 13:50:04 +00:00
Richard Osborne
ff6114e872 Add instruction encodings for ZEXT and SEXT. 
Previously these were marked with the wrong format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170327 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 13:20:37 +00:00
Richard Osborne
1ffe48a84b Add instruction encodings / disassembly support for 2r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 12:29:31 +00:00
Richard Osborne
dd78daa199 Add instruction encodings / disassembly support for 0r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 12:26:29 +00:00
Richard Osborne
54d6266e9b Add instruction encodings and disassembly for 1r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-16 17:37:34 +00:00
Richard Osborne
6438214d21 Replace ${:comment} with the comment symbol. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170286 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-16 15:59:02 +00:00
Jakob Stoklund Olesen
4d320db5d1 Fix load/store SDNode flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 14:43:30 +00:00
Bill Wendling
56cb229866 Remove tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160477 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-19 00:11:40 +00:00
Jakob Stoklund Olesen
68c10a2ff7 Remove variable_ops from call instructions in most targets. 
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-13 20:44:29 +00:00