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38977 Commits

Author SHA1 Message Date
Bill Wendling
be22683202 Dale and Evan suggested putting the "check for setjmp" much earlier in the 
machine code generation. That's a good idea, so I made it so.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:32:40 +00:00
Jakob Stoklund Olesen
6a45d681e5 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:28:19 +00:00
Shih-wei Liao
6d37a29588 Adding the missing implementation of Bitfield's "clear" and "insert". 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:25:05 +00:00
Shih-wei Liao
5170b71143 To handle s* registers in emitVFPLoadStoreMultipleInstruction(). 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:02:28 +00:00
Eric Christopher
96ac5156ca Start adding mach-o tls reloc support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104651 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:02:12 +00:00
Jakob Stoklund Olesen
76f0ad7bf5 Drop the SuperregHashTable. It is essentially the same as SubregHashTable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 23:43:18 +00:00
Devang Patel
c3f5f783a2 First cut at supporting .debug_loc section. 
This is used to track variable information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104649 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 23:40:22 +00:00
Benjamin Kramer
48aefe15d0 Properly promote operands when optimizing a single-character memcmp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 22:53:43 +00:00
Bill Wendling
f10bc81b4e Constify function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104646 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 22:02:22 +00:00
Dan Gohman
eddc114a66 Do one map lookup instead of two. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104645 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 21:59:42 +00:00
Dan Gohman
5b71dcedf0 Fix a missing newline in debug output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104644 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 21:50:35 +00:00
Eric Christopher
04386ca726 Move the verbose asm output up a bit so it can be used in the special cases 
as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 21:49:43 +00:00
Bill Wendling
5edfbdc963 Okay, bear with me here... 
If you have a setjmp/longjmp situation, it's possible for stack slot coloring to
reuse a stack slot before it's really dead. For instance, if we have something
like this:

1:  y = g;
    x = sigsetjmp(env, 0);
    switch (x) {
    case 1:
      /* ... */
      goto run;  
    case 0:
  run:
      do_run(); /* marked as "no return" */
      break;
    case 3:
      if (...) {
        /* ... */
        goto run;
      }
      /* ... */
      break;
    }

2:  g = y;

"y" may be put onto the stack, so the expression "g = y" is relying upon the
fact that the stack slot containing "y" isn't modified between (1) and (2). But
it can be, because of the "no return" calls in there. A longjmp might come back
with 3, modify the stack slot, and then go to case 0. And it's perfectly
acceptable to reuse the stack slot there because there's no CFG flow from case 3
to (2).

The fix is to disable certain optimizations in these situations. Ideally, we'd
disable them for all "returns twice" functions. But we don't support that
attribute. Check for "setjmp" and "sigsetjmp" instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 21:44:26 +00:00
Eric Christopher
02b46bc942 Add support for initialized global data for darwin tls. Update comments 
and testcases accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 21:28:50 +00:00
Kevin Enderby
cf50a5390c Changed the encoding of X86 floating point stack operations where both operands 
are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 20:52:34 +00:00
Jakob Stoklund Olesen
b53985239c Separate unrelated cases that once shared a numeric value 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104629 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:40 +00:00
Jakob Stoklund Olesen
1fc8e759a7 Print symbolic SubRegIndex names on machine operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
4fda9670f0 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:33 +00:00
Daniel Dunbar
39e2dd7bab MC/X86: Add a hack to allow recognizing 'cmpltps' and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:32 +00:00
Dale Johannesen
86234c30a7 Fix another variant of PR 7191. Also add a testcase 
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104624 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 18:47:23 +00:00
Daniel Dunbar
79373680ed MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 18:40:53 +00:00
Kevin Enderby
04ac770be9 The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required 
for the 64-bit version of the Bit Test instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 18:16:58 +00:00
Dale Johannesen
61734eb117 Fix PR 7191. I have been unable to create a .ll file that fails, sorry. 
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104619 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:50:03 +00:00
Eric Christopher
7e2f5aaa67 Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen
48d0c163fb Ignore NumberHack and give each SubRegIndex instance a unique enum value instead. 
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
c159fba712 Use enums instead of literals for SystemZ subregisters 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104612 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:04:18 +00:00
Jakob Stoklund Olesen
22c0e97c56 Use enums instead of literals for X86 subregisters. 
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104611 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:04:16 +00:00
Zonr Chang
f3c770a2cb Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate)) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 10:23:52 +00:00
Zonr Chang
f86399be0c Add support to MOVimm32 using movt/movw for ARM JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 08:42:45 +00:00
Bob Wilson
a85df80ed7 Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated. 
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 04:51:47 +00:00
Bob Wilson
4876bdb69e Fix up instruction classes for Thumb2 RSB instructions to be consistent with 
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 04:43:08 +00:00
Bob Wilson
ab3912e3ce Clean up indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 03:36:52 +00:00
Jakob Stoklund Olesen
b7a3170917 Disable invalid coalescer assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104574 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 00:15:18 +00:00
Jakob Stoklund Olesen
e00fa64c16 Use enums instead of literals in the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 00:15:15 +00:00
Bill Wendling
ef473bfc44 Print out the name of the function during SSC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104572 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 23:16:04 +00:00
Jakob Stoklund Olesen
33276d95ef Switch SubRegSet to using symbolic SubRegIndices 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 23:03:18 +00:00
Bob Wilson
c21763fd99 Allow Thumb2 MVN instructions to set condition codes. The immediate operand 
version of t2MVN already allowed that, but not the register versions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 22:41:19 +00:00
Jakob Stoklund Olesen
f27462eb29 Lose the dummies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:47:01 +00:00
Jakob Stoklund Olesen
09bc029865 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:46:58 +00:00
Evan Cheng
3946043a80 Avoid adding duplicate function live-in's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:33:37 +00:00
Dan Gohman
e350690e3b Fix an mmx movd encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 20:51:08 +00:00
Kevin Enderby
ca956dc0f6 MC/X86: Add aliases for CMOVcc variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 20:32:23 +00:00
Bob Wilson
d303846e16 Clean up some extra whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 20:08:34 +00:00
Bob Wilson
bb7ecb2bf5 Thumb2 RSBS instructions were being printed without the 'S' suffix. 
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:44:06 +00:00
Devang Patel
295cdf8b82 Do not emit line number entries for unknown debug values. 
This fixes recent regression in store.exp from gdb testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104524 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:26:49 +00:00
Evan Cheng
c7cf10c97e LR is in GPR, not tGPR even in Thumb1 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
a1132276e7 Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are 
never used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104517 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:55:38 +00:00
Jakob Stoklund Olesen
d6be874e8c Use SubRegIndex in SystemZ. 
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104515 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:43:01 +00:00
Jakob Stoklund Olesen
fff916a960 SubRegIndex'ize Mips 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:42:58 +00:00
Jakob Stoklund Olesen
59f7199e16 SubRegIndex'ize MSP430 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:42:55 +00:00
Jakob Stoklund Olesen
7bb31e3187 Fix a few places that depended on the numeric value of subreg indices. 
Add assertions in places that depend on consecutive indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
558661d271 Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums 
from ARMRegisterInfo.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 16:54:32 +00:00
Jakob Stoklund Olesen
3458e9e4df Rename X86 subregister indices to something shorter. 
Use the tablegen-produced enums.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
73ea7bf450 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 14:48:12 +00:00
Nicolas Geoffray
3816c25fdc Encode the Caml frametable by following what the comment says: the number of descriptors 
is first emitted, and StackOffsets are emitted in 16 bits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 12:24:11 +00:00
Daniel Dunbar
414c0c43d3 llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 18:36:38 +00:00
Daniel Dunbar
01777ff094 llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 18:36:34 +00:00
Daniel Dunbar
fdb5a86179 MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104463 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 17:44:06 +00:00
Bob Wilson
069e434868 VDUP doesn't support vectors with 64-bit elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 05:42:31 +00:00
Daniel Dunbar
62e4c671b6 MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: 
addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 21:02:33 +00:00
Daniel Dunbar
54ddf3d9c7 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 21:02:29 +00:00
Daniel Dunbar
4c361972fd MC/X86: Add alias for setz, setnz, jz, jnz. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 06:37:33 +00:00
Evan Cheng
2457f2c661 Implement @llvm.returnaddress. rdar://8015977. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:47:14 +00:00
Jim Grosbach
5eb1951539 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:06:18 +00:00
Bob Wilson
be751cfe9c Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by 
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:23:12 +00:00
Eric Christopher
8116ca5134 Add full bss data support for darwin tls variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:10:22 +00:00
Devang Patel
65eb482e8f Collect variable information during endFunction() instead of beginFunction(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:04:14 +00:00
Bob Wilson
70fe6643d6 Clean up extra whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:53:55 +00:00
Eric Christopher
e81d010589 Make this LookAheadLimit, not the uninitialized LookAheadLeft. 
Evan please verify!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:40:03 +00:00
Chris Lattner
c2685a9c98 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:16:21 +00:00
Eric Christopher
070c1abbc9 Expand on comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:03:53 +00:00
Kevin Enderby
9d31d79493 Added retl for 32-bit x86 and added retq for 64-bit x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:01:38 +00:00
Evan Cheng
835810bbf8 Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:22:19 +00:00
Eric Christopher
9b00685bb6 Fix section attribute name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104381 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:08:52 +00:00
Bob Wilson
78f006acdf Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:05:32 +00:00
Evan Cheng
1015ba7018 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
18b2c9d3bf Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction 
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 20:02:01 +00:00
Devang Patel
379fe83dda Simplify 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:49:09 +00:00
Dale Johannesen
acbf6348b1 Previous commit message should refer to 104308. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104337 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:44:47 +00:00
Dale Johannesen
e39859a838 Fix two bugs in 104348: 
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104336 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:40:15 +00:00
Chris Lattner
a26a8471bd now that fp reg kill insertion stuff happens as a separate 
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104333 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:17:54 +00:00
Chris Lattner
d596c90030 Use less evil form of switch stmt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104331 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:02:42 +00:00
Chris Lattner
d3d9ee1a4d use continue to reduce nesting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104330 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:01:24 +00:00
Chris Lattner
637e073181 pull a nested loop of this pass out to its own function, 
eliminating the gymnastics around the ContainsFPCode var.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104328 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:57:03 +00:00
Chris Lattner
6f569aabb5 modernize this pass a bit, fit in 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:49:07 +00:00
Chris Lattner
65569b8ddf constify accessor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104325 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
19f5f71bba Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." 
This reverts r104322. I think it was causing miscompilations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
00c53caa33 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple 
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:36:13 +00:00
Jakob Stoklund Olesen
63e6a488cb If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:32:16 +00:00
Matt Fleming
d8a33ddcfe Currently, createMachOStreamer() is invoked directly in llvm-mc which 
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 12:54:43 +00:00
Matt Fleming
7efaef6b82 Split out the x86_32 an x86_64 ELF backends as they handle ELF 
differently. This will make adding ELF support easier in the long run.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104317 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 11:39:07 +00:00
Matt Fleming
924c5e58f2 Add support for parsing the ELF .type assembler directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104316 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 11:36:59 +00:00
Dale Johannesen
7d07b48b26 Fix i64->f64 conversion, x86-64, -no-sse. A bit 
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:52:33 +00:00
Evan Cheng
f7d87ee158 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:43:17 +00:00
Evan Cheng
b11ac950d6 Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:42:32 +00:00
Devang Patel
c0c5a26dea Simplify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104302 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:10:20 +00:00
Daniel Dunbar
4ef6730632 Fix __crashreport_info__ declaration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 23:50:19 +00:00
Evan Cheng
1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 23:26:43 +00:00
Dan Gohman
0fe46d9b48 DominatorTree.getNode can return null for unreachable blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104290 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 22:46:54 +00:00
Dan Gohman
9f383eb950 Minor code cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104287 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 22:25:20 +00:00
Mikhail Glushenkov
dcc44670f4 Print a space after the colon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 21:11:37 +00:00
Dan Gohman
a552878508 Make Solve check its own post-condition, to reduce clutter in the 
top-level LSRInstance logic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:59:23 +00:00
Dan Gohman
76c315a26c Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:52:00 +00:00
Daniel Dunbar
4e7f8390c0 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:36:29 +00:00
Devang Patel
6ed0ce3240 Rename variable. add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:35:24 +00:00
Dan Gohman
402d43529c More code cleanups. Use iterators instead of indices when indices 
aren't needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104273 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:33:18 +00:00
Daniel Dunbar
1fe591da3e X86: Model i64i32imm properly, as a subclass of all immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:20:39 +00:00
Daniel Dunbar
0306e3ddbf X86: Fix immediate type of FOO64i32 operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:20:35 +00:00
Dan Gohman
c6519f916b Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set 
Changed directly instead of using a return value.

Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104269 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:05:31 +00:00
Dan Gohman
f7ff37d674 Add some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104268 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:00:41 +00:00
Dan Gohman
d974a0e9d6 Simplify this code. Don't do a DomTreeNode lookup for each visited block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104267 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:00:25 +00:00
Devang Patel
ee43286ca9 Refactor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:57:06 +00:00
Matt Fleming
ab3b3651ad Grammar fix. This is a test commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104264 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:45:09 +00:00
Dan Gohman
ea507f5c28 Minor code cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:44:23 +00:00
Dan Gohman
f182b23f8f When canonicalizing icmp operand order to put the loop invariant 
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.

Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:26:52 +00:00
Mikhail Glushenkov
eb0971529d llvmc: Make segfault detection work on Win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:23:47 +00:00
Dan Gohman
9da1bf4845 Set Changed to true when canonicalizing ICmp operand order; even though 
it isn't a very interesting change, it's a change nonetheless.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104260 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:16:03 +00:00
Bob Wilson
63b8845e78 Handle Neon v2f64 and v2i64 vector shuffles as register copies. 
This fixes the remaining issue with pr7167.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 18:39:53 +00:00
Jim Grosbach
76526f8863 Remove dbg_value workaround and associated command line option 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 18:34:01 +00:00
Dan Gohman
53e184980d Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't 
have a pattern and it had an invalid encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104244 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 18:05:01 +00:00
Dale Johannesen
5f07d5224d The PPC MFCR instruction implicitly uses all 8 of the CR 
registers.  Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
 vreg = MCRF  CR0
 MFCR  <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment).  That avoids all problems.  7739628.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 17:48:26 +00:00
Devang Patel
69b4d1caff Strip llvm.dbg.lv also. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104236 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:49:22 +00:00
Dan Gohman
24a7c30822 Rename a variable to avoid shadowing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:41:11 +00:00
Devang Patel
26c1e56f13 Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:36:41 +00:00
Dan Gohman
4766744072 Minor code simplification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:23:28 +00:00
Dan Gohman
e5e4ff974d Fix assembly parsing and encoding of the pushf and popf family of 
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:16:00 +00:00
Dan Gohman
100804f494 Set neverHasSideEffects on 64-bit pushf and popf, for consistency with 
16-bit and 32-bit pushf and popf.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104228 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 15:42:55 +00:00
Dan Gohman
5ce6d05ad6 Move the code for deleting BaseRegs and LSRUses into helper functions, 
and fix a bug that valgrind noticed where the code would std::swap an
element with itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 15:17:54 +00:00
Benjamin Kramer
c37791e875 Reduce string trashing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104223 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 14:14:22 +00:00
Evan Cheng
15a16def6e Add a hybrid bottom up scheduler that reduce register usage while avoiding 
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 06:13:19 +00:00
Nick Lewycky
761fd4c1d9 Fix typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104209 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 03:30:09 +00:00
Dan Gohman
14aaeac5cf Define the x86 pause instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 01:35:50 +00:00
Dan Gohman
ee5673b622 Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it 
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 01:23:41 +00:00
Eric Christopher
c1a887d76d Partial code for emitting thread local bss data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 00:49:07 +00:00
Dan Gohman
a2086b3483 Teach LSR how to cope better with unrolled loops on targets where 
the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104186 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 23:43:12 +00:00
Bob Wilson
492fd454ca Optimize away insertelement of an undef value. This shows up in 
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 23:42:58 +00:00
Chris Lattner
a7f1354eb5 fix rdar://7986634 - match instruction opcodes case insensitively. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 23:34:33 +00:00
Jim Grosbach
de70b1f9be Enable preserving debug information through post-RA scheduling 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104175 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 22:57:47 +00:00
Jim Grosbach
309d20c89c Fix the post-RA instruction scheduler to handle instructions referenced by 
more than one dbg_value instruction. rdar://7759363


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 22:57:06 +00:00
Evan Cheng
e163168aab Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 22:42:23 +00:00
Devang Patel
461a646a03 Revert r104165. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 21:58:28 +00:00
Jakob Stoklund Olesen
d32e735ae6 Add support for partial redefs to the fast register allocator. 
A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.

Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 21:36:05 +00:00
Devang Patel
f4ccaeaef9 There is no need to maintain InsnsBeginScopeSet separately. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104165 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 21:26:53 +00:00
Jakob Stoklund Olesen
7ebc4d63db Add MachineInstr::readsVirtualRegister() in preparation for proper handling of 
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 20:36:22 +00:00
Evan Cheng
211ffa1351 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 20:19:50 +00:00
Jakob Stoklund Olesen
3437352887 TwoAddressInstructionPass doesn't really know how to merge live intervals when 
lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 20:08:00 +00:00
Mikhail Glushenkov
139c9e1f85 llvmc: report an error if a child process segfaults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104145 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 19:24:32 +00:00
Bob Wilson
14b2141497 When expanding a vector_shuffle, the element type may not be legal and may 
need to be promoted.  The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion.  This fixes part of pr7167.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104141 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 18:48:32 +00:00
Daniel Dunbar
d94406a940 MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104122 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 17:20:58 +00:00
Daniel Dunbar
52322e7b8b MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same 
prefix byte problem as in r104062.
 - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104120 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 15:26:43 +00:00
Daniel Dunbar
7d4bd203be MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and 
CALL64pcrel32, for the same reason.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104116 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 08:07:12 +00:00
Evan Cheng
9085f98b32 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 07:28:01 +00:00
Evan Cheng
27fa722311 Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 07:26:50 +00:00
Daniel Dunbar
597f17d5f1 MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104112 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 06:20:44 +00:00
Evan Cheng
5fd1c9be2d Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 06:07:03 +00:00
Evan Cheng
3c3195cbf1 Target instruction selection should copy memoperands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 06:06:09 +00:00
Daniel Dunbar
9248b3208a MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to 
avoid same prefix byte problem as in r104062.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 04:31:36 +00:00
Evan Cheng
ea420b20d4 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 01:52:25 +00:00
Dan Gohman
86026cd24e Add a comment explaining why this code uses Append mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 01:21:34 +00:00
Evan Cheng
0a942dbb1e Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. 
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 01:08:17 +00:00
Dan Gohman
7c2e03916c Factor out the code for picking integer arithmetic with immediate 
opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104091 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 00:53:19 +00:00
Dan Gohman
57aaa0b264 Add a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104089 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 23:55:57 +00:00
Dan Gohman
360026f07f Fix the predicate which checks for non-sensical formulae which have 
constants in registers which partially cancel out their immediate fields.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104088 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 23:48:08 +00:00
Dan Gohman
b2df433f71 Factor out the code for recomputing an LSRUse's Regs set after some 
of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104087 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 23:42:37 +00:00
Bob Wilson
417d1705bb Fix a crash when debugging the coalescer. DebugValue instructions are not 
in the coalescer's instruction map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104086 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 23:19:42 +00:00
Dan Gohman
d079c300ed Factor out code for estimating search space complexity into a helper 
function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 22:51:59 +00:00
Dan Gohman
0da751baf7 Add some more debug output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104080 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 22:41:32 +00:00
Dan Gohman
d69d62833a Factor out the code for deleting a formula from an LSRUse into 
a helper function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104079 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 22:39:15 +00:00
Dan Gohman
6458ff9230 Make some debug output more informative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 22:37:37 +00:00
Dan Gohman
c4cfbaf217 Print an error message in Formula::print if the HasBaseReg flag 
is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104077 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 22:35:55 +00:00
Dan Gohman
90bb355b16 Rename RegUseTracker's RegUses member to RegUsesMap to avoid 
confusion with LSRInstance's RegUses member.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104076 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 22:33:00 +00:00
Jakob Stoklund Olesen
dcf7708ad9 Remember to update VirtRegLastUse when spilling without killing before a call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104074 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 22:20:09 +00:00
Dan Gohman
f8c1ef0510 Teach mode load folding and unfolding code about CMP32ri8 and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:54:15 +00:00
Bill Wendling
2abc93d0fb Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is 
specified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:47:08 +00:00
Dan Gohman
e5efbafdac When converting a test to a cmp to fold a load, use the cmp that has an 
8-bit immediate field rather than one with a wider immediate field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:42:03 +00:00
Chris Lattner
6db0363bdc make mcinstlower remove all but the first operand to CALL64pcrel32. 
The register use operands (e.g. the first argument is passed in a 
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use.  This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.

This fixes rdar://7998435


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104062 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:40:18 +00:00
Evan Cheng
28dad2a5ca Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:31:17 +00:00
Eric Christopher
011c3f110b Implement EmitTBSSSymbol for MachOStreamer. 
Fixes build failure as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:26:41 +00:00
Eric Christopher
4d01cbe93b Make EmitTBSSSymbol take a section argument so that we can find it later. 
Fix up callers and users.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104057 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:16:04 +00:00
Jakob Stoklund Olesen
0eeb05c969 Properly handle multiple definitions of a virtual register in the same 
instruction.

This can happen on ARM:

>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:10:50 +00:00
Evan Cheng
5012f9b825 Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 20:07:47 +00:00
Evan Cheng
27e4840e03 Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 20:03:28 +00:00
Kevin Enderby
9f2ad11624 Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and not 
CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 18:09:20 +00:00
Kevin Enderby
d8ba292c9b Fixed the problem with a branch to "0b" that was not parsed by llvm-mc 
correctly.  The Lexer was incorrectly eating the newline casusing it to branch
to address 0.  Updated the test case to use a "0:" label and a branch to "0b".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104038 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 17:51:35 +00:00
Jakob Stoklund Olesen
6a8d2c6119 Teach the machine code verifier to use getSubRegisterRegClass(). 
The old approach was wrong. It had an off-by-one error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104034 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 17:31:12 +00:00
Daniel Dunbar
2ae4bfd769 MC/Mach-O: Implement support for setting indirect symbol table offset in section header. 
Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104033 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 17:28:24 +00:00
Daniel Dunbar
56279f42b6 MC/Mach-O: Remove some FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 17:28:20 +00:00
Daniel Dunbar
ca1212de59 MC/Mach-O: Fail faster/harder when we see .file, which isn't yet supported. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 17:28:17 +00:00
Daniel Dunbar
3f40b31256 MC/X86: Implement custom lowering to make sure we match things like 
X86::ADC32ri $0, %eax
to
  X86::ADC32i32 $0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104030 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 17:22:24 +00:00
Daniel Dunbar
3538c808f8 llc (et al): Add support for --show-encoding and --show-inst. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104029 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 17:22:19 +00:00
Dan Gohman
68e947ac61 Usage of O_NONBLOCK in bjam is now confirmed as a bug and fixed upstream. 
Update the comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 15:25:14 +00:00
Benjamin Kramer
47f9a49560 Simplify MCContext::(Next|Get)Instance 
- Allocate MCLabels in the context so they don't leak.
- Avoid duplicated densemap lookup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 12:15:34 +00:00
Evan Cheng
a083988c8a FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104004 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 00:03:40 +00:00
Jakob Stoklund Olesen
535af4a320 ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a 
too large limit.

The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.

A test case is very difficult to produce because it will only fail when the
scavenger is used.

rdar://problem/7894847

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103995 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 23:29:23 +00:00
Evan Cheng
c6dcce3ba5 Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103994 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 23:24:12 +00:00
Bill Wendling
53f7602b61 - Set the "HasCalls" flag after instruction selection is finished. 
- Change the logic DisableFramePointerElim() to check for the
  -disable-non-leaf-fp-elim before -disable-fp-elim.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103990 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 23:09:50 +00:00
Kevin Enderby
ebe7fcd041 Added support in MC for Directional Local Labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103989 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 23:08:19 +00:00
Eric Christopher
c6177a4531 More data/parsing support for tls directives. Add a few more testcases 
and cleanup comments as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 22:53:55 +00:00
Evan Cheng
44bfdd3d78 Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 22:09:49 +00:00