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2683 Commits

Author SHA1 Message Date
Bob Wilson
13ef840807 Add the cc_out operand for t2RSBrs instructions. I missed this when I changed 
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 00:27:15 +00:00
Jim Grosbach
0798eddd07 Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:49:24 +00:00
Evan Cheng
12616727c7 Use report_fatal_error, not llvm_unreachable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:45:31 +00:00
Jim Grosbach
a65850230a back out 104862/104869. Can reuse stacksave after all. Very cool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:11:57 +00:00
Evan Cheng
84f60b7359 llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 22:08:38 +00:00
Bob Wilson
d984eb6073 Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases 
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 20:23:42 +00:00
Jim Grosbach
ad9aaf038e add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH 
to update the jmpbuf in the presence of VLAs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 18:23:48 +00:00
Jakob Stoklund Olesen
c8b9f6ce23 Give SubRegIndex names to all ARM subregisters. This will be required by 
TableGen shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 22:15:03 +00:00
Jim Grosbach
23ff7cff52 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 20:22:18 +00:00
Jakob Stoklund Olesen
ca561ffcf3 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 17:27:12 +00:00
Shih-wei Liao
9f3b6a381a Coding style change (Adding 1 missing space.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 04:46:50 +00:00
Shih-wei Liao
45469f38b6 Adding the missing implementation for ARM::SBFX and ARM::UBFX. 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 03:21:39 +00:00
Jim Grosbach
54e13eceff fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 01:22:21 +00:00
Jakob Stoklund Olesen
b555609e73 Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
6a45d681e5 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:28:19 +00:00
Shih-wei Liao
6d37a29588 Adding the missing implementation of Bitfield's "clear" and "insert". 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:25:05 +00:00
Shih-wei Liao
5170b71143 To handle s* registers in emitVFPLoadStoreMultipleInstruction(). 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:02:28 +00:00
Jakob Stoklund Olesen
4fda9670f0 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:33 +00:00
Zonr Chang
f3c770a2cb Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate)) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 10:23:52 +00:00
Zonr Chang
f86399be0c Add support to MOVimm32 using movt/movw for ARM JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 08:42:45 +00:00
Bob Wilson
a85df80ed7 Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated. 
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 04:51:47 +00:00
Bob Wilson
4876bdb69e Fix up instruction classes for Thumb2 RSB instructions to be consistent with 
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 04:43:08 +00:00
Bob Wilson
ab3912e3ce Clean up indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 03:36:52 +00:00
Jakob Stoklund Olesen
e00fa64c16 Use enums instead of literals in the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 00:15:15 +00:00
Jakob Stoklund Olesen
33276d95ef Switch SubRegSet to using symbolic SubRegIndices 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 23:03:18 +00:00
Bob Wilson
c21763fd99 Allow Thumb2 MVN instructions to set condition codes. The immediate operand 
version of t2MVN already allowed that, but not the register versions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 22:41:19 +00:00
Jakob Stoklund Olesen
f27462eb29 Lose the dummies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:47:01 +00:00
Jakob Stoklund Olesen
09bc029865 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:46:58 +00:00
Bob Wilson
d303846e16 Clean up some extra whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 20:08:34 +00:00
Bob Wilson
bb7ecb2bf5 Thumb2 RSBS instructions were being printed without the 'S' suffix. 
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:44:06 +00:00
Evan Cheng
c7cf10c97e LR is in GPR, not tGPR even in Thumb1 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
7bb31e3187 Fix a few places that depended on the numeric value of subreg indices. 
Add assertions in places that depend on consecutive indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
558661d271 Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums 
from ARMRegisterInfo.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 16:54:32 +00:00
Bob Wilson
069e434868 VDUP doesn't support vectors with 64-bit elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 05:42:31 +00:00
Evan Cheng
2457f2c661 Implement @llvm.returnaddress. rdar://8015977. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:47:14 +00:00
Jim Grosbach
5eb1951539 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:06:18 +00:00
Bob Wilson
be751cfe9c Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by 
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:23:12 +00:00
Evan Cheng
f7d87ee158 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:43:17 +00:00
Evan Cheng
1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 23:26:43 +00:00
Bob Wilson
63b8845e78 Handle Neon v2f64 and v2i64 vector shuffles as register copies. 
This fixes the remaining issue with pr7167.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 18:39:53 +00:00
Evan Cheng
211ffa1351 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 20:19:50 +00:00
Evan Cheng
9085f98b32 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 07:28:01 +00:00
Evan Cheng
27fa722311 Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 07:26:50 +00:00
Evan Cheng
5fd1c9be2d Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 06:07:03 +00:00
Evan Cheng
3c3195cbf1 Target instruction selection should copy memoperands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 06:06:09 +00:00
Evan Cheng
ea420b20d4 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 01:52:25 +00:00
Evan Cheng
28dad2a5ca Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:31:17 +00:00
Jakob Stoklund Olesen
535af4a320 ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a 
too large limit.

The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.

A test case is very difficult to produce because it will only fail when the
scavenger is used.

rdar://problem/7894847

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103995 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 23:29:23 +00:00
Evan Cheng
47006be498 vmov of immediates are trivially re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103982 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 21:54:50 +00:00
Bob Wilson
7f43fd84db Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests. 
Obvious in retrospect but not fun to debug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103969 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 20:31:13 +00:00
Evan Cheng
6206124250 Turn on -neon-reg-sequence by default. 
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 19:51:20 +00:00
Evan Cheng
9c207ac0dc No reason not to run the NEON domain croassing fix up pass in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 01:11:46 +00:00
Anton Korobeynikov
bd91ea53f8 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 09:15:36 +00:00
Anton Korobeynikov
4878b8415f Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 08:54:20 +00:00
Evan Cheng
8f6de385d6 Model vst lane instructions with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103898 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 03:27:48 +00:00
Anton Korobeynikov
a9790d739a Some cheap DAG combine goodness for multiplication with a particular constant. 
This can be extended later on to handle more "complex" constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 18:16:59 +00:00
Anton Korobeynikov
418d1d954d "trap" pseudo-op turned out to be apple-local. 
Temporary emit it as raw bytes until it will be added to binutils as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 17:19:20 +00:00
Evan Cheng
7189fd03fa Model 128-bit vld lane with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 07:53:37 +00:00
Evan Cheng
4782b1e2ca v4i64 and v8i64 are only synthesizable when NEON is available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 02:20:21 +00:00
Evan Cheng
06b666c705 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 02:18:07 +00:00
Evan Cheng
7092c2bfcb Model 64-bit lane vld with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 01:36:29 +00:00
Evan Cheng
b990a2f249 Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE 
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 23:21:14 +00:00
Evan Cheng
12c24690c7 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 22:54:52 +00:00
Bill Wendling
b92187a410 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:14:32 +00:00
Evan Cheng
5c6aba2e3a Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 18:54:59 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 02:13:41 +00:00
Evan Cheng
7f68719517 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 00:21:45 +00:00
Evan Cheng
c4ca40eb5e Add comment about the pseudo registers QQ, each of which is a pair of Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 20:02:08 +00:00
Bob Wilson
1190c14b54 Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers. 
Do not use those for Thumb1 functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 19:58:24 +00:00
Daniel Dunbar
1860e7dcfd Fix -Asserts warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 03:19:36 +00:00
Evan Cheng
69b9f9883e Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 01:12:06 +00:00
Evan Cheng
d929f77738 Expand VMOVQQ into a pair of VMOVQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:17:02 +00:00
Evan Cheng
020cc1b4d0 Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:16:46 +00:00
Evan Cheng
431300797b Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 23:13:12 +00:00
Evan Cheng
a4d73d01c4 Remove a dead fixme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 20:20:22 +00:00
Rafael Espindola
18c1021ec1 Add support for movi32 of global values to the new (MC) asm printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 05:16:34 +00:00
Evan Cheng
5bdc2aa264 vst instructions are modeled as this: 
v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
      = VSTxx <addr>, v1025, v1026

The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
      = VSTxx <addr>, v1024:5, v1024:6

The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.

As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.

Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 01:42:50 +00:00
Evan Cheng
9647f3d981 Avoid breaking vstd when reg_sequence is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 21:07:36 +00:00
Duncan Sands
16d8f8bd91 I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 20:16:09 +00:00
Dan Gohman
ff7a562751 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263 Remove the TargetLowering::getSubtarget() virtual function, which 
was unused. TargetMachine::getSubtarget() is used instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 16:21:03 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 07:26:32 +00:00
Evan Cheng
0ce537a9db Model some vst3 and vst4 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 01:19:40 +00:00
Evan Cheng
e9e2ba05de Model some vld3 instructions with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a Model vld2 / vst2 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 17:34:18 +00:00
Jim Grosbach
4b77f6a85a Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:34:55 +00:00
Evan Cheng
435d499177 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:54:08 +00:00
Evan Cheng
c10b5afbe8 Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 00:24:52 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1 Add a missing break statement to fix unintentional fall-through 
(replacing the previous patch for the same issue).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7 Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3 Fix "warning: extra ';' inside a struct or union" when building llvm with clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128 Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 05:08:57 +00:00
Eric Christopher
f865cb5c1f Revert r103156 since it was breaking the build bots. 
Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 02:29:06 +00:00
Evan Cheng
9c35ee2099 Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:54:03 +00:00
Evan Cheng
4ffc22ae00 Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:52:03 +00:00
Evan Cheng
d31c5496d7 Cosmetic changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:34:11 +00:00
Evan Cheng
7f2f436267 storeRegToStackSlot has forgotten about QPR_8 register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:32:54 +00:00
Jim Grosbach
29402132f3 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 23:44:43 +00:00
Evan Cheng
676b2dfd27 Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 22:15:40 +00:00
Jim Grosbach
b1dc393bd5 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 18:28:36 +00:00
Evan Cheng
94cc6d3a2b With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:39:49 +00:00
Evan Cheng
826bdfa603 Do not pre-allocate for registers which form a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:38:12 +00:00
Jim Grosbach
6e62b4ef14 rdar://7937137 - dbg values not being handled in thumb1 version of 
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 00:11:37 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 00:01:06 +00:00
Evan Cheng
8601a3d4de Frame index can be negative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 01:13:30 +00:00
Jim Grosbach
d100755bab Add sizes non-floating point versions for the eh sjlj intrinsic expansions. 
rdar://7895451



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 20:33:09 +00:00
Bob Wilson
5dfa87ecc6 Handle register-to-register copies within the tGPR class. 
Radar 7896289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:20:08 +00:00
Dale Johannesen
3f282aa94b Handle target-specific form of DBG_VALUE in AsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:07:31 +00:00
Evan Cheng
62b50656ce Add ARM specific emitFrameIndexDebugValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:39:25 +00:00
Jim Grosbach
3a1287b470 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 23:24:18 +00:00
Johnny Chen
c048f1d12c Modified some assert() msg strings; no other functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 18:37:48 +00:00
Evan Cheng
e566763b19 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 03:18:23 +00:00
Johnny Chen
52d2b0ed00 Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:01:19 +00:00
Johnny Chen
d6b5d72c0f Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), 
instead of just asserting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 21:29:28 +00:00
Johnny Chen
ef37e3abb7 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', 
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 17:28:50 +00:00
Johnny Chen
3974ade503 Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where 
d==15 is considered illegal.  Return false instead of assert().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 01:01:57 +00:00
Johnny Chen
6bcf52f00a More IT instruction error-handling improvements from fuzzing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 00:15:41 +00:00
Johnny Chen
d0f3c46d16 Better error handling of invalid IT mask '0000', instead of just asserting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 23:02:58 +00:00
Johnny Chen
22e401f5d4 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 21:19:52 +00:00
Johnny Chen
d6cc53cfe4 Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand 
instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 17:16:40 +00:00
Johnny Chen
4b7df442a8 ARM disassembler did not react to recent changes to the NEON instruction table. 
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 16:20:34 +00:00
Anton Korobeynikov
928eb49cae Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-18 20:31:01 +00:00
Dan Gohman
3fb150a902 Fix -Wcast-qual warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 17:42:52 +00:00
Dan Gohman
0d805c33d1 Add const qualifiers to TargetLoweringObjectFile usage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 16:44:48 +00:00
Dan Gohman
d858e90f03 Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 15:26:15 +00:00
Dan Gohman
1e93df6f0b Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 14:41:14 +00:00
Bob Wilson
9f3f061d74 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this 
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 05:30:19 +00:00
Johnny Chen
de0ade4939 Cast to (uint64_t) instead of relying on the "ul" suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 23:30:28 +00:00
Dan Gohman
53c5e42ab9 Add skeleton target-specific SelectionDAGInfo files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101564 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 23:04:22 +00:00
Johnny Chen
af5b0e851e Fixed logic error. Should check Builder for validity before calling SetSession 
on it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 23:02:25 +00:00
Johnny Chen
c7b65914e0 Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a 
case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 22:40:20 +00:00
Johnny Chen
16fda6982b In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(), 
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 19:57:21 +00:00
Johnny Chen
2fb10f17d8 Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed 
to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 19:33:23 +00:00
Johnny Chen
d73d187e33 Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" are 
considered legal instructions.

Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101524 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 19:10:52 +00:00
Evan Cheng
47b7b9f228 Use getAL() rather than a major constant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101446 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 05:46:06 +00:00
Johnny Chen
1cfa094562 Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not 
am2offset.  Modified the instruction table entry and added a new test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 23:12:47 +00:00
Evan Cheng
3a1588a2e3 Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 22:20:34 +00:00
Evan Cheng
0ea7d219ec ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908 
llvm is generating poor code for dynamic alloca, I'll fix that later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 18:42:28 +00:00
Johnny Chen
c8866980fe DEBUG() print out "Unknown format" msg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101382 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 18:13:51 +00:00
Dan Gohman
8c407d4596 ReuseFrameIndexVals is used in multiple files, so it can't be static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 17:34:58 +00:00
Dan Gohman
b35798347e Fix a bunch of namespace polution. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 17:08:50 +00:00
Dan Gohman
ae541aad5c Add more const qualifiers for LLVM IR pointers in CodeGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 04:33:49 +00:00
Anders Carlsson
0dbdca5a85 Fix build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101335 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 03:11:28 +00:00
Dan Gohman
46510a73e9 Add const qualifiers to CodeGen's use of LLVM IR constructs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 01:51:59 +00:00
Johnny Chen
44398693e7 Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101329 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 01:20:56 +00:00