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11243 Commits

Author SHA1 Message Date
Anton Korobeynikov
656ac6f0f6 Provide proper stack offsets for outgoing arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75945 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:51:53 +00:00
Anton Korobeynikov
4f9017f214 Change register allocation order to reduce amount of callee-saved regs to be spilled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75944 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:51:34 +00:00
Anton Korobeynikov
ef5decab53 Emit callee-saved regs spills / restores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75943 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:51:12 +00:00
Anton Korobeynikov
ba249e41f3 Some preliminary call lowering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75941 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:50:21 +00:00
Anton Korobeynikov
3c98c616c5 Prologue / epilogue emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75940 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:49 +00:00
Anton Korobeynikov
51f613fb2b Add simple frame index elimination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:25 +00:00
Anton Korobeynikov
c4368a1507 Swap the order of imm and idx field for rri addrmode in order to make handling of rri and ri addrmodes common 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75937 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:48:42 +00:00
Anton Korobeynikov
3240740ef4 Do not truncate sign bits for negative imms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75936 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:48:23 +00:00
Anton Korobeynikov
711d5b68e0 Add address computation stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:59 +00:00
Anton Korobeynikov
dfd0dffa36 Cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75934 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:36 +00:00
Anton Korobeynikov
c8301d17a8 Add mem-imm stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75933 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:14 +00:00
Anton Korobeynikov
30da5380e0 [PATCH 023/155] Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75932 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:45:22 +00:00
Anton Korobeynikov
961bb6f430 Add stores and truncstores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:45:00 +00:00
Anton Korobeynikov
dc28955b3f Add patterns for various extloads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:44:30 +00:00
Anton Korobeynikov
3360da9772 Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75929 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:44:00 +00:00
Anton Korobeynikov
4cad7d29fc Change register allocation order, so R0 will be allocated the last among scratch. This will make address-calculation code much more happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75928 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:43:40 +00:00
Anton Korobeynikov
9e4816e09f Add shifts and reg-imm address matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:43:18 +00:00
Anton Korobeynikov
a51752cbea Add bunch of 32-bit patterns... Uffff :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:42:31 +00:00
Anton Korobeynikov
e0167c1d5a Add 32 bit subregs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75923 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:35:30 +00:00
Anton Korobeynikov
9342d3180a Add another bunch of reg-imm patterns for add/or/and/xor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75922 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:35:08 +00:00
Anton Korobeynikov
da308c9a67 Add bunch of reg-imm movs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:34:50 +00:00
Anton Korobeynikov
fc9ceeaad8 Proper match halfword-imm operands for mov and add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:34:24 +00:00
Anton Korobeynikov
89edcd0927 Provide masked reg-imm 'or' and 'and' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:33:57 +00:00
Anton Korobeynikov
e6220fb230 Add reg-reg and pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75917 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:32:49 +00:00
Anton Korobeynikov
bdc9081693 Add sub reg-reg pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75916 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:32:16 +00:00
Anton Korobeynikov
b573f99ab7 Add xor reg-reg pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:31:28 +00:00
Anton Korobeynikov
26ba0b1ec5 Add or reg-reg pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:30:53 +00:00
Anton Korobeynikov
0676d2887a Add add reg-reg and reg-imm patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:30:15 +00:00
Anton Korobeynikov
1cc9dc7267 Add simple reg-reg and reg-imm moves 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75912 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:29:38 +00:00
Anton Korobeynikov
87a24e3ee4 Minimal lowering for formal_arguments / ret 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:28:59 +00:00
Anton Korobeynikov
4403b930f8 Let's start another backend :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:27:25 +00:00
Richard Osborne
db9e697725 Combine an unaligned store of unaligned load into a memmove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 12:50:48 +00:00
Richard Osborne
787e90f862 Lower the threshold at which memcpy / memmove / memset stop being expanded 
inline in the XCore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75906 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 12:41:34 +00:00
Richard Osborne
ff4149b903 Fix typo in last commit on expansion of unaligned loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75903 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:48:47 +00:00
Richard Osborne
ccb7e96ef0 Expand unaligned 32 bit loads from an address which is a constant 
offset from a 32 bit aligned base as follows:

  ldw low, base[offset >> 2]
  ldw high, base[(offset >> 2) + 1]
  shr low_shifted, low, (offset & 0x3) * 8
  shl high_shifted, high, 32 - (offset & 0x3) * 8
  or result, low_shifted, high_shifted

Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:42:35 +00:00
Richard Osborne
7f47ce9662 Custom lower unaligned 32 bit stores and loads into libcalls. This is 
a big code size win since before they were expanding to upto 16
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:21:18 +00:00
Evan Cheng
378445303b Let callers decide the sub-register index on the def operand of rematerialized instructions. 
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 09:20:10 +00:00
Chris Lattner
6ef40b11f8 use SUBREG_TO_REG instead of INSERT_SUBREG, this way the code 
generator can know the top bits are zero, not undefined.
Thanks to Dan for pointing this out.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75899 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 06:31:37 +00:00
Chris Lattner
c2b443a698 fix some casts that I improperly refactored, patch by Artur Pietrek! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75894 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 04:34:33 +00:00
Daniel Dunbar
64cc972123 Kill off <TARGET>MachineModule variables, and <TARGETASMPRINTER>ForceLink 
variables.
 - Module initialization functions supplanted the need for these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75886 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 01:55:13 +00:00
Chris Lattner
fe2fe7094e fix section switching to ensure that stubs are emitted to the right 
section on ppc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75881 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 01:23:26 +00:00
Daniel Dunbar
5d77cad60b Lift addAssemblyEmitter into LLVMTargetMachine. 
- No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75859 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 23:34:19 +00:00
Daniel Dunbar
1e1f8ba28c Register AsmPrinter for XCore, MSP430, and PIC16 targets. 
- Switch to standard addAssemblyEmitter logic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75854 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 23:17:20 +00:00
Daniel Dunbar
cfe9a605ee Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine. 
- No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75848 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 22:33:19 +00:00
Daniel Dunbar
f05522974b Remove old style hacks to register AsmPrinter into TargetMachine. 
- No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 22:01:32 +00:00
Owen Anderson
a90b3dc2f1 Move a few more convenience factory functions from Constant to LLVMContext. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75840 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 21:51:10 +00:00
Chris Lattner
7add5ff1d1 move createAlphaLLRPPass out of addAssemblyEmitter to make Alpha 
more like other targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75839 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 21:40:24 +00:00
Ted Kremenek
1935629829 Lexically order files in CMakeLists.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75831 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 21:08:16 +00:00
Daniel Dunbar
f1459cf1f2 Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75829 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 20:59:20 +00:00
Bruno Cardoso Lopes
4b70fab658 use std::vector instead of std::list for both Section and Symbol lists because 
we care more about random access than insertion/deletion of elements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75828 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 20:49:10 +00:00