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2513 Commits

Author SHA1 Message Date
Johnny Chen
b72e59e361 Missed this one line for the previous checkin to fix build warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100697 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 22:21:03 +00:00
Johnny Chen
efd518e1fd Fixed warnings pointed out by clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100696 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 22:03:27 +00:00
Johnny Chen
7e4823c51f Fixed warnings pointed out by clang. 
Next to work on is ARMDisassemblerCore.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100695 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 21:52:48 +00:00
Johnny Chen
c22e2fcf72 Fixed 3 warnings pointed out by clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 21:23:48 +00:00
Johnny Chen
3c500e6947 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in 
ARMDecoderEmitter.cpp, with FIXME comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 20:53:12 +00:00
Sean Callanan
90b7097f92 Added an AsmLexer for the ARM target, which uses 
a simple mapping of register names to IDs to
identify register tokens.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100685 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 20:29:34 +00:00
Dale Johannesen
375be7730a Educate GetInstrSizeInBytes implementations that 
DBG_VALUE does not generate code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 19:51:44 +00:00
Anton Korobeynikov
4b38debf59 Remove late ARM codegen optimization pass committed by accident. 
It is not ready for public yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:23:27 +00:00
Anton Korobeynikov
e1676011c6 Split A8/A9 itins - they already were too big. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100672 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:22:11 +00:00
Anton Korobeynikov
895867326e Add some crude itin approximation for VFP load / stores on A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100671 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:22:03 +00:00
Anton Korobeynikov
67867135ec Add some crude approximation for neon load/store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100670 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:58 +00:00
Anton Korobeynikov
9113052a1f Add some A8-based approximation for instructions with unknown cycle times 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100669 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:52 +00:00
Anton Korobeynikov
ebd4cb43c2 Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:46 +00:00
Anton Korobeynikov
9ad709b523 Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:41 +00:00
Anton Korobeynikov
f3da92b2f2 Fix A8 FP NEON MAC itins 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100666 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:33 +00:00
Anton Korobeynikov
924369d58e A9 NEON FP itins 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100665 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:27 +00:00
Anton Korobeynikov
ec69dfa7ca Some permute goodness for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100664 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:22 +00:00
Anton Korobeynikov
5ca13c6ee3 More shift itins for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100663 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:16 +00:00
Anton Korobeynikov
ecc6406072 More fixes for itins 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:10 +00:00
Anton Korobeynikov
95102073e8 Fix invalid itins for 32-bit varians of VMLAL and friends 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:04 +00:00
Anton Korobeynikov
7930ac19e7 Add MAC stuff for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:58 +00:00
Anton Korobeynikov
d76da03e91 Fix invalid NEON MAC itins on A8 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100659 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:53 +00:00
Anton Korobeynikov
dc0bab70cf Fix itins for VPAL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100658 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:47 +00:00
Anton Korobeynikov
0a3e2b591c Fix itins for VABA 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100657 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:42 +00:00
Anton Korobeynikov
fc2b08438c Correct VMVN itinerary: operand is read in the second cycle, not in the first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100656 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:36 +00:00
Anton Korobeynikov
e715b1e43a More A9 itineraries 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:29 +00:00
Anton Korobeynikov
1c03f2493f Correct itinerary class for VPADD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:24 +00:00
Anton Korobeynikov
4ac0af851f VP{MAX, MIN} are of IIC_VSUBi4D itin class as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:18 +00:00
Anton Korobeynikov
f8b5c63617 VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:13 +00:00
Anton Korobeynikov
268b7446cf Some easy NEON scheduling goodness for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100651 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:07 +00:00
Anton Korobeynikov
a31c6fb65e Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:02 +00:00
Anton Korobeynikov
63401e33cb FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100649 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:56 +00:00
Anton Korobeynikov
bcc02d13bb Proper cycle times for locks, since wbck latency can be larger than fwd latency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:51 +00:00
Anton Korobeynikov
c492e09455 Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100647 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:46 +00:00
Anton Korobeynikov
391b3431e2 Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100646 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:40 +00:00
Anton Korobeynikov
2eeeff8371 Some bits of A9 scheduling: VFP 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:18 +00:00
Anton Korobeynikov
035b23a0f4 Separate const from non-const stuff during mergeing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:13 +00:00
Anton Korobeynikov
1e7b324fe5 Some initial version of global merger 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100641 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:07 +00:00
Bob Wilson
d0910c4534 Expand SELECT and SELECT_CC for NEON vector types. 
Radar 7770501.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100568 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-06 22:02:24 +00:00
Chris Lattner
0333535054 don't use emitlabel in the arm asm printer yet, the order 
isn't well specified.  ARM really needs to have its instprinter
finished at some point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100439 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 17:52:31 +00:00
Chris Lattner
0752cda4de fix a couple problems I introduced handling symbols 
with spaces in them.  Sym->getName()  !=   OS << *Sym




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 16:32:14 +00:00
Johnny Chen
7fb053dd45 Get rid of traling whitespaces. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 04:51:50 +00:00
Johnny Chen
9d563b676c The disassembler impl. of MCDisassembler::getInstruction() was using the pattern 
uint32_t insn;
  MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)

to read 4 bytes of memory contents into a 32-bit uint variable.  This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail.  Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 04:46:17 +00:00
Jakob Stoklund Olesen
fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. 
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 03:10:20 +00:00
Evan Cheng
cb86609421 Temporarily remove to disable building of ARM disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 01:57:50 +00:00
Evan Cheng
f6232cf8bb Re-apply 100265 but instead disable building of ARM disassembly for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 01:34:00 +00:00
Evan Cheng
1b0194d646 Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 01:04:27 +00:00
Chris Lattner
90429c487f just have all targets create the DwarfWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 00:42:55 +00:00
Chris Lattner
8e680482c1 simplify various getAnalysisUsage implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 00:38:44 +00:00
Chris Lattner
3d22513611 eliminate the magic AbsoluteDebugSectionOffsets MAI hook, 
which is really a property of the section being referenced.
Add a predicate to MCSection to replace it.

Yay for reduction in magic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 23:22:29 +00:00
Chris Lattner
1d20473c9d revert my patch, need to reconsider this and figure out what is really going on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 21:49:31 +00:00
Chris Lattner
4166047030 fix pasto, this is the wrong setting for arm elf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100357 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 21:37:20 +00:00
Chris Lattner
3f53c8398d clean up the asmprinter header and privatize some stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 18:52:31 +00:00
Chris Lattner
9d1c1ada21 remove TargetMachine.h #include, also, TRI isn't used frequently 
enough to warrant caching in AsmPrinter, so remove it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100336 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 18:06:11 +00:00
Chris Lattner
b23569aff0 Momentous day: remove the "O" member from AsmPrinter. Now all 
"asm printering" happens through MCStreamer.  This also 
Streamerizes PIC16 debug info, which escaped my attention.

This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 08:18:47 +00:00
Chris Lattner
9d7efd3081 mcize a bunch more stuff, using EmitRawText for things we 
don't have mcstreamer support for yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100319 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 07:05:53 +00:00
Chris Lattner
7ad07c4636 convert the non-MCInstPrinter'ized EmitInstruction 
implementations to use EmitRawText instead of writing
directly to "O".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 06:12:20 +00:00
Chris Lattner
c75c028a15 fix PrintAsmOperand and PrintAsmMemoryOperand to pass down 
raw_ostream to print to.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:29:35 +00:00
Chris Lattner
d374087be5 fix an ugly wart in the MCInstPrinter api where the 
raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:04:31 +00:00
Chris Lattner
35c33bd772 change a ton of code to not implicitly use the "O" raw_ostream 
member of AsmPrinter.  Instead, pass it in explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 04:47:45 +00:00
Mon P Wang
20adc9dc46 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 03:10:48 +00:00
Chris Lattner
0c08d09204 asmstreamerize the .size directive for function bodies, force clients 
of printOffset to pass in a stream to print to.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-03 22:28:33 +00:00
Johnny Chen
7fed809484 Get rid of the middleman (ARMAlgorithm), which causes more trouble than the 
abstraction it brings.  And also get rid of the atexit() handler, it does not
belong in the lib directory. :-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-03 04:10:56 +00:00
Johnny Chen
b7aaed83e2 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-03 01:17:30 +00:00
Johnny Chen
b35ae7f7d6 Register ARMAlgorithm::DoCleanup() to be called on exit to free the memory 
occuplied by the cached ARMAlgorithm objects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100258 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-03 01:09:47 +00:00
Johnny Chen
a70261550e Fix another build warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 23:43:38 +00:00
Johnny Chen
b68a3ee82a Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen 
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 22:27:38 +00:00
Sean Callanan
7626476733 Added support for reporting operand token ranges 
to the ARM AsmParser.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 22:27:05 +00:00
Chris Lattner
c7f3ace20c use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 20:16:16 +00:00
Mon P Wang
e754d3fb85 Revert r100191 since it breaks objc in clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 18:43:02 +00:00
Mon P Wang
e33c848fa4 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 18:04:15 +00:00
Dale Johannesen
93d6a7e9c2 Teach AnalyzeBranch, RemoveBranch and the branch 
folder to be tolerant of debug info following the
branch(es) at the end of a block.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 01:38:09 +00:00
Jim Grosbach
1118b5e490 vml[as] are slow on 1136jf-s also. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 00:13:43 +00:00
Bill Wendling
5e1b55d672 Comment the changes for r98218 and friends inside the source code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-31 18:47:10 +00:00
Bob Wilson
100f090add Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 22:27:04 +00:00
Mon P Wang
808bab0169 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, 
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 20:55:56 +00:00
Chris Lattner
9b97a73ded Rip out the 'is temporary' nonsense from the MCContext interface to 
create symbols.  It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.

This fixes rdar://7807601.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 18:10:53 +00:00
Chris Lattner
f283e40b6a add a note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 17:02:02 +00:00
Johnny Chen
79c4d820b4 Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions. 
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd).  The table is specified via
a list of vectors, which can be:

{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 01:14:22 +00:00
Chris Lattner
0a00ed98f1 fix integer negates to use the proper type for the zero vectors, 
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:39:10 +00:00
Chris Lattner
b26fdcb48b fix vnot matching to explicitly specify the type of the 
input to be v8i8 or v16i8, which buildvectors get canonicalized to.

This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:08:07 +00:00
Bob Wilson
2cd1a12fe0 Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 04:01:23 +00:00
Bob Wilson
10bc69c726 Add a format argument to the N3V and N3VX classes, removing the N3Vf class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 03:56:52 +00:00
Johnny Chen
897dd0c588 Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set 
it as the format for the appropriate N3V*SL*<> classes.  These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.

Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):

	vmlal.s32	q3, d2, d10[0]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99690 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 01:03:13 +00:00
Jim Grosbach
9ab0427015 Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass 
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99678 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 00:09:12 +00:00
Johnny Chen
9ee9d7d493 Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified 
to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99676 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 23:49:07 +00:00
Johnny Chen
629c25cda6 Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8} 
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99659 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 22:28:56 +00:00
Johnny Chen
c6e704df8d Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not 
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 21:26:28 +00:00
Jim Grosbach
9a52d0c352 vldm/vstm can only do up to 16 double-word registers at a time. 
Radar 7797856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 18:41:09 +00:00
Johnny Chen
575c91cba7 Add N3RegFrm to represent "NEON 3 vector register format" instructions. 
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 18:32:20 +00:00
Johnny Chen
0a3dc10eba Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily 
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field.  The Vd, Vm fields are interpreted
the same between the two, though.

See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99590 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 01:07:59 +00:00
Jim Grosbach
7ec7a0e96b switch the flag for using NEON for SP floating point to a subtarget 'feature'. 
Re-commit. This time complete with testsuite updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:47:34 +00:00
Jim Grosbach
78e496e165 need to fix 'make check' tests first. revert for a moment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:34:05 +00:00
Jim Grosbach
bd17bc96bf switch the flag for using NEON for SP floating point to a subtarget 'feature' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:32:19 +00:00
Johnny Chen
da9283cd57 Removed instruction class NI from ARMInstrFormats.td. 
It doesn't seem to be used anywhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:11:56 +00:00
Jim Grosbach
6b2e8dc9a0 switch the use-vml[as] instructions flag to a subtarget 'feature' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:11:16 +00:00
Johnny Chen
2d2898e6e9 Add NVDupLnFrm and change NVDupLane class to use that format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 21:49:12 +00:00
Jim Grosbach
65cef00142 ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 20:48:50 +00:00
Johnny Chen
fa80bec349 Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to 
expect a Format arg.  N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99548 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 20:39:04 +00:00
Johnny Chen
e4614f7e84 Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ, 
instead of the current N2V.  Format of NVDupLane instances are set to NEONFrm
currently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 17:01:27 +00:00
Jim Grosbach
2676737e5e Make the use of the vmla and vmls VFP instructions controllable via cmd line. 
Preliminary testing shows significant performance wins by not using these
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 22:31:46 +00:00
Johnny Chen
69631b1327 Trivial formating change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 21:25:07 +00:00
Johnny Chen
2fadd6b221 Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm. 
NVCVTFrm will later be used to describe "vcvt with fractional bits".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 19:47:14 +00:00
Johnny Chen
7d85ac09f8 Reverted r99376. The disassembler will deal with the 2-reg format of these two 
N3VX instructions using special case code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 18:46:34 +00:00
Jim Grosbach
35075a7e81 tweak the arm if conversion heuristic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99402 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 16:15:14 +00:00
Johnny Chen
b7ba5781e6 Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 01:29:25 +00:00
Johnny Chen
c5f413a74c Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm, 
respectively, and add some more comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 00:57:50 +00:00
Jim Grosbach
fceabef52c try being more permissive for if-conversion on ARM V7. see what the nightly 
test run permformance numbers say as to whether it helps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 00:03:13 +00:00
Johnny Chen
a271174771 Renamed NVdImmFrm to N1RegModImmFrm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 23:09:14 +00:00
Johnny Chen
841e828702 Fix typo in the comment for N3VX class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 21:35:03 +00:00
Johnny Chen
be7849ee73 Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 21:30:12 +00:00
Johnny Chen
3ae9a57c74 Add New NEON Format NVdVmVCVTFrm. 
Converted some of the NEON vcvt instructions to this format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 21:25:38 +00:00
Johnny Chen
927b88f771 Add New NEON Format NVdVmImmFrm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 20:40:44 +00:00
Bob Wilson
df9a4f0591 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. 
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 18:54:46 +00:00
Bob Wilson
011355944b Fix bad indentation, 80-column violations, and trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 17:23:59 +00:00
Johnny Chen
785516adc5 Add New NEON Format NVdImmFrm. 
Ref: A7.4.6 One register and a modified immediate value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 16:43:47 +00:00
Bob Wilson
c289a0252b Rename some instructions to match the corresponding NEON opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 06:26:18 +00:00
Bob Wilson
11d9899759 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 06:20:33 +00:00
Bob Wilson
621f195243 Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 05:25:43 +00:00
Bob Wilson
62ef3c8910 Rename one more NEON instruction that I missed earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 20:31:39 +00:00
Bob Wilson
052ba45bf8 Regroup some instructions. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:22:06 +00:00
Bob Wilson
a6979754da Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:13:18 +00:00
Bob Wilson
58393bc3fd Remove some redundant instruction classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:02:38 +00:00
Bob Wilson
39842553e8 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 16:43:10 +00:00
Jeffrey Yasskin
fa72340ba0 Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 16:13:21 +00:00
Daniel Dunbar
5d067fe158 TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:36:22 +00:00
Bob Wilson
c88d072293 pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:20:40 +00:00
Bob Wilson
226036ee73 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:13:40 +00:00
Bob Wilson
d5fadaf56e Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with 
address register writeback.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:57:36 +00:00
Bob Wilson
4f4f93f9d6 Add variants of VST2, VST3 and VST4 with address register writeback, and 
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99093 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:45:18 +00:00
Bob Wilson
068b18be0d Add instructions for double-spaced VST3 and VST4 without address register 
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99090 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:15:48 +00:00
Bob Wilson
25eb5013d0 Add VST1 instructions with address register writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:54:36 +00:00
Bob Wilson
a1023645f8 Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with 
address register writeback.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:47:18 +00:00
Bob Wilson
41315282f9 Tidy some more comments and whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:39:53 +00:00
Bob Wilson
92cb9321a1 Add variants of VLD2, VLD3 and VLD4 with address register writeback, and 
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99080 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:10:51 +00:00
Bob Wilson
667a13e1be Tidy some comments and whitespace for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 19:57:03 +00:00
Bob Wilson
95ffecd4fe Rename some instructions for consistency and sanity: use "_UPD" suffix for 
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 18:35:24 +00:00
Bob Wilson
00bf1d93d7 Add instructions for double-spaced VLD3 and VLD4 without address register 
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99065 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 18:14:26 +00:00
Bob Wilson
99493b2b53 Add VLD1 instructions with address register writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99062 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 17:59:03 +00:00
Bob Wilson
55c9cb5a22 Revert the rest of 98679. 
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 06:34:02 +00:00
Bob Wilson
98330ff8e3 Fix a very bad typo. Since the register number was off by one, the ARM 
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 06:05:13 +00:00
Johnny Chen
caa608e97c Add NLdStFrm Format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 00:17:00 +00:00
Johnny Chen
e86425f224 Revert r98679. The disassembler will be updated to depend on the existence of 
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99013 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 23:50:27 +00:00
Bob Wilson
76a312b7d1 Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 22:51:32 +00:00
Johnny Chen
81f04d59f6 Renumber LdStExFrm from 28 to 11 and shift the existing format values to make 
room for it.  This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98967 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 17:39:00 +00:00
Chris Lattner
60e9eac357 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:33:51 +00:00
Jeffrey Yasskin
c3e45f1ee2 Remove a memory leak from ThumbTargetMachine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:25:28 +00:00
Daniel Dunbar
6b7c2cf5d4 Fix -Asserts warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98928 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 03:18:23 +00:00
Bob Wilson
50622ce8cf Update comment to refer to the right filename. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 23:57:57 +00:00
Anton Korobeynikov
341ab138fb Get rid of target-specific fp <-> int nodes when still I'm here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 22:35:45 +00:00