6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-25 14:32:53 +00:00
Code Issues Projects Releases Wiki Activity
38,125 Commits 39 Branches 0 Tags 277 MiB
80b09fe8bc
Commit Graph

8860 Commits

Author SHA1 Message Date
Evan Cheng
20ccded7de Remove isImplicitDef TargetInstrDesc flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-15 00:19:36 +00:00
Evan Cheng
da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-15 00:03:38 +00:00
Dale Johannesen
8f5422c24b Implement the real calling convention for ppc32 Altivec: 
vectors go at the end of the memory area, after all
non-vector parameters.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48364 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 17:41:26 +00:00
Evan Cheng
029d9dafa0 Fix some 80 col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48361 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 07:46:48 +00:00
Evan Cheng
172b794cd5 Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48360 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 07:39:27 +00:00
Evan Cheng
17ed8fa63d Add debugging stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48359 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 07:13:42 +00:00
Chris Lattner
69a74ab421 Add an issue that is preventing instcombine from doing a simplification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48356 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 06:00:19 +00:00
Dan Gohman
704df9fcbd Use SDTNone instead of duplicating it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48346 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 23:07:40 +00:00
Christopher Lamb
6634e26aa1 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 05:47:01 +00:00
Dale Johannesen
d75686a471 Do not promote float params to double in varargs 
calls here.  This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48310 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 23:40:01 +00:00
Chris Lattner
58d74910c6 Reimplement the parameter attributes support, phase #1. hilights: 
1. There is now a "PAListPtr" class, which is a smart pointer around
   the underlying uniqued parameter attribute list object, and manages
   its refcount.  It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
   the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
   longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
   ParamAttrsWithIndex's, no need to make a SmallVector of a specific 
   size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
   dereferencing the pointer is simplified to just access the 
   PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
   bit simpler.

Phase #2 will rename some stuff (e.g. PAListPtr) and do other less 
invasive changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48289 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 17:45:29 +00:00
Evan Cheng
c8e3b147ee Clean up my own mess. 
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48279 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 07:02:50 +00:00
Dale Johannesen
404d99010d One more bit of Altivec parameter passing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48269 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 00:49:20 +00:00
Dale Johannesen
75092de483 Implement Altivec passing to varargs functions on ppc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48264 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 00:22:17 +00:00
Anton Korobeynikov
4d86e2a6b8 Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48257 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 22:38:53 +00:00
Dan Gohman
bfae83139d Use PassManagerBase instead of FunctionPassManager for functions 
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 22:29:46 +00:00
Chris Lattner
e12ecf272d Implement basic support for the 'f' register class constraint. This basically 
works, but probably won't if you mix it with 't' or 'u' yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48243 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 19:50:13 +00:00
Chris Lattner
1d38677e34 coalesce away 80-bit floating point copies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48241 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 19:30:09 +00:00
Chris Lattner
07f7cc3ddb convert a massive if statement to a switch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48240 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 19:28:17 +00:00
Chris Lattner
fce84acbbc start handling the 'f' x87 constraint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48239 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 19:06:29 +00:00
Christopher Lamb
1bc1008b38 Missed part of recommit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48224 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 10:27:36 +00:00
Christopher Lamb
1fab4a6bbb Recommitting parts of r48130. These do not appear to cause the observed failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 10:09:17 +00:00
Evan Cheng
fa2f786f4e If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48220 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:54:14 +00:00
Evan Cheng
676dd7c80b When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:19:34 +00:00
Evan Cheng
204496d58e In 32-bit mode, mark 64-bit GPR's as unallocatable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48217 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:16:00 +00:00
Nick Lewycky
3c78697a3c Fix the build on gcc 4.2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48212 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 05:56:09 +00:00
Chris Lattner
447ff68c08 Change the model for FP Stack return to use fp operands on the 
RET instruction instead of using FpSET_ST0_32.  This also generalizes
the code to handling returning of multiple FP results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48209 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 03:23:40 +00:00
Dan Gohman
034f60ed24 Generalize ExpandIntToFP to handle the case where the operand is legal 
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 01:59:03 +00:00
Chris Lattner
183275a627 abort with an assert instead of a cerr to get line# 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48199 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 23:56:08 +00:00
Scott Michel
405fba12ce - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency. 
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48197 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 23:49:09 +00:00
Chris Lattner
03fdec04d1 Don't emit FP_REG_KILL into a block that just returns. Nothing 
can be live out of the block anyway, so it isn't needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48192 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 23:34:12 +00:00
Dale Johannesen
82e4289fc7 Disable prolog code that aligns the stack when a 
local object of >16 byte alignment exists.  It does not
work and getting it to work is not trivial, as explained
in the comment.  This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.

(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec.  So I think disabling it is OK.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48188 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 22:59:46 +00:00
Bill Wendling
4a66e9a57e Change the "enable/disable" mechanism so that we can enable PPC register 
scavenging for 32-bit and 64-bit separately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 22:49:16 +00:00
Chris Lattner
8e6da15e54 Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to 
copyfromreg/copytoreg instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 21:08:41 +00:00
Evan Cheng
d2cde68855 Default ISD::PREFETCH to expand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 19:38:10 +00:00
Evan Cheng
4499e495ea Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 19:31:26 +00:00
Chris Lattner
cb341de0e2 fix 80 col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48166 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 18:55:53 +00:00
Nicolas Geoffray
9348c69dcf Stylistic modifications. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48158 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 17:46:45 +00:00
Scott Michel
78c47fa50b Integer comparison tests for CellSPU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48152 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 16:58:52 +00:00
Scott Michel
5b8f82e35b Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's 
return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 15:42:14 +00:00
Nicolas Geoffray
0404cd97e4 Add description of individual bits in CR. This fix PR1765. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 14:12:10 +00:00
Christopher Lamb
3feb0170a8 Allow insert_subreg into implicit, target-specific values. 
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 06:12:08 +00:00
Dale Johannesen
b8cafe3427 Increase ISD::ParamFlags to 64 bits. Increase the ByValSize 
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff.  Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and 
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 02:17:22 +00:00
Chris Lattner
dc9971a2e3 Darwin PPC64 indirect call target goes in X12, not R12. This fixes these 
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48120 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 20:49:33 +00:00
Chris Lattner
5e09da236e cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48119 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 20:31:11 +00:00
Chris Lattner
68a0d0984d make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48118 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 20:12:44 +00:00
Chris Lattner
f30e1cf9b7 teach X86InstrInfo::copyRegToReg how to copy into ST(0) from 
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48107 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 09:15:31 +00:00
Chris Lattner
5c927500c8 add some code to support cross-register class copying from 
RST -> RFP{32/64/80}.  We only handle ST(0) for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48104 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 08:46:19 +00:00
Chris Lattner
90b347dc90 rearrange some code, no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48101 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 07:58:04 +00:00
Chris Lattner
8dc023f684 claim ST(x) registers are 80 bits, which is true. This doesn't affect 
codegen yet because these can't be spilled (they don't exist until after RA).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48098 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 07:49:01 +00:00
Chris Lattner
afb23f48a4 rename FP_SETRESULT -> FP_SET_ST0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48094 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 07:08:44 +00:00
Chris Lattner
6fa2f9c636 rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for 
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48093 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 07:05:32 +00:00
Chris Lattner
67f453aae7 Finish implementing a readme entry: when inserting an i64 variable 
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48090 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 05:42:06 +00:00
Chris Lattner
f68cbceb17 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48064 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 01:08:22 +00:00
Chris Lattner
62098040a1 Implement a readme entry, compiling 
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48063 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 01:05:04 +00:00
Chris Lattner
19f7969f81 1) Improve comments. 
2) Don't try to insert an i64 value into the low part of a 
   vector with movq on an x86-32 target.  This allows us to 
   compile:

__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:

_doload64:
	movaps	LCPI1_0, %xmm0
	ret

instead of:

_doload64:
	subl	$28, %esp
	movl	$0, 4(%esp)
	movl	$1, (%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48057 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-08 22:59:52 +00:00
Chris Lattner
c9517fb6eb minor simplifications to this code, don't create a dead 
SCALAR_TO_VECTOR on paths that end up not using it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48056 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-08 22:48:29 +00:00
Chris Lattner
b607f9c822 This one looks easy, add a note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48055 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-08 22:32:39 +00:00
Chris Lattner
f658ad10f6 move these to the appropriate file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48054 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-08 22:28:45 +00:00
Dale Johannesen
7f96f3912e More ppc32 byval handling (bug fixes). Things 
are looking pretty good now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48043 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-08 01:41:42 +00:00
Evan Cheng
27b7db549e Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-08 00:58:38 +00:00
Dan Gohman
a2fcff4d97 Add support for calls with i128 return values on ppc64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48041 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-08 00:19:12 +00:00
Bill Wendling
5f5bf3a3fd PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this 
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48030 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:49:02 +00:00
Dan Gohman
9ed06db5c8 Add support for lowering 128-bit shifts on ppc64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48029 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:36:53 +00:00
Dale Johannesen
8419dd6aa6 Next bits of PPC byval handling. Basically functional 
but there are bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48028 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:27:40 +00:00
Chris Lattner
af8ee84fe5 Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48027 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:18:24 +00:00
Chris Lattner
49bd37d369 Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work 
with 32 or 64-bit operands/results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48026 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:13:51 +00:00
Chris Lattner
d1108222fd mark frem as expand for all legal fp types on x86, regardless of whether 
we're using SSE or not.  This fixes PR2122.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48006 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 06:36:32 +00:00
Gabor Greif
2cf36e0772 some more spelling changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47996 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-06 10:51:21 +00:00
Scott Michel
4cb8bd8eff Refine Cell's i64 constant generation code to cover more constants where the 
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47985 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-06 04:02:54 +00:00
Andrew Lenharth
6ad150baac gcc likes things spelled correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47981 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 23:41:37 +00:00
Dale Johannesen
1f797a32fd Next bit of PPC ByVal handling; call-site code seems 
correct now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47978 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 23:31:27 +00:00
Scott Michel
ad2715e0d7 - Fix support for "special" i64 immediates that can be loaded 
using IL, ILA, et. al. v2i64 and i64 are now supported by
  the select bits (SELB) instruction.

- Add missing comparison operations (testcase forthcoming)

- More multiclass refactoring.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47973 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 23:02:02 +00:00
Chris Lattner
4d93b2f16d evan implemented this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47948 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 17:11:51 +00:00
Evan Cheng
e9083d669a isTwoAddress = 1 -> Constraints. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47941 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 08:19:16 +00:00
Evan Cheng
e7b8a8b713 PSLLWri etc. are two-address instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47940 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 08:11:27 +00:00
Chris Lattner
063d825208 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47939 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 07:22:39 +00:00
Evan Cheng
b7664c6173 Ignore debugging related instructions if they get this far. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47934 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 02:34:36 +00:00
Evan Cheng
0b21390a86 Rather than asserting. Dump out the MI that we are not able to encode and abort. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47933 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 02:08:03 +00:00
Evan Cheng
6fd599fa69 Add a target lowering hook to control whether it's worthwhile to compress fp constant. 
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47931 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 01:30:59 +00:00
Andrew Lenharth
d19189e990 64bit CAS on 32bit x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47929 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 01:15:49 +00:00
Evan Cheng
6130f66eaa Refactor code. Remove duplicated functions that basically do the same thing as 
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47927 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 00:59:57 +00:00
Bill Wendling
2b5fab67c1 Removed spurious EnablePPCRS check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47918 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 23:27:33 +00:00
Dale Johannesen
5b3b695c2f Move PPC lowering functions into PPCTargetLowering 
class (cosmetic).  First piece of byval implementation;
this doesn't work yet.  No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47917 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 23:17:14 +00:00
Bill Wendling
880d0f6018 Use a command-line option to turn register scavenging on/off for PPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 23:13:51 +00:00
Andrew Lenharth
a76e2f0331 x86-64 atomics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47903 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 21:13:33 +00:00
Evan Cheng
32967d2c7d 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47878 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 03:20:06 +00:00
Evan Cheng
07b7ea1a48 Remove -always-fold-and-in-test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47871 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 00:40:35 +00:00
Dan Gohman
4c1fa61652 Add support for lowering i64 SRA_PARTS and friends on x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47865 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-03 22:22:09 +00:00
Bill Wendling
7194aaf738 This is the initial check-in for adding register scavenging to PPC. (Currently, 
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-03 22:19:16 +00:00
Devang Patel
41e2397b72 s/isReturnStruct()/hasStructRetAttr()/g 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47857 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-03 21:46:28 +00:00
Chris Lattner
53b7277917 another random note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47831 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 19:29:42 +00:00
Chris Lattner
150943c178 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47830 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 19:27:34 +00:00
Chris Lattner
767486b1d5 Evan implemented these. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47828 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 18:05:14 +00:00
Chris Lattner
3be4893dce Evan implemented this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47827 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 17:56:29 +00:00
Chris Lattner
ff939213db add support for lvsl, fixing PR1481 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47825 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 08:54:27 +00:00
Chris Lattner
4e22012ea4 add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47824 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 08:47:13 +00:00
Chris Lattner
2299fec22c refactor intrinsic handling code out into its own method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47823 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 08:29:41 +00:00
Chris Lattner
d9a706ecf9 fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector. 
Now they all pass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47820 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 08:14:45 +00:00
Chris Lattner
9152daf868 insertelement got the wrong operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47819 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 08:10:16 +00:00
Chris Lattner
e05252b476 Several changes: 
* Simplify handling of byval, making it easier to understand and more 
    consistent.  This fixes PR2065.
  * Clean up and simplify handling of GEPs.  I can actually understand it now!
  * Implement support for GEP'ing into vectors, this fixes
    SingleSource/UnitTests/Vector/build2 among others.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47818 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 08:07:24 +00:00
Chris Lattner
939732afc2 Fix a bug I introduced in constant array and constant vector handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47816 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 05:46:57 +00:00
Chris Lattner
b1855add0c implement shufflevector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47815 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 05:41:07 +00:00
Chris Lattner
0452ed6bd6 implement extractelement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47812 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 03:57:08 +00:00
Chris Lattner
33a44d928b implement insertelement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47811 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 03:52:39 +00:00
Chris Lattner
90683abb56 respect isSigned for vector types, fixing sdiv of vectors etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47810 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 03:41:23 +00:00
Chris Lattner
32cba8e063 print the attribute in the right place, this fixes function returning vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47809 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 03:39:43 +00:00
Chris Lattner
b61d41b8dd vector types are simple types. This fixes div/rem of vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47807 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 03:33:31 +00:00
Chris Lattner
85feab6c57 Print vector types appropriately. This gets basic vector code working 
(PR1126)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47806 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 03:29:50 +00:00
Chris Lattner
0a3d4d971d rename PT -> VT for VectorTypes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47805 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 03:18:46 +00:00
Chris Lattner
c8b6d339d7 Print i32/i64 integer constants as 1u instead of ((unsigned int)1). 
Use dyn_cast better.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47804 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 03:16:38 +00:00
Chris Lattner
a11deb0392 Move pr717 to here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47803 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 02:51:40 +00:00
Andrew Lenharth
fe0753efba good catch anton 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47800 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-01 23:18:21 +00:00
Andrew Lenharth
ce1105da43 make CAS work 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47799 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-01 22:27:48 +00:00
Andrew Lenharth
26ed8697d4 all but CAS working on x86 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47798 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-01 21:52:34 +00:00
Andrew Lenharth
ea7da50e5a Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47795 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-01 13:37:02 +00:00
Anton Korobeynikov
8213f9cf94 Use enumeration for preffered EH dwarf encoding reason 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47770 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 22:09:08 +00:00
Anders Carlsson
b26947e967 Use the correct instruction encodings for the 64-bit MMX movd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47740 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 01:35:12 +00:00
Evan Cheng
d703ed6aed Added option -align-loops=<true/false> to disable loop aligner pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47736 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 23:29:57 +00:00
Dale Johannesen
28d08fdb9f Interface of getByValTypeAlignment differed between 
generic & x86 versions; change generic to follow x86
and improve comments.  Add PPC version (not right
for non-Darwin.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47734 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 22:31:51 +00:00
Lauro Ramos Venancio
f3c630e3fc Initialize TextAlignFillValue. Fix revision 47703. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47732 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 22:14:09 +00:00
Lauro Ramos Venancio
1f4a887e32 Avoid collisions in value names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47725 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 20:26:04 +00:00
Chris Lattner
e29536ca8d add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47720 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 17:21:27 +00:00
Evan Cheng
e526d8a955 Set to default: x86 no longer fold and into test if it has more than one use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47711 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 07:46:38 +00:00
Chris Lattner
6baaf91598 Sparc backend doesn't support debug info yet, mark the nodes as expand. This fixes a crash on 
test/DebugInfo/funccall.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47709 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 05:54:25 +00:00
Chris Lattner
a4b521598a Fix CodeGen/Generic/storetrunc-fp.ll on sparc, PR2105 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47707 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 05:48:04 +00:00
Chris Lattner
61273d55e9 fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47706 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 05:44:20 +00:00
Chris Lattner
48840f8db9 target-indep codegen memcpy lowering issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47705 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 05:34:27 +00:00
Chris Lattner
daf6c541b2 Add a random not very important note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47704 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 04:52:59 +00:00
Evan Cheng
fb8075d03f Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47703 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 00:43:03 +00:00
Eli Friedman
41ce5b82da A few more small things I've run into. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47702 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 00:21:43 +00:00
Anton Korobeynikov
7b1b7f5c5a EHPreferredDataFormat hook for PPC targets. Looks like Darwin 
uses the same encoding everywhere. Linux FIXME'ed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47701 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 23:49:15 +00:00
Anton Korobeynikov
cee750fb1e Preparation step for some cleanup/generalization in EH information emission: 
provide TAI hook for selection of EH data emission format. Currently unused.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47699 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 23:33:50 +00:00
Dan Gohman
ec59b95a19 Don't hard-code the mask size to be 32, which is incorrect on ppc64 
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47692 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 21:12:32 +00:00
Evan Cheng
fd1074f171 This is done. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47688 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 20:26:32 +00:00
Bill Wendling
6ef781f3ce Final de-tabification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 06:33:05 +00:00
Chris Lattner
b09916bdfb Make X86TargetLowering::LowerSINT_TO_FP return without creating a dead 
stack slot and store if the  SINT_TO_FP is actually legal.  This allows
us to compile:

double a(double b) {return (unsigned)b;}

to:

_a:
	cvttsd2siq	%xmm0, %rax
	movl	%eax, %eax
	cvtsi2sdq	%rax, %xmm0
	ret

instead of:

_a:
	subq	$8, %rsp
	cvttsd2siq	%xmm0, %rax
	movl	%eax, %eax
	cvtsi2sdq	%rax, %xmm0
	addq	$8, %rsp
	ret

crazy.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47660 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 05:57:41 +00:00
Chris Lattner
22eedf4eec this code is correct but strange looking ;-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47659 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 05:48:44 +00:00
Chris Lattner
d0ba2a9c14 Compile x86-64-and-mask.ll into: 
_test:
	movl	%edi, %eax
	ret

instead of:

_test:
        movl    $4294967295, %ecx
        movq    %rdi, %rax
        andq    %rcx, %rax
        ret

It would be great to write this as a Pat pattern that used subregs 
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47658 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 05:47:54 +00:00
Evan Cheng
d36531249a Spiller now remove unused spill slots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47657 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 03:04:06 +00:00
Dan Gohman
b3564aa836 Convert the last remaining users of the non-APInt form of 
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47654 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 01:23:58 +00:00
Chris Lattner
ba309d43aa add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47652 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 01:17:20 +00:00
Arnold Schwaighofer
258bb1b8e8 Refactor according to Evan's and Anton's suggestions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47635 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 22:21:54 +00:00
Bill Wendling
e6d088acc9 Rename PrintableName to Name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 21:47:57 +00:00
Bill Wendling
74ab84c31e Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool 
would have been a Godsend here!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 21:11:01 +00:00
Arnold Schwaighofer
16a3e52d08 Correct function comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47606 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 17:50:59 +00:00
Bill Wendling
85db3a96b4 De-tabify 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47600 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 10:57:23 +00:00
Arnold Schwaighofer
a2a4b475fc Add support for intermodule tail calls on x86/32bit with 
GOT-style position independent code. Before only tail calls to
protected/hidden functions within the same module were optimized.
Now all function calls are tail call optimized.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47594 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 10:21:54 +00:00
Arnold Schwaighofer
865c68188a Change the lowering of arguments for tail call optimized 
calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47593 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 09:19:59 +00:00
Dan Gohman
545914311a Revert the assert for MUL_LOHI with an unused high result; Chris 
pointed out that this isn't correct at -O0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47575 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-25 22:43:48 +00:00