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336 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
62204220e1 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 23:56:31 +00:00
Benjamin Kramer
b0bbfaf3b3 Hexagon: Avoid unused variable warnings in Release builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185445 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-02 17:24:00 +00:00
Richard Trieu
a785a7bf51 Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185392 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-01 23:06:23 +00:00
Richard Trieu
d1fe8d5212 Change assert(0 && "text") to llvm_unreachable(0 && "text") 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185243 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 23:46:19 +00:00
Richard Trieu
c09324483c Fix broken asserts that never fire. 
Change assert("text") to assert(0 && "text").  The first case is a const char *
to bool conversion, which always evaluates to true, never triggering the
assert.  The second case will always trigger the assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185227 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 21:54:25 +00:00
Chad Rosier
5b3fca50a0 The getRegForInlineAsmConstraint function should only accept MVT value types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-22 18:37:38 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:36:55 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-16 20:34:27 +00:00
Andrew Trick
b86a0cdb67 Machine Model: Add MicroOpBufferSize and resource BufferSize. 
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 04:49:57 +00:00
Bill Wendling
54a56fad36 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:19:56 +00:00
Bill Wendling
6a2e7ac0b6 Cache the TargetLowering info object as a pointer. 
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 00:43:09 +00:00
Ahmed Bougacha
23ed37a6b7 Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-31 23:45:26 +00:00
Andrew Trick
6e0b2a0cb0 Order CALLSEQ_START and CALLSEQ_END nodes. 
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-29 22:03:55 +00:00
Jyotsna Verma
ee6e242e78 Hexagon: Typo fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-28 19:01:45 +00:00
Andrew Trick
ac6d9bec67 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-25 02:42:55 +00:00
Benjamin Kramer
a32218a7ec Hexagon: Make helper functions static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182588 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-23 15:43:11 +00:00
Jyotsna Verma
b4b14070a4 Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182390 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 15:54:32 +00:00
Matt Arsenault
225ed7069c Add LLVMContext argument to getSetCCResultType 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-18 00:21:46 +00:00
Benjamin Kramer
033f3b7eb6 Don't cast away constness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 11:39:41 +00:00
Rafael Espindola
992c3817ea Remove dead calls to addFrameMove. 
Without a PROLOG_LABEL present, the cfi instructions are never printed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182016 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 15:08:37 +00:00
Jyotsna Verma
a29a8965e2 Hexagon: Pass to replace tranfer/copy instructions into combine instruction 
where possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 18:54:06 +00:00
Jyotsna Verma
36e1b51438 Hexagon: Add patterns to generate 'combine' instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 17:16:38 +00:00
Jyotsna Verma
91eadc6d69 Hexagon: ArePredicatesComplement should not restrict itself to TFRs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 16:36:34 +00:00
Jyotsna Verma
9c9bf9a240 Hexagon: Remove dead-code after unconditional return from addPreSched2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 15:33:27 +00:00
Duncan Sands
b99052ce4a Suppress GCC compiler warnings in release builds about variables that are only 
read in asserts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181689 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-13 07:50:47 +00:00
Rafael Espindola
4a971705bc Remove the MachineMove class. 
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-13 01:16:13 +00:00
Rafael Espindola
d84ccfaf50 Change getFrameMoves to return a const reference. 
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-11 02:38:11 +00:00
Jyotsna Verma
fd4ccda4a5 Fix unused variable error. 
Earlier, this variable was used in an assert and was causing failure on
darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181630 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 21:44:02 +00:00
Jyotsna Verma
cdfb55d15b Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore. 
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181628 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 20:58:11 +00:00
Jyotsna Verma
1a35b8e2eb Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 20:27:34 +00:00
Rafael Espindola
6e53180db1 Remove unused argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 18:16:59 +00:00
Rafael Espindola
3a0d00eef9 Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181606 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 16:53:12 +00:00
Jyotsna Verma
80d81aa8ba Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions. 
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181535 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-09 19:16:07 +00:00
Jyotsna Verma
f4f60b10e4 Hexagon: Use relation map for getMatchingCondBranchOpcode() and 
getInvertedPredicatedOpcode() functions instead of switch cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181530 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-09 18:25:44 +00:00
Jyotsna Verma
f931f691ee Hexagon: Fix Small Data support to handle -G 0 correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181344 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 19:53:00 +00:00
Jyotsna Verma
ddcf3ee768 Reverting r181331. 
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 17:12:35 +00:00
Jyotsna Verma
81fda3b4d5 Hexagon: Fix Small Data support to handle -G 0 correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181331 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 16:42:15 +00:00
Jyotsna Verma
8cc93593cd Hexagon: Set accessSize and addrMode on all load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 15:06:29 +00:00
Krzysztof Parzyszek
942940a326 Print IR from Hexagon MI passes with -print-before/after-all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181255 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 21:58:00 +00:00
Krzysztof Parzyszek
b072090f39 Cleanup of the HexagonTargetMachine setup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181250 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 21:25:45 +00:00
Jyotsna Verma
1a7eab3878 Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 18:49:23 +00:00
Krzysztof Parzyszek
ed6fe299cf Make references to HexagonTargetMachine "const". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181233 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 18:38:37 +00:00
Krzysztof Parzyszek
cc420a0911 Use consistent function names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-04 01:30:49 +00:00
Reid Kleckner
aa35a56975 Fix missing include in Hexagon code for Release+Asserts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 00:54:56 +00:00
Jyotsna Verma
d4f8a6b9e9 reverting r180953 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 22:10:59 +00:00
Jyotsna Verma
8a3f50038f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:21:57 +00:00
Pranav Bhandarkar
02d937d864 Hexagon - Add peephole optimizations for zero extends. 
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 20:22:51 +00:00
Jyotsna Verma
f945d09d53 Hexagon: Honor __builtin_expect by using branch probabilities. 
* lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
  Given a jump opcode return the right pred.new jump opcode with
  a taken vs not-taken hint based on branch probabilities provided
  by the target independent module.
  * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
  * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
  Enhance existing function use branch probabilities like
  HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180923 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 15:39:30 +00:00
Jyotsna Verma
6ea706e40e Hexagon: Use multiclass for Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 21:37:34 +00:00
Jyotsna Verma
f9759c9f08 Hexagon: Clear isKill flag on the predicate register in 
PredicateInstruction function.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180884 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 21:27:30 +00:00
Jyotsna Verma
42ba77db53 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 21:17:40 +00:00
Jyotsna Verma
197c833ee1 Hexagon: Define relations for GP-relative instructions. 
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180144 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 21:05:55 +00:00
Jyotsna Verma
47089c91ae Hexagon: Remove assembler mapped instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 19:15:55 +00:00
Jyotsna Verma
3d7b39e7d4 Hexagon: Remove duplicate instructions to handle global/immediate values 
for absolute/absolute-set addressing modes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:11:46 +00:00
Tim Northover
6265d5c91a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 12:32:17 +00:00
Michael Liao
2a8bea7a8e ArrayRefize getMachineNode(). No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 22:22:57 +00:00
Jyotsna Verma
1877dc00e7 Hexagon: Set isPredicatedNew flag on predicate new instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179388 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 18:01:06 +00:00
Jyotsna Verma
c1406d76ec Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179387 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 17:46:52 +00:00
Jyotsna Verma
0e58d92628 Hexagon: Expand br_cc. 
It fixes following tests for Hexagon:

CodeGen/Generic/2003-07-29-BadConstSbyte.ll
CodeGen/Generic/2005-10-21-longlonggtu.ll
CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
CodeGen/Generic/MachineBranchProb.ll
CodeGen/Generic/builtin-expect.ll
CodeGen/Generic/pr12507.ll



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178794 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 21:18:26 +00:00
Duncan Sands
0857a6fd33 Remove unused typedef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178462 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-01 13:46:15 +00:00
Duncan Sands
79f615cbfe There is no longer any need to silence this compiler warning as the warning has 
been turned off globally.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178451 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-31 17:44:09 +00:00
Jyotsna Verma
2a88555e0d Hexagon: Add emitFrameIndexDebugValue function to emit debug information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178368 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-29 21:09:53 +00:00
Jyotsna Verma
65063feac5 Hexagon: Disable DwarfUsesInlineInfoSection flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178345 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-29 15:46:12 +00:00
Jyotsna Verma
810848d5b3 Hexagon: Replace switch-case in isDotNewInst with TSFlags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178281 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 19:44:04 +00:00
Jyotsna Verma
e41c7d4890 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178279 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 19:34:49 +00:00
Jyotsna Verma
4f2ef94d6a Hexagon: Use multiclass for gp-relative instructions. 
Remove noV4T gp-relative instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 16:25:57 +00:00
Tim Northover
fe37e6279e Switch to LLVM support function abs64 to keep VS2008 happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178141 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-27 13:15:08 +00:00
Jyotsna Verma
0f680703eb Hexagon: Disable optimizations at O0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178132 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-27 11:14:24 +00:00
Jyotsna Verma
7bb9585c6e Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 15:43:57 +00:00
Jyotsna Verma
a8c8c45838 Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/HexagonMCInst.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178030 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 15:34:22 +00:00
Jyotsna Verma
97e602b574 Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-22 18:41:34 +00:00
Jyotsna Verma
cec50e6da2 Hexagon: Removed asserts regarding alignment and offset. 
We are warning the user about the alignment, so we should not assert.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-14 19:08:03 +00:00
Jakub Staszak
760fa5dc80 Cleanup #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-10 13:11:23 +00:00
Tom Stellard
3ef5383b35 DAGCombiner: Use correct value type for checking legality of BR_CC v3 
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-08 15:36:57 +00:00
Jyotsna Verma
86df21767a Hexagon: Add patterns for zero extended loads from i1->i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-08 14:15:15 +00:00
Jyotsna Verma
a4dd8d6732 Hexagon: Handle i8, i16 and i1 Var Args. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176647 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 20:28:34 +00:00
Jyotsna Verma
b6716187ca Hexagon: Add support to lower block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 19:10:28 +00:00
Jyotsna Verma
0d44328ce8 reverting patch 176508. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 20:29:23 +00:00
Jyotsna Verma
c34f17140f Hexagon: Add support for lowering block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 19:37:46 +00:00
Jyotsna Verma
18daead3ff Hexagon: Expand addc, adde, subc and sube. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 19:04:47 +00:00
Jyotsna Verma
9feabc23b3 Hexagon: Use MO operand flags to mark constant extended instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176500 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 18:51:42 +00:00
Jyotsna Verma
ee0ef13eba Hexagon: Add encoding bits to the TFR64 instructions. 
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 18:42:28 +00:00
Andrew Trick
1c01af8f26 Added FIXME for future Hexagon cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176400 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-02 01:43:08 +00:00
Jyotsna Verma
ef94c6c85e Hexagon: Add constant extender support framework. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-01 17:37:13 +00:00
Andrew Trick
667754e239 Remove code copied from GenRegisterInfo.inc. 
There's no apparent reason this code was copied from generated source
into a .cpp. It sets a bad example for those working on other targets
and trying to understand the register info API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175849 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-22 01:15:08 +00:00
Eli Bendersky
700ed80d3d Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-21 20:05:00 +00:00
Anshuman Dasgupta
6585d3b64b Hexagon: Expand cttz, ctlz, and ctpop for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-21 19:39:40 +00:00
Jim Grosbach
3450f800aa Update TargetLowering ivars for name policy. 
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-20 21:13:59 +00:00
Jyotsna Verma
d6c98ae638 Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. 
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175634 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-20 16:13:27 +00:00
Jyotsna Verma
383c6fc458 Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with 
HexagonInstrFormats.td.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175537 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-19 18:18:36 +00:00
Jyotsna Verma
55a98b00c1 Hexagon: Set appropriate TSFlags to the loads/stores with global address to 
support constant extension.

This patch doesn't introduce any functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175280 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-15 17:52:07 +00:00
Jyotsna Verma
84a2c2bbb5 Hexagon: Change insn class to support instruction encoding. 
This patch doesn't introduce any functionality changes.
It adds some new fields to the Hexagon instruction classes and
changes their layout to support instruction encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 19:57:17 +00:00
Jyotsna Verma
5e3100afef Hexagon: Use multiclass for absolute addressing mode loads. 
This patch doesn't introduce any functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175187 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 18:15:29 +00:00
Anshuman Dasgupta
666e0d3bc4 Hexagon: add support for predicate-GPR copies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-13 22:56:34 +00:00
Jyotsna Verma
f6563427c4 Hexagon: Use absolute addressing mode loads/stores for global+offset 
instead of redefining separate instructions for them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-13 21:38:46 +00:00
Andrew Trick
ecb8c2ba60 MIsched: HazardRecognizers are created for each DAG. Free them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-13 19:22:27 +00:00
Jyotsna Verma
6b8d2026ba Hexagon: Add support to generate predicated absolute addressing mode 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-12 16:06:23 +00:00
Krzysztof Parzyszek
71490fa946 Extend Hexagon hardware loop generation to handle various additional cases: 
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174904 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-11 21:37:55 +00:00
Krzysztof Parzyszek
ce55d91ec9 Implement HexagonInstrInfo::analyzeCompare. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174901 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-11 20:04:29 +00:00
Jyotsna Verma
1d3d2c57f5 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle 
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 19:20:45 +00:00