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246 Commits

Author SHA1 Message Date
Richard Barton
c8f2fcc9a3 Correct decoder for T1 conditional B encoding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 09:12:53 +00:00
Silviu Baranga
169e9ba2b2 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 09:28:27 +00:00
Kevin Enderby
2d524b0765 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits 
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 22:41:56 +00:00
Silviu Baranga
b422d0b65e Fixed disassembler for vstm/vldm ARM VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 16:38:40 +00:00
Richard Barton
0a552d611e Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 09:43:18 +00:00
Evan Cheng
cac31de146 Specify cpu to unbreak tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-26 01:38:10 +00:00
Kevin Enderby
24e767d076 Add missing test cases for ARM VLD3 (single 3-element structure to all lanes) 
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 17:45:56 +00:00
Kevin Enderby
2c66edf434 Add missing test cases for ARM VLD4 (single 4-element structure to all lanes) 
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155444 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 15:55:00 +00:00
Silviu Baranga
35ee7d28a6 Added support for disassembling unpredictable swp/swpb ARM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 14:18:57 +00:00
Silviu Baranga
6b9f97dd89 Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 14:09:07 +00:00
Silviu Baranga
fa1ebc6abe Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 13:12:50 +00:00
Silviu Baranga
e546c4c9c3 Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 13:02:55 +00:00
Silviu Baranga
9e71231309 Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 12:48:43 +00:00
Kevin Enderby
c5a2a33938 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-17 00:49:27 +00:00
Kevin Enderby
b318cc16c9 Fixed a case of ARM disassembly getting an assert on a bad encoding 
of a VST instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:40:17 +00:00
Kevin Enderby
a69da35c12 Fix ARM disassembly of VLD instructions with writebacks.  And add test a case 
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 00:25:40 +00:00
Evan Cheng
82509e5c62 Fix a number of problems with ARM fused multiply add/subtract instructions. 
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 00:13:00 +00:00
Silviu Baranga
1c01249191 Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-05 16:19:29 +00:00
Silviu Baranga
82e1bba0e4 Added support for handling unpredictable arithmetic instructions on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-05 16:13:15 +00:00
Silviu Baranga
50ac2e9229 Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 15:20:39 +00:00
Eli Bendersky
cc85160672 Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 
* Removed test/lib/llvm.exp - it is no longer needed 
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
  left in the test suite so this code is no longer required. test/lit.cfg is
  now much shorter and clearer 
* Removed a lot of duplicate code in lit.local.cfg files that need access to
  the root configuration, by adding a "root" attribute to the TestingConfig
  object. This attribute is dynamically computed to provide the same
  information as was previously provided by the custom getRoot functions. 
* Documented the config.root attribute in docs/CommandGuide/lit.pod





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-25 09:02:19 +00:00
Silviu Baranga
6fe310e155 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-22 14:14:49 +00:00
Silviu Baranga
b7c2ed6664 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-22 13:24:43 +00:00
Silviu Baranga
a0c48eb8f6 Added soft fail cases for the disassembler when decoding MUL instructions on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-22 13:14:39 +00:00
Kevin Enderby
f0586f08df Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test 
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-21 20:54:32 +00:00
Silviu Baranga
5c062ad926 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 15:54:56 +00:00
Kevin Enderby
158c8a49c2 Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:33:12 +00:00
Kevin Enderby
b0578512c7 Change ARMInstPrinter::printPredicateOperand() so it will not abort if it 
runs into the undefined 15 condition code value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-01 22:13:02 +00:00
Eli Bendersky
0f0c411079 Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed. 
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 06:28:33 +00:00
James Molloy
3015dfb7d7 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-09 10:56:31 +00:00
Jim Grosbach
e90ac9bce9 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:35:22 +00:00
Owen Anderson
b589be9334 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:55:00 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Benjamin Kramer
70be28a5ad Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:59 +00:00
Owen Anderson
81550dc0a8 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 18:03:14 +00:00
Owen Anderson
60cb643f75 Fix disassembly of some VST1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 22:18:13 +00:00
Owen Anderson
fb6ab2b30e More not-crashing NEON disassembly updates for the vld refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 17:17:32 +00:00
Owen Anderson
017f87cf68 Fix illegal disassembly testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143231 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 21:45:09 +00:00
Owen Anderson
cb9fed6655 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 18:02:13 +00:00
Owen Anderson
03e03b0984 Add testcase for r143162. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 22:54:14 +00:00
Owen Anderson
a7c98f58ea Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 18:04:29 +00:00
Owen Anderson
cd20c58e98 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 22:23:58 +00:00
Owen Anderson
fe0748d696 Fix decoding tests for fixed MSR encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142624 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 22:01:48 +00:00
Jim Grosbach
c66e7afcf2 Thumb2 assembly parsing and encoding for LDC/STC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 20:54:17 +00:00
Jim Grosbach
fbab2206cf Update test for r141704. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 20:18:50 +00:00
James Molloy
acad68da50 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 14:21:38 +00:00
Owen Anderson
21733e8f80 Fix an incorrect decoder test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 23:08:34 +00:00
Owen Anderson
1f24002ed4 Fix incorrect disassembly test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140423 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:05:54 +00:00
Owen Anderson
0781c1f700 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:26:40 +00:00
Owen Anderson
31d485ec9a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:07:25 +00:00