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5625 Commits

Author SHA1 Message Date
Jim Grosbach
6cb4b08182 ARM accept an immediate offset in memory operands w/o the '#'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:14:41 +00:00
Jim Grosbach
5c984e451d ARM enclosing curly braces optional on one-register VLD/VST instruction lists. 
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:45:55 +00:00
Jim Grosbach
eaf2056709 ARM size suffix on VFP single-precision 'vmov' is optional. 
rdar://10435114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144698 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:18:35 +00:00
Jim Grosbach
25e0a87e91 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144695 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:01:30 +00:00
Jim Grosbach
19885de61d ARM alternate size suffices for VTRN instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:49:46 +00:00
Owen Anderson
22925d93e9 Fix a misplaced paren bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144692 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:30:41 +00:00
Jim Grosbach
a68e90c36e ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:29:42 +00:00
Jim Grosbach
bfb0a1717b ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:14:51 +00:00
Jim Grosbach
d2586daf06 ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:02:06 +00:00
Jim Grosbach
7f1ec9570d Thumb2 two-operand 'mul' instruction wide encoding parsing. 
rdar://10449724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:55:16 +00:00
Owen Anderson
b589be9334 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:55:00 +00:00
Jim Grosbach
1de0bd1945 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:29:45 +00:00
Jim Grosbach
c5a6a687fd ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144650 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 17:49:59 +00:00
Jay Foad
bf8356b37c Fix typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 07:50:05 +00:00
Jay Foad
978e0dfe46 Make use of MachinePointerInfo::getFixedStack. This removes all mention 
of PseudoSourceValue from lib/Target/.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 07:34:52 +00:00
Jay Foad
d9190c0f14 Remove some unnecessary includes of PseudoSourceValue.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 07:24:32 +00:00
Evan Cheng
eaa192af18 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 02:12:34 +00:00
Jim Grosbach
bfc9429c2b ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:46:57 +00:00
Jim Grosbach
dd47e0b5d4 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:43:46 +00:00
Jim Grosbach
e052b9afa1 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:32:59 +00:00
Jim Grosbach
04db7f7a7d Add explanatory comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:21:09 +00:00
Jim Grosbach
0530d0d5d9 Split out the plain '.{8|16|32|64}' suffix handling. 
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:20:14 +00:00
Jim Grosbach
ef448767a3 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:11:19 +00:00
Chad Rosier
2c42b8c912 Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:04:09 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Chad Rosier
909cb4f2f2 Add support for inlining small memcpys. 
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:46:17 +00:00
Chad Rosier
e489af8dce Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:34:48 +00:00
Jim Grosbach
02e3d9268f ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:28:39 +00:00
Chad Rosier
57b2997966 Add support for Thumb load/stores with negative offsets. 
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 20:22:27 +00:00
Jim Grosbach
430052b084 Tidy up. 80 column. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 17:52:47 +00:00
Chad Rosier
dc9205d9c2 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 04:09:28 +00:00
Chad Rosier
9eb674880b The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 09:44:21 +00:00
Chad Rosier
a517ab155b Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 05:14:43 +00:00
Chad Rosier
5be833de76 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 04:25:02 +00:00
Chad Rosier
b29b950bf2 Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 02:23:59 +00:00
Daniel Dunbar
b8ebca83f4 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:10:57 +00:00
Jim Grosbach
9588c10b69 ARM refactor simple immediate asm operand render methods. 
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:58:43 +00:00
Jim Grosbach
742c4bac07 Re-apply 144430, this time with the associated isel and disassmbler bits. 
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:31:53 +00:00
Jim Grosbach
4d06138d53 Oops. Missed the isel half of this. revert while I sort that out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:51:31 +00:00
Jim Grosbach
10a630dea6 ARM assembly parsing for VST1 two-register encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:45:47 +00:00
Jim Grosbach
c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:34:43 +00:00
Chad Rosier
11add26ec2 Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:31:03 +00:00
Jim Grosbach
7aef99b677 ARM vldm and vstm VFP instructions can take a data type suffix. 
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.

Partial for rdar://10435264

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:08:10 +00:00
Jim Grosbach
c3937b97c0 Nuke no longer accurate comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:30:06 +00:00
Andrew Trick
95bc85e4ee Preserve MachineMemOperands in ARMLoadStoreOptimizer. 
Fixes PR8113.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:18:09 +00:00
Jim Grosbach
ce485e7f70 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 21:27:40 +00:00
Benjamin Kramer
eea66f63d9 Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144384 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 12:39:41 +00:00
Chad Rosier
1c47de87c7 Rename variables to avoid confusion. No functionallity change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 06:27:41 +00:00
Chad Rosier
a07d3fc693 Add support for using immediates with select instructions. 
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 06:20:39 +00:00
Eli Friedman
15f58c56e9 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 03:16:38 +00:00
Chad Rosier
646abbfa30 When loading a value, treat an i1 as an i8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 02:38:59 +00:00
Chad Rosier
4e89d97e3a Add support for using MVN to materialize negative constants. 
rdar://10412592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:36:21 +00:00
Daniel Dunbar
5ed5506f18 LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:23:56 +00:00
Jim Grosbach
0352b4679e Thumb2 ldm/stm updating w/ one register in the list are LDR/STR. 
rdar://10429490

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144338 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:58:34 +00:00
Jim Grosbach
83ec87755e ARM let processInstruction() tranforms chain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:42:14 +00:00
Jim Grosbach
5402637ff2 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:17:11 +00:00
Jim Grosbach
fae02597bb Thumb1 diagnostics for reglist on PUSH/POP fix. 
Was not checking the first register in the register list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:01:27 +00:00
Jim Grosbach
1b332860ae Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:10:12 +00:00
Chad Rosier
16455ce1a4 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 21:09:49 +00:00
Jim Grosbach
d475f8612b ARM .thumb_func directive for quoted symbol names. 
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.

rdar://10428015

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 20:48:53 +00:00
Jim Grosbach
ee10ff89a2 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 16:44:55 +00:00
Chad Rosier
6cba97c555 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 01:30:39 +00:00
Daniel Dunbar
affc6cf9d2 llvm-build: Add --native-target and --enable-targets options, and add logic to 
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:50:07 +00:00
Daniel Dunbar
c352caf168 llvm-build: Add an explicit component type to represent targets. 
- Gives us a place to hang target specific metadata (like whether the target has a JIT).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:49:51 +00:00
Jim Grosbach
c27f6725b9 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:02:33 +00:00
Jim Grosbach
3c5d6e4df4 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:44:23 +00:00
Eli Friedman
14e809c872 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:36:02 +00:00
Chad Rosier
7346347674 The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. 
rdar://10418009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144213 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 21:30:12 +00:00
Chad Rosier
2f2fe417f9 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 03:22:02 +00:00
Evan Cheng
44ee4714a8 Hide cpu name checking in ARMSubtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 01:57:03 +00:00
Evan Cheng
3568a1051e Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:21:09 +00:00
Chad Rosier
66dc8ca04b ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. 
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:12:00 +00:00
Lang Hames
5207bf2177 Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. 
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 18:56:23 +00:00
Pete Cooper
d752e0f7e6 Added invariant field to the DAG.getLoad method and changed all calls. 
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 18:42:53 +00:00
Eli Friedman
9f1f26aefa Make sure to mark vector extload's as expand on ARM. Fixes PR11319. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 01:43:53 +00:00
Chad Rosier
0eff39f2e2 Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:03:32 +00:00
Chad Rosier
62c8e8e3f6 Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:43:40 +00:00
Benjamin Kramer
70be28a5ad Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:59 +00:00
Benjamin Kramer
5908536673 Replace (Lower|Upper)caseString in favor of StringRef's newest methods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 20:37:06 +00:00
Chad Rosier
42536af5ce Add support for passing i1, i8, and i16 call parameters. Also, be sure to 
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143821 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 20:16:15 +00:00
Chad Rosier
38f5c0da6d Allow i1 to be promoted to i32 for ARM APCS calling convention. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143755 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 00:02:56 +00:00
Chad Rosier
451afbc6a2 Cannot create a result register for non-legal types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 23:45:39 +00:00
Chad Rosier
a4e07270bc When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit 
in a 16-bit immediate.  However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend.  This prevents us from materializing things
such as 'true' (i.e., i1 1).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 23:09:49 +00:00
Chad Rosier
44e895761f Enable support for materializing i1, i8, and i16 integers via move immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 22:29:00 +00:00
Daniel Dunbar
b0d9ce567f build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just 
added a layer of indirection with no value (not even conciseness).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 19:04:23 +00:00
Evan Cheng
c39916b166 Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 01:48:58 +00:00
Chad Rosier
8e4a2e4f73 Indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 00:58:10 +00:00
Chad Rosier
f470cbbad2 Add fast-isel support for returning i1, i8, and i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 00:50:21 +00:00
Dan Gohman
65fd6564b8 Reapply r143206, with fixes. Disallow physical register lifetimes 
across calls, and only check for nested dependences on the special
call-sequence-resource register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 21:49:52 +00:00
Daniel Dunbar
a3a2dfd4a2 build: Add initial cut at LLVMBuild.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 18:53:17 +00:00
Chad Rosier
463fe24f1d Add support for sign-extending non-legal types in SelectSIToFP(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143603 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 02:04:59 +00:00
Lang Hames
a1e78888d9 Fixed parameter name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 23:37:04 +00:00
Lang Hames
1a1d1fcc0b Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 22:52:45 +00:00
Chad Rosier
e07cd5e40a Add support for comparing integer non-legal types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 18:08:25 +00:00
Owen Anderson
81550dc0a8 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 18:03:14 +00:00
Owen Anderson
244006db5c The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 17:46:18 +00:00
Owen Anderson
e31b42a6f5 Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 17:41:23 +00:00
Chad Rosier
87633026d6 Factor out an EmitIntExt function. No functionality change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143547 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 17:20:24 +00:00
Chad Rosier
0d7b231c9b Factor out a SelectTrunc function. No functionality change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143523 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 00:18:48 +00:00